CN105047120A - Grid driving circuit, driving method thereof and display device - Google Patents
Grid driving circuit, driving method thereof and display device Download PDFInfo
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Abstract
The embodiment of the invention provides a gate driving circuit, which comprises a plurality of gate driving units cascaded along a first direction, wherein at least one gate driving unit comprises a first scanning signal input end, a second scanning signal input end, a first clock signal input end, a second clock signal input end, a reset signal input end, a first input end, a second input end and an output end, wherein the output end of a previous-stage gate driving unit arranged along the first direction is electrically connected with the first input end of a next-stage gate driving unit, and the second input end of the previous-stage gate driving unit arranged along the first direction is electrically connected with the output end of the next-stage gate driving unit; the first input end of the first stage of grid driving unit and the second input end of the last stage of grid driving unit which are arranged along the first direction are electrically connected with each other and connected to a trigger signal end; and the reset signal input ends of the gate driving units are electrically connected to each other and connected to a reset signal end.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving circuit in a display driving circuit, a driving method thereof, and a display device including the gate driving circuit.
Background
In recent years, with the development of display technology, the application of display panels is becoming more and more widespread. In the related art, a display panel includes a plurality of scanning lines (gate lines), a plurality of signal lines (data lines), a scanning line (gate line) driving circuit, and a signal line (data line) driving circuit. Each of the driving circuits is located in a non-display region of the display device and is composed of a plurality of elements. When the display panel is in operation, a gate driving circuit in the display panel generates a scan signal to drive each gate line in the array substrate one by one, so that a data signal can be transmitted to each pixel unit in the array substrate. The scanning signal is generated by a gate driving unit with a shift register function in the gate driving circuit.
Fig. 1 is a schematic diagram of a gate driving circuit of the prior art. As shown in fig. 1, the gate driving circuit includes cascaded gate driving units electrically connected to each gate line and a dummy gate driving unit not connected to a gate line, and the dummy gate driving unit does not generate a scan signal and only provides a trigger signal for a next gate driving unit or a reset signal for a previous gate driving unit, but the occupied space of the dummy gate driving unit is not small, so that the number of gate driving units restricts the reduction of the gate driving circuit and the reduction of the frame of the display screen.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is that the number of internal devices in the driving circuit in the prior art is large, which is not favorable for reducing the frame area of the display panel.
In order to solve the above technical problem, an embodiment of the present invention provides a gate driving circuit, including a plurality of gate driving units cascaded along a first direction, at least one of the gate driving units includes a first scanning signal input terminal, a second scanning signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a reset signal input terminal, a first input terminal, a second input terminal, and an output terminal, wherein the output terminal of a previous gate driving unit arranged along the first direction is electrically connected to the first input terminal of a next gate driving unit, and the second input terminal of a previous gate driving unit arranged along the first direction is electrically connected to the output terminal of the next gate driving unit; the first input end of the first stage of grid driving unit and the second input end of the last stage of grid driving unit which are arranged along the first direction are electrically connected with each other and connected to a trigger signal end; and the reset signal input ends of the gate driving units are electrically connected to each other and connected to a reset signal end.
The gate driving circuit provided by the embodiment of the invention reduces the dummy gate driving units while ensuring the stability of the circuit in the reset stage, thereby reducing the area occupied by the gate driving circuit and effectively reducing the frame area.
The embodiment of the invention also provides a display device, which comprises a display area and a non-display area surrounding the display area, wherein the gate driving circuit is arranged on at least one side of the non-display area.
According to the display device provided by the embodiment of the invention, the area of the gate drive circuit in the non-display area is smaller, and the frame width of the display device is effectively reduced. In addition, under the condition that the width of the frame is limited, the display device provided by the embodiment of the invention is more beneficial to realizing higher resolution.
The embodiment of the invention also provides a driving method of the grid driving circuit, and one frame scanning period comprises a first reset stage, a shift stage and a second reset stage.
According to the driving method of the gate driving circuit, provided by the embodiment of the invention, the resetting is performed twice before and after the shifting stage, and the resetting mode does not need to use an additional dummy gate driving unit for resetting, so that the area of the gate driving circuit is effectively reduced, and the area of a frame is reduced.
Drawings
FIG. 1 is a diagram of a gate driving circuit in the prior art;
fig. 2 is a schematic diagram of a gate driving unit according to an embodiment of the invention;
fig. 3 is a timing diagram illustrating an operation of a gate driving unit according to an embodiment of the invention;
fig. 4 is a schematic diagram of a gate driving circuit according to an embodiment of the invention;
FIG. 5 is a timing chart of the operation of the gate driving circuit in FIG. 4 when scanning in a first direction;
FIG. 6 is a timing chart of the operation of the gate driving circuit in FIG. 4 when scanning in the second direction;
fig. 7 is a top view of a display device according to an embodiment of the invention;
fig. 8 is a top view of another display device according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a gate driving circuit, which comprises a plurality of gate driving units cascaded along a first direction, wherein at least one gate driving unit comprises a first scanning signal input end, a second scanning signal input end, a first clock signal input end, a second clock signal input end, a reset signal input end, a first input end, a second input end and an output end, wherein the output end of a previous-stage gate driving unit arranged along the first direction is electrically connected with the first input end of a next-stage gate driving unit, and the second input end of the previous-stage gate driving unit arranged along the first direction is electrically connected with the output end of the next-stage gate driving unit; the first input end of the first stage of grid driving unit and the second input end of the last stage of grid driving unit which are arranged along the first direction are electrically connected with each other and connected to a trigger signal end; and the reset signal input ends of the gate driving units are electrically connected to each other and connected to a reset signal end.
The gate driving circuit provided by the embodiment of the invention reduces the dummy gate driving units while ensuring the stability of the circuit in the reset stage, thereby reducing the area occupied by the gate driving circuit and effectively reducing the frame area.
The embodiment of the invention also provides a display device, which comprises a display area and a non-display area surrounding the display area, wherein the gate driving circuit is arranged on at least one side of the non-display area.
According to the display device provided by the embodiment of the invention, the area of the gate drive circuit in the non-display area is smaller, and the frame width of the display device is effectively reduced. In addition, under the condition that the width of the frame is limited, the display device provided by the embodiment of the invention is more beneficial to realizing higher resolution.
The embodiment of the invention also provides a driving method of the grid driving circuit, and one frame scanning period comprises a first reset stage, a shift stage and a second reset stage.
According to the driving method of the gate driving circuit, provided by the embodiment of the invention, the resetting is performed twice before and after the shifting stage, and the resetting mode does not need to use an additional dummy gate driving unit for resetting, so that the area of the gate driving circuit is effectively reduced, and the area of a frame is reduced.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 2, the gate driving unit according to the embodiment of the present invention includes first to ninth transistors T1 to T9, a first capacitor C1, and a second capacitor C2.
The gate of the first transistor T1 is electrically connected to the first input terminal Gn-1/STV1, and the first pole of the first transistor T1 is electrically connected to the first scanning signal input terminal DIR 1; the second pole of the first transistor T1 electrically connects the second pole of the second transistor T2 to point P.
The gate of the second transistor T2 is electrically connected to the second input terminal Gn +1/STV2, and the first pole of the second transistor is electrically connected to the second scan signal input terminal DIR 2.
The first scanning signal input terminal DIR1 and the second scanning signal input terminal DIR2 are used for controlling the signal access circuit of the first input terminal Gn-1/STV1 or the second input terminal Gn +1/STV2, namely, the circuit is switched under the scanning mode of two directions, and when the circuit is applied to a display device, bidirectional selective scanning can be realized.
With continued reference to fig. 2, the gate of the third transistor T3 is electrically connected to the second pole of the first capacitor C1, i.e., the Q point in the circuit; a first pole of the third transistor T2 is electrically connected to a first potential VGL, and a second pole of the third transistor T3 is electrically connected to the first transistor T1 and the second pole T2 of the second transistor T2, i.e., a P point in the circuit.
A gate of the fourth transistor T4 and a gate of the fifth transistor T5 are electrically connected to a Reset signal terminal Reset; a first pole of the fourth transistor T4 is electrically connected to a first potential VGL, and a second pole of the fourth transistor T4 is electrically connected to second poles of the first transistor T1 and the second transistor T2, i.e., a point P in the circuit. The fourth transistor T4 and the fifth transistor T5 are controlled by a reset signal to reset the circuit before the shift phase begins.
A gate of the fifth transistor T5 is electrically connected to the Reset signal terminal Reset, a first pole of the fifth transistor T5 is electrically connected to the first potential VGL, and a second pole of the fifth transistor is electrically connected to the output terminal Gn of the gate driving unit;
the gate of the sixth transistor T6 is electrically connected to the second pole, point P in the circuit, of the first transistor T1 and the second transistor T2; a first pole of the sixth transistor T6 is electrically connected to the first potential VGL, and a second pole of the sixth transistor T6 is electrically connected to the second pole of the first capacitor C1, i.e., the Q point in the circuit.
The gate of the seventh transistor T7 is electrically connected to the second pole of the first capacitor C1, i.e., the Q point in the circuit; a first pole of the seventh transistor T7 is electrically connected to the first potential VGL, and a second pole of the seventh transistor T7 is electrically connected to the output terminal Gn of the gate driving unit.
The gate of the eighth transistor T8 is electrically connected to the second clock signal input terminal CLK 2; a first pole of the eighth transistor T8 is electrically connected to the first potential VGL, and a second pole of the eighth transistor T8 is electrically connected to the output terminal Gn of the gate driving unit.
The gate of the ninth transistor T9 is electrically connected to the second pole, point P in the circuit, of the first transistor T1 and the second transistor T2; a first pole of the ninth transistor T9 is electrically connected to the first clock signal input terminal CLK1, and a second pole of the ninth transistor T9 is electrically connected to the output terminal Gn of the gate driving unit.
A first pole of the first capacitor C1 is electrically connected to a first pole of the ninth transistor T9, i.e., the first clock signal input terminal CLK 1; the second pole of the first capacitor C2 is electrically connected to the gate of the third transistor T3, i.e., the Q point in the circuit.
A first pole of the second capacitor C2 is electrically connected to a second pole, point P in the circuit, of the first transistor T1 and the second transistor T2; the second pole of the second capacitor C2 is electrically connected to the output Gn of the gate driving unit.
Further, the first to ninth transistors T1 to T9 are N-type transistors (NMOS), and the first potential VGL is a low level potential.
In the gate driving unit provided by the embodiment of the invention, the Reset signal terminal Reset can be switched on in the Reset phase, that is, the fourth transistor T4 and the fifth transistor T5 are turned on, and the point P and the output terminal Gn are switched on to the first potential VGL. After the reset phase is completed, i.e., after the fourth transistor T4 and the fifth transistor T5 are turned off, the first clock signal input terminal CLK1 is coupled to the first clock signal, and the second clock signal input terminal CLK2 is coupled to the second clock signal, which has an opposite phase to the first clock signal.
The first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 may be switched immediately when the reset signal and the clock signal are switched, or may have a certain blank period. As shown in fig. 3, during the first Reset period R1 in one frame period, the Reset signal terminal Reset, the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 all switch on the Reset signal; during the shift stage S of a frame, the first clock signal input terminal CLK1 is asserted, the second clock signal input terminal CLK2 is asserted, and the first clock signal and the second clock signal are inverted. The first Reset stage R1 and the shift stage S have a certain blank space, and the Reset signal terminal Reset, the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are all connected to low level potential. In other embodiments of the present invention, there may be no blank space, i.e. the shift stage S is entered immediately after the first reset stage R1 is finished.
Fig. 3 shows a timing diagram of the ports of the gate driving unit in fig. 2, i.e. a timing diagram when the first scan signal input terminal DIR1 is switched to a high level, the second scan signal input terminal DIR2 is switched to a low level, and the first voltage VGL is a low level, i.e. a timing diagram of the first input terminal Gn-1/STV1 is switched to a circuit. In other embodiments of the present invention, the first scan signal input terminal DIR1 may be switched to a low level, and the second scan signal input terminal DIR2 may be switched to a high level, i.e., the second input terminal Gn +1/STV2 may be switched to a signal switching circuit.
With continued reference to fig. 3, during the first Reset phase R1, the Reset signal terminal Reset is connected to the Reset signal, and the Reset signal is at a high level. At this time, the fourth transistor T4 is turned on and the fifth transistor T5 is turned on. The fourth transistor T4 switches the first potential VGL to the low level potential P point of the circuit, and the circuit is reset. The fifth transistor T5 switches the low-level potential switched in by the first potential VGL into the output terminal Gn of the gate driving unit.
During the shift stage S, the first pole of the first capacitor C1 is electrically connected to the first clock signal input terminal CLK1, and is at a low level. The first clock signal input terminal CLK1 receives the first clock signal, the second clock signal input terminal CLK2 receives the second clock signal, and the first input terminal Gn-1/STV1 receives the first input signal, which is at a high level. The first transistor T1 is turned on to switch the high level potential of the first scan signal input terminal DIR1 to the P point. The ninth transistor T9 is turned on to switch the first clock signal inputted from the first clock signal input terminal CLK1 to the output terminal Gn of the gate driving unit; meanwhile, the second clock signal inputted from the second clock signal input terminal CLK2 is inputted to the gate of the seventh transistor T7, and at this time, the second clock signal is at a high level, and the eighth transistor T8 is turned on, so that the low level potential inputted from the first potential VGL is transmitted to the output terminal Gn of the gate driving unit. At this time, the first clock signal and the first potential are both low-level potentials, so that the output terminal Gn of the gate driving unit outputs the low-level potential. The first pole of the second capacitor C2 is electrically connected to the point P and is at a high level potential, the second pole of the second capacitor C2 is electrically connected to the output terminal Gn of the gate driving unit and is at a low level potential, and the second capacitor C2 is charged.
With continued reference to the shift stage S in fig. 3, when the input signal inputted from the first input terminal Gn-1/STV1 changes to a low level potential, the first transistor T1 is turned off, the point P keeps a high level potential due to the discharge of the second capacitor C2, and the ninth transistor T9 turns on the first clock signal inputted from the first clock signal input terminal CLK1 to be inputted to the output terminal Gn of the gate driving unit; meanwhile, a second clock signal input by the second clock signal input terminal CLK2 is connected to the gate of the eighth transistor T8, at this time, the second clock signal is at a low level potential, and the eighth transistor T8 is turned off, so that the output of the output terminal Gn of the gate driving unit is not affected; meanwhile, the point Q keeps a low level potential, and the third transistor T3 and the seventh transistor T7 are turned off, so that the output of the output terminal Gn of the gate driving unit is not affected; at this time, the first clock signal is at a high level potential, so that the output terminal Gn of the gate driving unit outputs the high level potential, that is, the gate driving unit shifts the high level potential of the input signal to the output terminal Gn for outputting in the shifting stage S.
In the second Reset phase R2, the Reset signal terminal Reset is connected to the Reset signal, and the Reset signal is at a high level. At this time, the fourth transistor T4 is turned on and the fifth transistor T5 is turned on. The fourth transistor T4 switches the first potential VGL to the low level potential P point of the circuit, and the circuit is reset. The fifth transistor T5 switches the low-level potential switched in by the first potential VGL into the output terminal Gn of the gate driving unit.
The embodiment of the present invention further provides a gate driving circuit, which includes a plurality of gate driving units arranged in cascade along a first direction, and the gate driving circuit provided by the embodiment of the present invention is described by taking three gate driving units as an example.
As shown IN fig. 4, the gate driving units cascaded IN the first direction are P1, P2, P3, and taking the gate driving unit P1 as an example, the gate driving unit P1 includes a first scan signal input terminal, a second scan signal input terminal, a first clock signal input terminal CLK1, a second clock signal input terminal CLK2, a Reset signal input terminal Reset, a first input terminal P1-IN1, a second input terminal P1-IN2, and an output terminal G1, wherein the output terminal G1 of the first stage gate driving unit P1 arranged IN the first direction is electrically connected to the first input terminal P2-IN1 of the next stage gate driving unit P2, and the second input terminal PI-IN2 of the gate driving unit P1 is electrically connected to the output terminal G2 of the next stage gate driving unit P2; the first input terminal P1-IN1 of the first stage gate driving unit P1 and the second input terminal PN-IN2 of the last stage gate driving unit PN arranged IN the first direction are electrically connected to each other and to a trigger signal terminal; and the Reset signal input terminals Reset of the gate driving units P1 … PN are electrically connected to each other and to a Reset signal terminal.
First clock signal input ends of odd-numbered gate driving units arranged along the first direction are electrically connected with each other and are connected to a first clock signal end, and second clock signal input ends of the odd-numbered gate driving units are electrically connected with each other and are connected to a second clock signal end; first clock signal input ends of even-numbered gate driving units arranged along the first direction are electrically connected to each other and to a second clock signal end, and second clock signal input ends of the even-numbered gate driving units are electrically connected to each other and to the first clock signal end. With continued reference to fig. 4, the first clock signal input terminals CLK1 of the first stage gate driving unit P1 and the third stage gate driving unit P3 in the first direction are electrically connected to each other and to the first clock signal terminal CK1, and the second clock signal input terminals CLK2 of the first stage gate driving unit P1 and the third stage gate driving unit P3 in the first direction are electrically connected to each other and to the second clock signal terminal CK 2; the first clock signal input terminals CLK1 of the even-numbered stage gate driving units P2 arranged in the first direction are electrically connected to each other and to the second clock signal terminal CK2, and the second clock signal input terminals CLK2 of the even-numbered stage gate driving units are electrically connected to each other and to the first clock signal terminal CK 1.
The first scan signal input terminals DIR1 of the gate driving units of each stage are electrically connected to each other and to a first scan signal input terminal, and the second scan signal input terminals DIR2 of the gate driving units of each stage are electrically connected to each other and to a second scan signal input terminal.
The first clock signal output by the first clock signal terminal and the second clock signal output by the second clock signal terminal have opposite phases, and the first scanning signal output by the first scanning signal terminal and the second scanning signal output by the second scanning signal terminal have opposite phases.
The gate driving circuit provided by the embodiment of the invention reduces the dummy gate driving units while ensuring the stability of the circuit in the reset stage, thereby reducing the area occupied by the gate driving circuit and effectively reducing the frame area.
The present embodiment further provides a driving method of the gate driving circuit, wherein one frame scanning period includes a first reset phase, a shift phase and a second reset phase. The shift stage further comprises a shift stage in the first direction: and applying a trigger signal to a first input end of the first-stage gate driving unit and a second input end of the last-stage gate driving unit along the first direction.
The shifting stage further comprises a shifting stage in the second direction: and applying trigger signals to the first input end of the first stage of gate driving unit and the second input end of the last stage of gate driving unit along the second direction.
And in the first reset phase and the second reset phase, a reset signal is simultaneously applied to the reset signal input end of the gate driving unit of each stage.
Referring to fig. 4, 5 and 6, fig. 5 and 6 show timing diagrams of the gate driving circuit in fig. 4, the first scan signal input terminal DIR1 is connected to the first scan signal, the second scan signal input terminal DIR2 is connected to the second scan signal, and the first voltage VGL is a low level voltage; the gate driving circuit can drive in a first direction or a second direction, wherein the second direction is opposite to the first direction.
Fig. 5 is a timing diagram of driving in a first direction, and a Reset signal is inputted to a Reset signal input terminal Reset in a first Reset phase R1; as described in the foregoing description of the first reset phase R1 in fig. 3, when the reset signal is at the high level, the fourth transistor T4 and the fifth transistor T5 of each gate driving unit are turned on, the whole gate driving circuit is reset, and the output terminal of each gate driving unit outputs the low level potential.
IN the shift stage S, the first clock signal input terminal CLK1 is connected to the first clock signal CK1, the second clock signal input terminal CLK2 is connected to the second clock signal CK2, the first input terminal of the first gate driving unit IN the first direction is connected to the trigger signal, i.e., the first input terminal P1-IN1 of the first stage gate driving unit P1 IN the first direction is connected to the trigger signal STV1, the second input terminal PN-IN2 of the last stage gate driving unit PN IN the first direction is connected to the trigger signal STV1, when the trigger signal is a high level potential, as described IN the shift stage S IN fig. 3, the first stage gate driving unit P1 IN the first direction shifts the high level of the trigger signal and outputs the high level potential, i.e., the output terminal G1 of the first stage gate driving unit P1 outputs the high level potential when the trigger signal is changed to the low level, and according to the above steps, the second stage gate driving unit P2 and the first stage gate driving unit P3 IN the first direction output the high level potentials sequentially, i.e. sequentially driving the respective gate driving units in a first direction. When the trigger signal STV1 inputted to the second input terminal PN-IN2 of the last stage of gate driving unit PN is a high level signal, referring to fig. 2, the second input terminal Gn +1/STV2 of the gate driving unit PN is inputted with a high level, the second transistor T2 is turned on, the second scan signal DIR2 is inputted, and according to the timing diagram 5, the second scan signal DIR2 keeps a low level, the output terminal of the last stage of gate driving unit PN keeps a low level, that is, no scan signal is generated until the first input terminal PN-IN1 of the last stage of gate driving unit PN is inputted with a high level, and then the scan signal is generated IN accordance with the previous stage of driving.
Since the gate driving circuit provided in this embodiment has no dummy gate driving unit, the last gate driving unit needs to be Reset again after generating the scan signal, that is, the second Reset stage R2, at this time, the Reset signal input terminal Reset is connected to the Reset signal; as described in the foregoing description of the first reset phase R1 in fig. 3, when the reset signal is at the high level, the fourth transistor T4 and the fifth transistor T5 of each gate driving unit, including the last gate driving unit, are turned on, the whole gate driving circuit is reset, and the output terminal of each gate driving unit outputs the low level potential. The one-frame scan period frame1 includes a first reset phase R1, a shift phase S, and a second reset phase R2.
Fig. 6 is a timing diagram of driving in the second direction, as shown in fig. 6, the Reset signal terminal Reset is switched in the Reset signal during the first Reset period R1; as described in the reset phase R in fig. 3, when the reset signal is at the high level, the fourth transistor T4 and the fifth transistor T5 of each gate driving unit are turned on, the whole gate driving circuit is reset, and the output end of each gate driving unit outputs the low level potential.
In the shift stage S, the first scan signal input terminal DIR1 is connected to a low level potential, the second scan signal input terminal DIR2 is connected to a high level potential, and the second transistor of each stage of gate driving unit is turned on to connect to the trigger signal of each stage of gate driving unit. The first clock signal input terminal CLK1 is asserted to the first clock signal CK1, the second clock signal input terminal CLK2 is asserted to the second clock signal CK2, the second input terminal of the first gate driving unit in the second direction is asserted to the trigger signal, that is, the second input terminal PN-IN2 of the first stage gate driving unit PN IN the second direction is connected to the triggering signal STV2, the first input terminal P1-IN1 of the last stage gate driving unit P1 IN the first direction is connected to the triggering signal STV2, and when the STV2 triggering signal is at a high level, unlike the shift stage S of FIG. 3, which is a port only connected to the trigger signal, the circuit operation in the gate driving unit P3 is the same as the shift stage of FIG. 3, therefore, the first stage gate driving unit PN in the second direction shifts the high level of the trigger signal and outputs the shifted trigger signal, that is, the output terminal GN of the gate driving unit PN outputs a high level potential when the trigger signal is converted to a low level potential. According to the above steps, the second gate driving unit P2 of the second stage and the third gate driving unit P1 in the second direction sequentially output high-level potentials, i.e., sequentially drive the respective gate driving units in the second direction. When the trigger signal STV2 inputted from the first input terminal P1-IN1 of the last stage of gate driving unit P1 is a high level signal, referring to fig. 2, the first input terminal Gn-1/STV1 of the gate driving unit is inputted high level, the first transistor T1 is turned on, the first scan signal DIR1 is inputted, according to the timing diagram 6, at this time, the first scan signal DIR1 keeps low level, the output terminal of the last stage of gate driving unit P1 keeps low level, that is, no scan signal is generated, until the second input terminal P1-IN2 of the last stage of gate driving unit P1 is inputted high level, and then it generates a scan signal according to the previous stage of driving method. The one-frame scan period frame1 includes a first reset phase R1, a shift phase S, and a second reset phase R2.
Since the gate driving circuit provided in this embodiment has no dummy gate driving unit, the last gate driving unit needs to be Reset again after generating the scan signal, that is, the second Reset stage R2, at this time, the Reset signal input terminal Reset is connected to the Reset signal; as described in the foregoing description of the first reset phase R1 in fig. 3, when the reset signal is at the high level, the fourth transistor T4 and the fifth transistor T5 of each gate driving unit, including the last gate driving unit, are turned on, the whole gate driving circuit is reset, and the output terminal of each gate driving unit outputs the low level potential.
The embodiment of the invention provides a driving method of a gate driving circuit, which carries out resetting twice before and after a shifting stage, and the resetting mode does not need to use an additional dummy gate driving unit for resetting, thereby effectively reducing the area of the gate driving circuit and reducing the area of a frame.
The invention also provides a display device, which comprises a display area and a non-display area surrounding the display area, wherein the gate driving circuit is arranged on at least one side of the non-display area. As shown in fig. 7 and 8, the display device includes a display area 11 and a non-display area 12 surrounding the display area. In fig. 7, the non-display region 12 on the display region 11 side is provided with a gate driver circuit 13, i.e., driving by one side. In fig. 8, the non-display region 12 on both sides of the display region 11 is provided with gate driving circuits 13a and 13b, i.e., driving by both sides. Besides one grid drive circuit is respectively arranged in the single-side drive and the double-side drive, a plurality of grid drive circuits or grid drive circuits can be arranged in non-display areas on other sides.
Further, as shown in fig. 7 and 8, the display region 11 includes a plurality of scan lines 14, a plurality of data lines 15, and an array-type pixel region 16 enclosed by the scan lines 14 and the data lines 15, and the output terminal of each stage of the gate driving unit in the gate driving circuits 13, 13a, and 13b is electrically connected to one scan line 14.
According to the display device provided by the embodiment of the invention, the gate driving unit in the gate driving circuit reduces the dummy gate driving unit while ensuring the stability of the circuit in the reset stage, so that the area occupied by the gate driving unit and the gate driving circuit is reduced, and the width of a frame is effectively reduced. In addition, under the condition that the width of the frame is limited, the display device provided by the embodiment of the invention is more beneficial to realizing higher resolution.
It should be noted that the above embodiments can be used for reference and comprehensive use. Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (13)
1. A gate driving circuit comprises a plurality of gate driving units cascaded along a first direction, at least one of the gate driving units comprises a first scanning signal input terminal, a second scanning signal input terminal, a first clock signal input terminal, a second clock signal input terminal, a reset signal input terminal, a first input terminal, a second input terminal and an output terminal,
the output end of the previous stage grid electrode driving unit arranged along the first direction is electrically connected with the first input end of the next stage grid electrode driving unit, and the second input end of the previous stage grid electrode driving unit arranged along the first direction is electrically connected with the output end of the next stage grid electrode driving unit;
the first input end of the first stage of grid driving unit and the second input end of the last stage of grid driving unit which are arranged along the first direction are electrically connected with each other and connected to a trigger signal end; and is
The reset signal input ends of the gate driving units are electrically connected to each other and connected to a reset signal end.
2. The gate driving circuit according to claim 1, wherein first clock signal input terminals of the odd-numbered stage gate driving units arranged in the first direction are electrically connected to each other and to a first clock signal terminal, and second clock signal input terminals of the odd-numbered stage gate driving units are electrically connected to each other and to a second clock signal terminal; first clock signal input ends of even-numbered gate driving units arranged along the first direction are electrically connected to each other and to a second clock signal end, and second clock signal input ends of the even-numbered gate driving units are electrically connected to each other and to the first clock signal end.
3. A gate driving circuit as claimed in claim 2, wherein the first scan signal input terminals of the gate driving units of each stage are electrically connected to each other and to a first scan signal terminal, and the second scan signal input terminals of the gate driving units of each stage are electrically connected to each other and to a second scan signal terminal.
4. The gate driving circuit as claimed in claim 3, wherein a first clock signal output from the first clock signal terminal is opposite in phase to a second clock signal output from the second clock signal terminal, and a first scan signal output from the first scan signal terminal is opposite in phase to a second scan signal output from the second scan signal terminal.
5. The gate drive circuit of claim 1, wherein the gate drive unit comprises: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor; wherein,
a gate of the first transistor is electrically connected to a first input terminal, a first pole of the first transistor is electrically connected to a first scanning signal input terminal, and a second pole of the first transistor is electrically connected to a second pole of the second transistor;
the grid electrode of the second transistor is electrically connected with the second input end, and the first electrode of the second transistor is electrically connected with the second scanning signal input end;
a gate of the third transistor is electrically connected to a second pole of the first capacitor, a first pole of the third transistor is electrically connected to a first potential, and a second pole of the third transistor is electrically connected to second poles of the first transistor and the second transistor;
a gate of the fourth transistor is electrically connected to the reset signal terminal and a gate of the fifth transistor, a first pole of the fourth transistor is electrically connected to the first potential, and a second pole of the fourth transistor is electrically connected to the second poles of the first transistor and the second transistor;
a gate of the fifth transistor is electrically connected to the reset signal terminal, a first pole of the fifth transistor is electrically connected to the first potential, and a second pole of the fifth transistor is electrically connected to the output terminal of the gate driving unit;
a gate of the sixth transistor is electrically connected to second poles of the first and second transistors, a first pole of the sixth transistor is electrically connected to the first potential, and a second pole of the sixth transistor is electrically connected to the second pole of the first capacitor;
a gate of the seventh transistor is electrically connected to the second pole of the first capacitor, a first pole of the seventh transistor is electrically connected to the first potential, and a second pole of the seventh transistor is electrically connected to the output terminal of the gate driving unit;
the grid electrode of the eighth transistor is electrically connected with the second clock signal input end; a first pole of the eighth transistor is electrically connected to the first potential, and a second pole of the eighth transistor is electrically connected to an output terminal of the gate driving unit;
a gate of the ninth transistor is electrically connected to the second poles of the first and second transistors; a first pole of the ninth transistor is electrically connected to the first clock signal input end, and a second pole of the ninth transistor is electrically connected to the output end of the gate driving unit;
the first pole of the first capacitor is electrically connected with the first clock signal input end; the second pole of the first capacitor is electrically connected with the grid electrode of the third transistor;
a first pole of the second capacitor electrically connects the first transistor and a second pole of the second transistor; and the second pole of the second capacitor is electrically connected with the output end of the grid driving unit.
6. The gate driver circuit according to claim 5, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all N-type transistors.
7. The gate drive circuit according to any one of claims 3 or 4, wherein the first scan signal and the second scan signal control the gate drive circuit to scan in the first direction or the second direction; wherein
The second direction is opposite to the first direction.
8. A display device includes a display area and a non-display area surrounding the display area,
wherein the gate driving circuit according to any one of claims 1 to 7 is disposed at least one side of the non-display region.
9. The display device according to claim 8, wherein the display region includes a plurality of scan lines, a plurality of data lines, and a pixel region surrounded by the scan lines and the data lines, and an output terminal of the gate driving unit of each stage is electrically connected to one scan line.
10. A driving method of the gate driving circuit as claimed in claim 1, wherein one frame scanning period includes a first reset phase, a shift phase and a second reset phase.
11. The driving method of claim 10, wherein the shifting stage further comprises a shifting stage in the first direction:
and applying a trigger signal to a first input end of the first-stage gate driving unit and a second input end of the last-stage gate driving unit along the first direction.
12. The driving method of claim 10, wherein the shifting stage further comprises a shifting stage in the second direction:
and applying trigger signals to the first input end of the first stage of gate driving unit and the second input end of the last stage of gate driving unit along the second direction.
13. The driving method according to claim 10, wherein a reset signal is applied to the reset signal input terminal of the gate driving unit of each stage at the same time at the time of the first reset phase and the second reset phase.
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