CN105024699A - Dual-slope integrating analog-to-digital converter based on switch capacitor feedback digital-to-analog conversion - Google Patents
Dual-slope integrating analog-to-digital converter based on switch capacitor feedback digital-to-analog conversion Download PDFInfo
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Abstract
The invention provides a dual-slope integrating analog-to-digital converter based on switch capacitor feedback digital-to-analog conversion. The dual-slope integrating analog-to-digital converter comprises an integrator composed of a switch capacitor feedback digital-to-analog conversion module and a capacitor, an amplifier, a comparator, a digital control and counting module and the switch capacitor feedback digital-to-analog conversion module. An input signal is loaded on the integrator composed of the switch capacitor feedback digital-to-analog conversion module and the capacitor. The digital control and counting module starts counting. After preset time, the switch capacitor feedback digital-to-analog conversion module is controlled to load one reverse-polarity reference voltage on the capacitor. The average values of the accumulated charges and input of the integrator are in direct proportion during the time period, integration of reference voltage is reverse slope of slope VREF/RC and the digital control and counting module starts counting from 0 at the time. When output of the integrator reaches 0, counting stops and an analog circuit is reset. Problems of integrator saturation and post failure can be solved by the dual-slope integrating analog-to-digital converter based on switch capacitor feedback digital-to-analog conversion so that error of current at nA or pA level can be reduced and area of a chip can also be reduced.
Description
Technical field
The invention belongs to electronic circuit field, relate more specifically to a kind of two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion.
Background technology
Integral analogue-to-digital converter is at low speed, field of high-precision measurement has a wide range of applications, particularly there are simple integral and double integrator two kinds of conversion regimes at digital instrument fields of measurement integral analogue-to-digital converter, the operation principle of simple integral analog to digital converter is that the signal of telecommunication be converted first is become a period of time interval, and then the time interval is counted, thus indirectly analog quantity is converted to a kind of conversion method of digital quantity, its major defect is that conversion accuracy is not high, mainly be subject to slope voltage generator, the impact of comparator precision and clock pulse stability, in order to improve the conversion accuracy of integral analogue-to-digital converter under similarity condition, double integrator pattern number converter can be adopted, dual integ ration ADC is by twice integration to analog input signal, the error that partial offset produces due to ramp generator, " feature of double integrator pattern number converter shows: precision is higher to improve conversion accuracy, 22 can be reached, antijamming capability is strong, due to the effect of integrating capacitor, and can significantly damp high-frequency noise.But its conversion speed is comparatively slow, and conversion accuracy reduces with the increase of switching rate, so this transducer is mainly used in the conversion art of low speed, as fields of measurement.
The emphasis of dual integ ration ADC is exactly the integrator of its inside, and the performance of integrator will see amplifier certainly, and also have, the BUFFER playing buffer action in system also has impact to the performance of system.
As shown in Figure 1, input signal is added on integrator the structure of concrete double integrator pattern number converter, and unison counter starts counting.After predetermined time (T), the reference voltage of a reversed polarity is added on integrator.Now between the stored charge of integrator and input at this moment, the mean value of section (T) is directly proportional.The backslash slope of the integration of reference voltage to be slope be VREF/RC.This hour counter is again from 0 counting.When integrator output reaches 0, counting stops, and resets analog circuit.Because the increase of electric charge and VIN × T are directly proportional, and be directly proportional with the electric charge loss measured and VREF × tx, result is directly proportional relative to full-scale count value and tx/T=VIN/VREF.If the output of counter is binary number, the binary number of Here it is input voltage is expressed.
Traditional two slopes integrating analog to digital converter is existing defects when measuring high-precision current sensor and coming: 1. carry out signal transacting again after being difficult to convert voltage to when electric current is in nA or pA rank; 2. R(resistance) and C(electric capacity) integrator that formed is easy to enter saturation condition when curent change is larger, analog to digital converter loses function; 3. resistance or electric capacity are too large cannot be integrated on very little chip, especially on cell phone type chip later.
Summary of the invention
1, object of the present invention.
The present invention in order to solve the excessive problem of the error of electric current when nA or pA rank, the saturated rear inefficacy of integrator and chip area, and proposes a kind of two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion.
2, the technical solution adopted in the present invention.
Based on two slopes integrating analog to digital converter of switching capacity feedback coefficient mode convertion, comprise the integrator be made up of switching capacity feedback D/A converter module and electric capacity, amplifier, comparator, digital control and counting module, switching capacity feedback D/A converter module, input signal is added in and feeds back D/A converter module by switching capacity, on the integrator that electric capacity is formed, digital controlly start to count with counting module, after the scheduled time, a reversed polarity reference voltage is carried on electric capacity by control switch capacitive feedback D/A converter module, now between the stored charge of integrator and input at this moment, the mean value of section is directly proportional, the backslash slope of the integration of reference voltage to be slope be VREF/RC, now digital controlly to count from 0 with counting module, when integrator output reaches 0, counting stops, reset analog circuit.
Further, described Preset Time is regulated and controled with counting module by digital control, thus control the time of integration.
Further, increase and the input voltage × time of the electric charge of integrator are directly proportional, and to lose with the electric charge measured and contrast potential × contrast potential time is directly proportional, result be relative to full-scale count value and contrast potential input time/input voltage time=input voltage/contrast potential is directly proportional.
Further, digital control is binary number with the output of counting module.
Further, when being stored on electric capacity when carrying out the anti-integration of anomalous integral, offset voltage is offset.
Further, described comparator is detected when anti-integration and judges whether anti-integral process terminates zero point.
Further, by the speed determination bandwidth of described comparator.
3, beneficial effect of the present invention.
(1) the present invention makes integrator also unsaturated with very little electric capacity C by regulation and control the time of integration, solves the problem of the saturated rear inefficacy of integrator.
(2) the present invention reduces the size of traditional quadrature device resistance R by switching capacity feedback D/A converter module, decreases the error of electric current when nA or pA rank, also reduces the area of chip.
Accompanying drawing explanation
Circuit diagram in Fig. 1 prior art.
Fig. 2 is circuit diagram of the present invention.
Embodiment
In order to enable the auditor of Patent Office especially the public clearly understand technical spirit of the present invention and beneficial effect, applicant will elaborate below by way of example, but be not all the restriction to the present invention program to the description of embodiment, any conceive according to the present invention done be only pro forma but not substantial equivalent transformation and all should be considered as technical scheme category of the present invention.
Embodiment 1
Based on two slopes integrating analog to digital converter of switching capacity feedback coefficient mode convertion, comprise the integrator be made up of switching capacity feedback D/A converter module and electric capacity, amplifier, comparator, digital control and counting module, switching capacity feedback D/A converter module, input signal is added in and feeds back D/A converter module by switching capacity, on the integrator that electric capacity is formed, digital controlly start to count with counting module, after the scheduled time, a reversed polarity reference voltage is carried on electric capacity by control switch capacitive feedback D/A converter module, now between the stored charge of integrator and input at this moment, the mean value of section is directly proportional, the backslash slope of the integration of reference voltage to be slope be VREF/RC, now digital controlly to count from 0 with counting module, when integrator output reaches 0, counting stops, reset analog circuit.
Embodiment 2
Based on two slopes integrating analog to digital converter of switching capacity feedback coefficient mode convertion, comprise the integrator be made up of switching capacity feedback D/A converter module and electric capacity, amplifier, comparator, digital control and counting module, switching capacity feedback D/A converter module, input signal is added in and feeds back D/A converter module by switching capacity, on the integrator that electric capacity is formed, digital controlly start to count with counting module, after the scheduled time, a reversed polarity reference voltage is carried on electric capacity by control switch capacitive feedback D/A converter module, now between the stored charge of integrator and input at this moment, the mean value of section is directly proportional, the backslash slope of the integration of reference voltage to be slope be VREF/RC, now digital controlly to count from 0 with counting module, when integrator output reaches 0, counting stops, reset analog circuit.
Described Preset Time is regulated and controled with counting module by digital control, thus control the time of integration.Increase and the input voltage × time of the electric charge of integrator are directly proportional, and to lose with the electric charge measured and contrast potential × contrast potential time is directly proportional, result be relative to full-scale count value and contrast potential input time/input voltage time=input voltage/contrast potential is directly proportional.Digital control is binary number with the output of counting module.When being stored on electric capacity when carrying out the anti-integration of anomalous integral, offset voltage is offset.Described comparator is detected when anti-integration and judges whether anti-integral process terminates zero point.By the speed determination bandwidth of described comparator.
Claims (7)
1. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion, it is characterized in that: comprise the integrator be made up of switching capacity feedback D/A converter module and electric capacity, amplifier, comparator, digital control and counting module, switching capacity feedback D/A converter module, input signal is added in and feeds back D/A converter module by switching capacity, on the integrator that electric capacity is formed, digital controlly start to count with counting module, after the scheduled time, a reversed polarity reference voltage is carried on electric capacity by control switch capacitive feedback D/A converter module, now between the stored charge of integrator and input at this moment, the mean value of section is directly proportional, the backslash slope of the integration of reference voltage to be slope be VREF/RC, now digital controlly to count from 0 with counting module, when integrator output reaches 0, counting stops, reset analog circuit.
2. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1, is characterized in that: described Preset Time is regulated and controled with counting module by digital control, thus controls the time of integration.
3. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1 and 2, it is characterized in that: increase and the input voltage × time of the electric charge of integrator are directly proportional, and to lose with the electric charge measured and contrast potential × contrast potential time is directly proportional, result be relative to full-scale count value and contrast potential input time/input voltage time=input voltage/contrast potential is directly proportional.
4. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1, is characterized in that: digital control is binary number with the output of counting module.
5. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1 and 2, is characterized in that: when being stored on electric capacity when carrying out the anti-integration of anomalous integral, and offset voltage is offset.
6. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1, is characterized in that: described comparator is detected when anti-integration and judges whether anti-integral process terminates zero point.
7. the two slopes integrating analog to digital converter based on switching capacity feedback coefficient mode convertion according to claim 1, is characterized in that: by the speed determination bandwidth of described comparator.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811987A (en) * | 2016-03-09 | 2016-07-27 | 广州龙之杰科技有限公司 | High-cost performance single-integral analog-to-digital converter and conversion method thereof |
| CN106899297A (en) * | 2017-01-17 | 2017-06-27 | 华中科技大学 | A kind of A/D converter circuit based on memristor |
| CN112187275A (en) * | 2019-07-03 | 2021-01-05 | 三星电机株式会社 | Dual slope analog to digital converter |
| CN113346896A (en) * | 2021-04-27 | 2021-09-03 | 北京航空航天大学 | Charge integrating and counting type circuit and analog and storage integrated structure |
| CN113839677A (en) * | 2021-08-31 | 2021-12-24 | 中国计量大学 | Integral analog-to-digital converter and analog-to-digital conversion method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358590A (en) * | 2000-06-09 | 2001-12-26 | Oki Micro Design Co Ltd | Analogue-digital converter |
| US7471231B2 (en) * | 2007-04-24 | 2008-12-30 | Forza Silicon Corporation | Column parallel readout with a differential sloped A/D converter |
| CN101860367B (en) * | 2010-06-25 | 2013-05-15 | 房慧龙 | High-precision fast-integration type AD (Analog-Digital) converter based on single chip microcomputer |
| CN102394651B (en) * | 2011-09-01 | 2014-03-26 | 徐州师范大学 | Programmable double integral type 32-bit ADC (analog-to-digital converter) |
-
2014
- 2014-04-24 CN CN201410167280.5A patent/CN105024699B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811987A (en) * | 2016-03-09 | 2016-07-27 | 广州龙之杰科技有限公司 | High-cost performance single-integral analog-to-digital converter and conversion method thereof |
| CN105811987B (en) * | 2016-03-09 | 2022-12-09 | 广州龙之杰科技有限公司 | Single-integration analog-to-digital converter and conversion method thereof |
| CN106899297A (en) * | 2017-01-17 | 2017-06-27 | 华中科技大学 | A kind of A/D converter circuit based on memristor |
| CN106899297B (en) * | 2017-01-17 | 2020-05-19 | 华中科技大学 | Memristor-based AD conversion circuit |
| CN112187275A (en) * | 2019-07-03 | 2021-01-05 | 三星电机株式会社 | Dual slope analog to digital converter |
| CN112187275B (en) * | 2019-07-03 | 2024-05-28 | 三星电机株式会社 | Dual slope analog to digital converter |
| CN113346896A (en) * | 2021-04-27 | 2021-09-03 | 北京航空航天大学 | Charge integrating and counting type circuit and analog and storage integrated structure |
| CN113346896B (en) * | 2021-04-27 | 2022-09-02 | 北京航空航天大学 | Charge integrating and counting type circuit and analog storage and calculation integrated structure |
| CN113839677A (en) * | 2021-08-31 | 2021-12-24 | 中国计量大学 | Integral analog-to-digital converter and analog-to-digital conversion method thereof |
| CN113839677B (en) * | 2021-08-31 | 2024-02-02 | 中国计量大学 | Integral analog-to-digital converter and analog-to-digital conversion method thereof |
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| CN105024699B (en) | 2018-06-29 |
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Effective date of registration: 20181016 Address after: 201800 room 409, 811 Ping Cheng Road, Jiading District, Shanghai. Patentee after: SHANGHAI SIMAX TECHNOLOGY CO., LTD. Address before: 215500 Room 308, Southeast University Science and Technology Park, Changshou City hi tech Industrial Development Zone, Suzhou, Jiangsu Patentee before: SUZHOU MAIYUE INFORMATION TECHNOLOGY CO., LTD. |
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