CN104993701A - PWM/PFM control circuit - Google Patents
PWM/PFM control circuit Download PDFInfo
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- CN104993701A CN104993701A CN201510436076.3A CN201510436076A CN104993701A CN 104993701 A CN104993701 A CN 104993701A CN 201510436076 A CN201510436076 A CN 201510436076A CN 104993701 A CN104993701 A CN 104993701A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a PWM/PFM control circuit comprising a feedback circuit, an error amplifier, a PWM comparator, an oscillator, and an oscillator frequency control circuit. The feedback circuit samples an output voltage of a power conversion circuit, and generates a feedback voltage reflecting the output voltage. The error amplifier obtains an error amplification voltage based on the error between a reference voltage and the feedback voltage. The oscillator generates a triangular wave oscillation signal. The PWM comparator is used for comparing the triangular wave oscillation signal and the error amplification voltage to output a control signal. The oscillator frequency control circuit outputs a corresponding current signal to the oscillator based on the error amplification voltage. The oscillator adjusts the magnitude of the charging current of the oscillator based on the current signal in order to change the frequency of the triangular wave oscillation signal output by the oscillator. Compared with the prior art, the PWM/PFM control circuit of the invention not only can realize continuous switching transition from PFM to PWM, but also can further reduce the minimum value of frequency under a PFM mode.
Description
[technical field]
The present invention relates to electric power management circuit field, the PWM/PFM control circuit particularly in a kind of switch power converter circuit.
[background technology]
Present many switch power converters (such as, voltage descending DC-DC converter) all comprise two kinds of mode of operation: PWM (Pulse Width Modulation) pattern and PFM (Pulse Frequency Modulation) pattern.During general heavier loads, switch power converter work in a PWM mode, thus under making it be operated in fixing upper frequency, maintains lower output voltage ripple.But the switching loss due to control circuit is in a PWM mode general comparatively large, therefore, usually when load is lighter, switch power converter is switched to PFM MODE of operation, along with load lightens, its operating frequency step-down, the mean value of the switching loss of control circuit reduces and step-down along with frequency.Because the control circuit of traditional compatible PWM mode and PFM pattern is mutation process when two kinds of patterns switch, therefore, when load current is near switching point, system is easily unstable, causes the output voltage ripple near switching point to enlarge markedly.U.S. Patent application US2009/0033305A1 discloses a kind of PWM/PFM control circuit of improvement, its operation principle is the PFM control signal A of a generation minimum ON time, pwm control signal B is produced by pwm control circuit, a time difference signal is produced by signal A and B, then at this moment between difference time period in oscillator suspension is charged, thus the cycle of delay generator, cycle oscillator after delay equals the time span that cycle oscillator under original PWM mode adds this time difference, the seamless continuous switching transition of PFM to PWM can be realized in this way, thus make output more stable when switching, the ripple of output voltage is less.But, according to this principle, maximum time difference length equals the high level time (i.e. minimum ON time) of PFM control signal A, this time is the longest is generally no more than the half of cycle oscillator time under PWM mode, therefore, frequency reducing be cycle oscillator under 1.5 times of PWM mode to greatest extent, namely the frequency of oscillation under 1/1.5=2/3 times of PWM mode is downconverted to, cause the mean value compared with switching loss under underload still larger like this, most limiting case is unloaded, in order to reduce compared with the stand-by power consumption under underload or under zero load further, be necessary to reduce further the frequency minimum under PFM pattern.
Therefore, be necessary that the technical scheme proposing a kind of improvement solves the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of PWM/PFM control circuit, it not only can realize the continuous switching transition of PFM to PWM, but also the frequency minimum that can reduce further under PFM pattern, thus reduce compared with the stand-by power consumption under the power consumption under underload and/or zero load.
To achieve these goals, the present invention proposes a kind of PWM/PFM control circuit, it has pwm pattern and PFM control model, and described PWM/PFM control circuit comprises feedback circuit, error amplifier, PWM comparator, oscillator and oscillator frequency control circuit.Described feedback circuit sample a power-switching circuit output voltage VO and formed reflection described output voltage VO feedback voltage, the control signal that described power-switching circuit exports based on PWM/PFM control circuit converts an input voltage to described output voltage VO; Described error amplifier obtains error amplification voltage based on the error of a reference voltage V REF and feedback voltage; Described oscillator produces triangular wave oscillation signal; Described PWM comparator is used for more described triangular wave oscillation signal and described error amplifies voltage to export described control signal; Described oscillator frequency control circuit amplifies voltage based on described error and exports corresponding current signal to described oscillator, described oscillator regulates the size of the charging current of described oscillator based on described current signal, to change the frequency of the triangular wave oscillation signal that described oscillator exports.
Further, described oscillator frequency control circuit comprises the first reference voltage VRH and the second reference voltage VRL, wherein, 0 < VRL < VRH < VP, VP is the crest voltage of the triangular wave oscillation signal that described oscillator exports, and VEAO is the magnitude of voltage that described error amplifies voltage.As VEAO > VRH, described oscillator frequency control circuit exports the first current signal IA to described oscillator, and (VEAO-VRH) is larger, the first current signal IA that described oscillator frequency control circuit exports is larger, cause the charging current of described oscillator less, and then the frequency of the triangular wave oscillation signal that described oscillator is exported is lower, as VEAO < VRL, described oscillator frequency control circuit exports the second current signal IB to described oscillator, and (VRL-VEAO) is larger, the second current signal IB that described oscillator frequency control circuit exports is larger, cause the charging current of described oscillator less, and then the frequency of the triangular wave oscillation signal making described oscillator export is lower, as VRL < VEAO < VRH, the electric current of the first current signal IA that described oscillator frequency control circuit exports and the second current signal is zero, now the charging current of described oscillator is fixed, the frequency of the triangular wave oscillation signal that described oscillator is exported is fixed.
Further, described oscillator frequency control circuit comprises the first trsanscondutance amplifier and the second trsanscondutance amplifier, first input end and the described error of described first trsanscondutance amplifier are amplified voltage and are connected, its second input is connected with the first reference voltage VRH, described first trsanscondutance amplifier is used for more described error and amplifies voltage and the first reference voltage VRH, produce and export the first current signal IA, as VEAO < VRH, the electric current of the first current signal IA is zero; As VEAO > VRH, and (VEAO-VRH) is larger, and the electric current of the first current signal IA is larger; Second input and the described error of described second trsanscondutance amplifier are amplified voltage and are connected, its first input end is connected with the second reference voltage VRL, described second trsanscondutance amplifier is used for more described error and amplifies voltage and the second reference voltage VRL, produce and export the second current signal IB, as VEAO > VRL, the electric current of the second current signal IB is zero; As described VEAO < VRL, and (VRL-VEAO) is larger, and the electric current of the second current signal IB is larger.
Further, the first input end of described first trsanscondutance amplifier and the second input are respectively positive input and the negative input of the first trsanscondutance amplifier; The first input end of described second trsanscondutance amplifier and the second input are respectively positive input and the negative input of the second trsanscondutance amplifier.
Further, described oscillator frequency control circuit comprises the first trsanscondutance amplifier, and the first trsanscondutance amplifier comprises the first current source I1, PMOS transistor MP1, MP2, MP3 and MP4, nmos pass transistor MN1, MN2 and MN3.The negative pole of described first current source I1 is connected with a power end, and the described positive pole of the first current source I1 is connected with the connected node between the source electrode of PMOS transistor MP1 and the source electrode of PMOS transistor MP2; The grid of PMOS transistor MP1 amplifies voltage as the first input end of described first trsanscondutance amplifier with described error and is connected, the grid of PMOS transistor MP2 is connected with the first reference voltage VRH as the second input of described first trsanscondutance amplifier, the drain electrode of nmos pass transistor MN1 is connected with the drain electrode of PMOS transistor MP1, the grid of nmos pass transistor MN1 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN1; The drain electrode of nmos pass transistor MN2 is connected with the drain electrode of PMOS transistor MP2, and the grid of nmos pass transistor MN2 is connected with the grid of nmos pass transistor MN1, the source ground of nmos pass transistor MN2; The source electrode of PMOS transistor MP3 and the source electrode of PMOS transistor MP4 are all connected with the negative pole of described first current source I1, the grid of PMOS transistor MP3 is connected with the drain electrode of himself, the grid of PMOS transistor MP4 is connected with the grid of PMOS transistor MP3, and the drain electrode of PMOS transistor MP4 exports the first current signal IA to described oscillator as the output of described first trsanscondutance amplifier; The drain electrode of nmos pass transistor MN3 is connected with the drain electrode of PMOS transistor MP3, and the grid of nmos pass transistor MN3 is connected with the drain electrode of nmos pass transistor MN2, the source ground of nmos pass transistor MN3.
Further, described oscillator frequency control circuit also comprises the second trsanscondutance amplifier, and described second trsanscondutance amplifier comprises the second current source I2, PMOS transistor MP5, MP6, MP7 and MP8, nmos pass transistor MN5, MN6 and MN7.The negative pole of described second current source I2 is connected with a power end, and the described positive pole of the second current source I2 is connected with the connected node between the source electrode of PMOS transistor MP5 and the source electrode of PMOS transistor MP6; The grid of PMOS transistor MP5 is connected with the second reference voltage VRL as the first input end of described second trsanscondutance amplifier, and the grid of PMOS transistor MP6 amplifies voltage as the second input of described second trsanscondutance amplifier with described error and is connected; The drain electrode of nmos pass transistor MN5 is connected with the drain electrode of PMOS transistor MP5, and the grid of nmos pass transistor MN5 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN5; The drain electrode of nmos pass transistor MN6 is connected with the drain electrode of PMOS transistor MP6, and the grid of nmos pass transistor MN6 is connected with the grid of nmos pass transistor MN5, the source ground of nmos pass transistor MN6; The source electrode of PMOS transistor MP7 and the source electrode of PMOS transistor MP8 are all connected with the negative pole of described second current source I2, the grid of PMOS transistor MP7 is connected with the drain electrode of himself, the grid of PMOS transistor MP8 is connected with the grid of PMOS transistor MP7, and the drain electrode of PMOS transistor MP8 exports the second current signal IB to described oscillator as the output of described second trsanscondutance amplifier; The drain electrode of nmos pass transistor MN7 is connected with the drain electrode of PMOS transistor MP7, the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MN6, the source ground of nmos pass transistor MN7, wherein, 0 < VRL < VRH < VP, VP are the crest voltage of the triangular wave oscillation signal that described oscillator exports.
Further described oscillator comprises electric capacity C1, charging circuit, discharge circuit and comparison circuit.Described charging circuit comprises the 3rd current source I3, and described charging circuit produces charging current Ic based on the difference of the 3rd current source I3 and the first current signal IA and the second current signal IB, and charging current Ic charges to electric capacity C1; Described comparison circuit compares the voltage of a reference voltage V 1 and described electric capacity C1, and when the voltage of described electric capacity C1 is greater than described reference voltage V 1, control described discharge circuit and carry out repid discharge to described electric capacity C1, the voltage signal of described electric capacity C1 just defines described triangular wave oscillation signal.
Further, described charging circuit also comprises PMOS transistor MP9 and MP10, and described discharge circuit comprises a discharge control switch, and described comparison circuit comprises comparator com1.The input of described oscillator receives the first current signal IA and the second current signal IB, and the negative pole of the 3rd current source I3 is connected with the input of described oscillator, the plus earth of the 3rd current source I3; The source electrode of PMOS transistor MP9 is all connected with a power end with the source electrode of MP10, and the grid of PMOS transistor MP9 is connected with the drain electrode of himself, and the drain electrode of PMOS transistor MP9 is connected with the input of described oscillator; The grid of PMOS transistor MP10 is connected with the grid of PMOS transistor MP9, and the drain electrode of PMOS transistor MP10 is connected with described electric capacity C1 one end, the other end ground connection of electric capacity C1; Described discharge control switch is in parallel with described electric capacity C1; The first input end of comparator com1 is connected with the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1, second input of comparator com1 is connected with reference voltage V 1, the output of comparator com1 is connected with the control end of discharge control switch, and the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1 exports triangular wave oscillation signal as the output of oscillator.
Further, the first input end of described comparator com1 and the second input are respectively positive input and the negative-phase input of comparator com1; Described discharge control switch is nmos pass transistor MN9, and nmos pass transistor MN9 drain electrode is connected with one end of described electric capacity C1, and its source electrode is connected with the other end of described electric capacity C1, and its grid is connected with the output of described comparator com1.
Further, the peak value of described triangular wave oscillation signal is fixed value, and its valley is fixed value.
Compared with prior art, the present invention has set up oscillator frequency control circuit in existing pwm control circuit, this oscillator frequency control circuit is when underloading or zero load, amplify voltage based on described error and produce corresponding current signal to oscillator, to reduce the charging current of oscillator, thus reduce the frequency of the triangular wave oscillation signal that oscillator exports.Like this, not only can realize the continuous switching transition of PFM to PWM, but also the frequency minimum under PFM pattern can be reduced further, thus reduce compared with the stand-by power consumption under the power consumption under underload and/or zero load.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the PWM/PFM control circuit system circuit diagram in one embodiment in the present invention;
Fig. 2 is the first trsanscondutance amplifier circuit diagram in one embodiment in Fig. 1;
Fig. 3 is the second trsanscondutance amplifier circuit diagram in one embodiment in Fig. 1;
Fig. 4 is the oscillator OSC circuit diagram in one embodiment in Fig. 1;
Fig. 5 is the oscillogram of the triangular wave oscillation signal Ramp that the oscillator in Fig. 4 exports.
[embodiment]
Detailed description of the present invention carrys out the running of direct or indirect simulation technical solution of the present invention mainly through program, step, logical block, process or other symbolistic descriptions.For thorough understanding the present invention, in ensuing description, set forth a lot of specific detail.And when not having these specific detail, the present invention then may still can realize.Affiliated those of skill in the art use the work that these describe and statement effectively introduces them to the others skilled in the art in affiliated field herein essential.In other words, be object of the present invention of avoiding confusion, due to the method known and program easy understand, therefore they are not described in detail.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.
Fig. 1 is PWM/PFM control circuit system 100 circuit diagram in one embodiment in the present invention.Described PWM/PFM control circuit system comprises power-switching circuit 110, feedback circuit 120, error amplifier EA, PWM comparator com, logic control element Control Logic, drive circuit Driver, oscillator OSC and oscillator frequency control circuit 130.In the embodiment had, described power-switching circuit 110 can not belong to described PWM/PFM control circuit system 100, but a circuit arranged side by side with described PWM/PFM control circuit system 100.
Described power-switching circuit 110 converts an input voltage VIN to an output voltage VO.In the embodiment shown in fig. 1, described power-switching circuit 110 is buck DC-DC voltage conversion circuit, it comprises inductance L 1, electric capacity C0, is connected on output transistor MPX and MNX between input voltage VIN and ground, their grid is connected with the output of described drive circuit Driver, connected node LX between output transistor MPX and MNX is by inductance L 1 and electric capacity C0 ground connection, and the voltage of the connected node between inductance L 1 and electric capacity C0 is as output voltage VO.
Described feedback circuit 120 is sampled described output voltage VO, and form the feedback voltage of the described output voltage VO of reflection, in the embodiment shown in fig. 1, described feedback circuit 120 comprises resistance R1 and R2 be series at successively between output voltage VO and ground, wherein, the voltage of the connected node FB between resistance R1 and resistance R2 is the feedback voltage of described feedback circuit 120.Described oscillator OSC generates and exports triangular signal Ramp (it also can be described as triangular wave oscillation signal Ramp).The error that described error amplifier EA amplifies a reference voltage V REF and feedback voltage FB obtains error and amplifies voltage EAO.Described PWM comparator com is used for more described triangular signal Ramp and institute's error amplifies voltage EAO, to export corresponding control signal PC.Control signal PC produces the first drive singal PDRV successively to the grid of output transistor MPX after logic control element Control Logic and drive circuit Driver, produce the second drive singal to the grid of output transistor MNX, with driver output transistor MPX and MNX alternate conduction; The voltage of connected node LX, after the filter circuit that inductance L 1 and electric capacity C0 are formed, forms output voltage VO.
The input of described oscillator frequency control circuit 130 is connected with the output of described error amplifier EA, and the output of described oscillator frequency control circuit 130 is connected with the input of described oscillator OSC.Described oscillator frequency control circuit 130 amplifies voltage OEA based on the error that described error amplifier EA exports and exports corresponding current signal to described oscillator OSC, described oscillator OSC regulates the size of charging current based on described current signal, thus changes the frequency (or changing the frequency of described oscillator OSC) of the triangular signal Ramp that described oscillator OSC exports.
In the embodiment shown in fig. 1, described oscillator frequency control circuit 130 comprises the first trsanscondutance amplifier Gm1 and the second trsanscondutance amplifier Gm2, the first input end of described first trsanscondutance amplifier Gm1 is connected with the output of described error amplifier EA, its second input is connected with the first reference voltage VRH, described first trsanscondutance amplifier Gm1 is used for more described error and amplifies voltage EAO and the first reference voltage VRH, produces and exports the first current signal IA to the input of described oscillator OSC; Second input of described second trsanscondutance amplifier Gm2 is connected with the output of described error amplifier EA, its first input end is connected with the second reference voltage VRL, described second trsanscondutance amplifier Gm2 is used for more described error and amplifies voltage EAO and the second reference voltage VRL, produces and exports the second current signal IB to the input of described oscillator OSC.Described oscillator OSC adjusts charging current according to the first current signal IA and the second current signal IB, and producing triangular signal Ramp based on the charging current after adjustment, the first current signal IA and the second current signal IB can change the frequency of triangular signal Ramp.Wherein, 0 < VRL < VRH < VP, VRH is the magnitude of voltage of the first reference voltage VRH, VRL is the magnitude of voltage of the second reference voltage VRL, VP is the crest voltage of the triangular signal Ramp that oscillator OSC exports, and specifically refers to Fig. 5.
Concrete, when described error amplifies voltage EAO much larger than the second reference voltage VRL, the second trsanscondutance amplifier Gm2 output current is zero; When described error amplify voltage EAO close to or when being less than described second reference voltage VRL, described second trsanscondutance amplifier Gm2 produces the second current signal IB, and (VRL-VEAO) is larger, the electric current of its second current signal IB exported is larger, wherein, VRL is the magnitude of voltage of the second reference voltage VRL, and VEAO is the magnitude of voltage that error amplifies voltage EAO.
When described error amplifies voltage EAO much smaller than the first reference voltage VRH, described first trsanscondutance amplifier Gm1 output current is zero; When described error amplify voltage EAO close to or when being greater than described first reference voltage VRH, described first trsanscondutance amplifier Gm1 produces the first current signal IA, and (VEAO-VRH) is larger, the electric current of its first current signal IA exported is larger, wherein, VRH is the magnitude of voltage of the first reference voltage VRH, and VEAO is the magnitude of voltage that error amplifies voltage EAO.
Due to amplify in error voltage EAO close to or when being less than the second reference voltage VRL, second trsanscondutance amplifier Gm2 exports the second current signal IB, error amplify voltage EAO close to or when being greater than the first reference voltage VRH, first trsanscondutance amplifier Gm1 exports the first current signal IA, and the second reference voltage VRL < first reference voltage VRH, therefore, the first current signal IA and the second current signal IB can't produce simultaneously.
Described oscillator OSC regulates current IB signal to regulate the size of charging current based on described first current signal IA or second, thus change the frequency of the triangular signal Ramp that described oscillator OSC exports, such as, the peak value of triangular signal Ramp is fixed value VP, valley is fixed value (such as, 0V), and the first current signal IA is larger, charging current is less, causes the frequency of oscillator OSC lower; Second current signal IB is larger, and charging current is less, causes the frequency of oscillator OSC lower.
Based on the description of the above-mentioned course of work to the first trsanscondutance amplifier Gm1 and the second trsanscondutance amplifier Gm2, specifically introduce the operation principle of the PWM/PFM control circuit in Fig. 1 below.
As VEAO > VRH, described oscillator frequency control circuit 130 exports the first current signal IA to described oscillator OSC, and (VEAO-VRH) is larger, the electric current of the first current signal IA that described oscillator frequency control circuit 130 exports is larger, make the charging current of described oscillator OSC less, cause the frequency of described oscillator OSC lower, thus the frequency-adjustable of the control signal PC that PWM comparator com is exported.Now, in fact PWM/PFM control circuit in Fig. 1 is in a PFM control model, namely as VEAO > VRH, show that the difference of input voltage VIN and output voltage VO is very little and load is very heavy, more big space rate can be realized by reducing frequency, ensureing dc-dc steady operation.
As VRL < VEAO < VRH, the electric current of the current signal that described oscillator frequency control circuit 130 exports is zero, the charging current of described oscillator OSC is fixed, cause the frequency of oscillator OSC to be fixed, thus the frequency of the control signal PC that PWM comparator com is exported is fixed.Now, in fact the PWM/PFM control circuit in Fig. 1 is in pwm pattern.
As VEAO < VRL, described oscillator frequency control circuit 130 exports the second current signal IB to described oscillator OSC, and (VRL-VEAO) is larger, the electric current of the second current signal IB that described oscillator frequency control circuit 130 exports is larger, make the charging current of described oscillator OSC less, cause the frequency of described oscillator OSC lower, thus the frequency-adjustable of the control signal PC that PWM comparator com is exported.Now, in fact the PWM/PFM control circuit in Fig. 1 is in the 2nd PFM control model, namely as VEAO < VRL, showing that load is very light, by reducing frequency, realizing lower power usage.Wherein, VRH is the magnitude of voltage of the first reference voltage VRH, and VRL is the magnitude of voltage of the second reference voltage VRL, and VEAO is the magnitude of voltage that error amplifies voltage EAO.
In sum, the present invention has set up oscillator frequency control circuit 130 in existing pwm control circuit, this oscillator frequency control circuit 130 error that error amplifier EA exports amplify voltage EAO excessive or too small time, produce corresponding current signal to oscillator OSC, when error amplification voltage EAO is greater than the first reference voltage VRH (namely error amplification voltage EAO is excessive), oscillator frequency control circuit 130 exports the first current signal IA, and error amplification voltage EAO is larger, the electric current of the first circuit signal IA is larger, and the frequency of oscillator OSC is lower; When error amplification voltage EAO is less than the second reference voltage VRL (namely error amplification voltage EAO is too small), oscillator frequency control circuit 130 exports the second current signal IB, and error amplification voltage EAO is less, the electric current of second circuit signal IB is larger, and the frequency of oscillator OSC is lower.Like this, not only can realize the continuous switching transition of PFM to PWM, but also the frequency minimum under PFM pattern can be reduced further, thus reduce compared with the stand-by power consumption under the power consumption under underload and/or zero load.
Obviously, PWM/PFM control circuit in the present invention also goes for the control of the dc-dc of other types, as, booster type, buck converter, it needs the Switching Power Supply change-over circuit power-switching circuit 110 in Fig. 1 being replaced with other types.
Please refer to shown in Fig. 2, it is the first trsanscondutance amplifier Gm1 circuit diagram in one embodiment in Fig. 1.The first trsanscondutance amplifier shown in Fig. 2 comprises the first current source I1, PMOS transistor MP1, MP2, MP3 and MP4, nmos pass transistor MN1, MN2 and MN3.
The negative pole of described first current source I1 is connected with a power end, and the described positive pole of the first current source I1 is connected with the connected node between the source electrode of PMOS transistor MP1 and the source electrode of PMOS transistor MP2; The grid of PMOS transistor MP1 is as the first input end of described first trsanscondutance amplifier, and the grid of PMOS transistor MP2 is as the second input of described first trsanscondutance amplifier; The drain electrode of nmos pass transistor MN1 is connected with the drain electrode of PMOS transistor MP1, and the grid of nmos pass transistor MN1 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN1; The drain electrode of nmos pass transistor MN2 is connected with the drain electrode of PMOS transistor MP2, and the grid of nmos pass transistor MN2 is connected with the grid of nmos pass transistor MN1, the source ground of nmos pass transistor MN2; The source electrode of PMOS transistor MP3 and the source electrode of PMOS transistor MP4 are all connected with the negative pole of described first current source I1, the grid of PMOS transistor MP3 is connected with the drain electrode of himself, the grid of PMOS transistor MP4 is connected with the grid of PMOS transistor MP3, and the drain electrode of PMOS transistor MP4 exports the first current signal IA as the output of described first trsanscondutance amplifier; The drain electrode of nmos pass transistor MN3 is connected with the drain electrode of PMOS transistor MP3, and the grid of nmos pass transistor MN3 is connected with the drain electrode of nmos pass transistor MN2, the source ground of nmos pass transistor MN3.Wherein, the first current source I1, PMOS transistor MP1 and MP2, nmos pass transistor MN1 and MN2 forms differential input stage; Nmos pass transistor MN3, PMOS transistor MP3 and MP4 form circuit output stage; Nmos pass transistor MN1 and MN2 forms current mirror; PMOS transistor MP3 and MP4 forms current mirror.
When error amplification voltage EAO is more lower than the first reference voltage VRH, PMOS transistor MP1 will get more electric current than PMOS transistor MP2 from the first current source I1, electric current (it equals to flow through the electric current of the PMOS transistor MP1) electric current after nmos pass transistor MN2 mirror image flowing through nmos pass transistor MN1 is caused to be greater than the electric current flowing through PMOS transistor MP2, then the grid voltage of nmos pass transistor MN3 reduces, nmos pass transistor MN3 ends, make that PMOS transistor MP3 and MP4 does not have electric current to flow through, the electric current of the first current signal IA is zero, namely when described error amplifies voltage EAO much smaller than the first reference voltage VRH, described first trsanscondutance amplifier Gm1 output current is zero.When error amplifies voltage EAO higher than the first reference voltage VRH, PMOS transistor MP2 will get more electric current than PMOS transistor MP1 from the first current source I1, electric current (it equals to flow through the electric current of the PMOS transistor MP1) electric current after nmos pass transistor MN2 mirror image flowing through nmos pass transistor MN1 is caused to be less than the electric current flowing through PMOS transistor MP2, then the grid voltage of nmos pass transistor MN3 uprises, the electric current of nmos pass transistor MN3 increases, electric current on PMOS transistor MP3 is increased, electric current on PMOS transistor MP4 mirror image PMOS transistor MP3, the output current IA of PMOS transistor MP4 is caused to increase, and (VEAO-VRH) is larger, the electric current of the first current signal IA is larger.
Please refer to shown in Fig. 3, it is the second trsanscondutance amplifier Gm2 circuit diagram in one embodiment in Fig. 1.The second trsanscondutance amplifier shown in Fig. 3 comprises the second current source I2, PMOS transistor MP5, MP6, MP7 and MP8, nmos pass transistor MN5, MN6 and MN7.
The negative pole of described second current source I2 is connected with a power end, and the described positive pole of the second current source I2 is connected with the connected node between the source electrode of PMOS transistor MP5 and the source electrode of PMOS transistor MP6; The grid of PMOS transistor MP5 is as the first input end of described second trsanscondutance amplifier, and the grid of PMOS transistor MP6 is as the second input of described second trsanscondutance amplifier; The drain electrode of nmos pass transistor MN5 is connected with the drain electrode of PMOS transistor MP5, and the grid of nmos pass transistor MN5 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN5; The drain electrode of nmos pass transistor MN6 is connected with the drain electrode of PMOS transistor MP6, and the grid of nmos pass transistor MN6 is connected with the grid of nmos pass transistor MN5, the source ground of nmos pass transistor MN6; The source electrode of PMOS transistor MP7 and the source electrode of PMOS transistor MP8 are all connected with the negative pole of described second current source I2, the grid of PMOS transistor MP7 is connected with the drain electrode of himself, the grid of PMOS transistor MP8 is connected with the grid of PMOS transistor MP7, and the drain electrode of PMOS transistor MP8 exports the second current signal IB as the output of described second trsanscondutance amplifier; The drain electrode of nmos pass transistor MN7 is connected with the drain electrode of PMOS transistor MP7, and the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MN6, the source ground of nmos pass transistor MN7.Wherein, the second current source I2, PMOS transistor MP5 and MP6, nmos pass transistor MN5 and MN6 forms differential input stage; Nmos pass transistor MN7, PMOS transistor MP7 and MP8 form circuit output stage; Nmos pass transistor MN5 and MN6 forms current mirror; PMOS transistor MP7 and MP8 forms current mirror.
When error amplification voltage EAO is more higher than the second reference voltage VRL, PMOS transistor MP5 will get more electric current than PMOS transistor MP6 from the second current source I2, electric current (it equals to flow through the electric current of the PMOS transistor MP5) electric current after nmos pass transistor MN6 mirror image flowing through nmos pass transistor MN5 is caused to be greater than the electric current flowing through PMOS transistor MP6, then the grid voltage of nmos pass transistor MN7 reduces, nmos pass transistor MN7 ends, make that PMOS transistor MP7 and MP8 does not have electric current to flow through, the electric current of the second current signal IB is zero, namely when described error amplifies voltage EAO much larger than the second reference voltage VRL, described second trsanscondutance amplifier Gm2 output current is zero.When error amplifies voltage EAO lower than the second reference voltage VRL, PMOS transistor MP6 will get more electric current than PMOS transistor MP5 from the first current source I1, electric current (it equals to flow through the electric current of the PMOS transistor MP1) electric current after nmos pass transistor MN6 mirror image flowing through nmos pass transistor MN5 is caused to be less than the electric current flowing through PMOS transistor MP6, then the grid voltage of nmos pass transistor MN7 uprises, the electric current of nmos pass transistor MN7 increases, electric current on PMOS transistor MP7 is increased, electric current on PMOS transistor MP8 mirror image PMOS transistor MP7, the output current IB of PMOS transistor MP8 is caused to increase, and (VRL-VEAO) is larger, the electric current of the second current signal IB is larger.
Please refer to shown in Fig. 4, it is the oscillator OSC circuit diagram in one embodiment in Fig. 1.Oscillator in Fig. 4 comprises electric capacity C1, charging circuit, discharge circuit and comparison circuit.Described charging circuit comprises the 3rd current source I3, and described charging circuit is based on the 3rd current source I3, and the first current signal IA of receiving of the input of oscillator and the second current signal IB produces charging current Ic, charging current Ic and charges to electric capacity C1.Described comparison circuit compares the voltage of a reference voltage V 1 and described electric capacity C1, and when the voltage of described electric capacity C1 is greater than described reference voltage V 1, control described discharge circuit and carry out repid discharge to described electric capacity C1, the voltage signal of described electric capacity C1 just defines triangular signal Ramp.
Charging circuit in Fig. 4, except the 3rd current source I3, also comprises PMOS transistor MP9 and MP10; Discharge circuit is the nmos pass transistor MN9 in parallel with electric capacity C1; In one embodiment, described nmos pass transistor MN9 also can be other equivalent electrons switching device, such as NPN bipolar transistor; Comparison circuit is comparator com1, and the reference voltage V 1 of comparator com1 is provided by voltage source V 1.
Concrete, oscillator shown in Fig. 4 comprises the 3rd current source I3, electric capacity C1, PMOS transistor MP9 and MP10, nmos pass transistor MN9, voltage source V 1 and comparator com1, the input of described oscillator receives the first current signal IA and the second current signal IB, the negative pole of the 3rd current source I3 is connected with the input of described oscillator, the plus earth of the 3rd current source I3; The source electrode of PMOS transistor MP9 is all connected with a power end with the source electrode of MP10, and the grid of PMOS transistor MP9 is connected with the drain electrode of himself, and the drain electrode of PMOS transistor MP9 is connected with the input of described oscillator; The grid of PMOS transistor MP10 is connected with the grid of PMOS transistor MP9, and the drain electrode of PMOS transistor MP10 is connected with described electric capacity C1 one end, the other end ground connection of electric capacity C1; The drain electrode of described nmos pass transistor MN9 is connected with one end of described electric capacity C1, and its source electrode is connected with the other end of described electric capacity C1; The positive input of comparator com1 is connected with the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1, the negative input of comparator com1 is connected with the positive pole of voltage source V 1, the minus earth of voltage source V 1, the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1 is as the output Ramp of oscillator.
The electric current flowing through PMOS transistor MP9 equals the difference of the 3rd current source I3 and the first current signal IA and the second current signal IB, charges after the electric current on PMOS transistor MP10 mirror image PMOS transistor MP9 to electric capacity C1, i.e. charging current IC=I3-IA-IB.When the electric current of the first current signal IA and the second current signal IB is zero, charging current IC is determined by the 3rd current source I3 completely, now, the frequency of oscillator is fixed, its cycle T 1=VP.C1/I3, wherein VP is the magnitude of voltage of voltage source V 1, and C1 is the magnitude of voltage of electric capacity C1, and I3 is the current value of the 3rd current source I3; From aforementioned, first current signal IA and the second current signal IB can not produce simultaneously, when the electric current of the first current signal IA or the electric current of the second current signal IB increase, the electric current flowing through PMOS transistor MP9 is caused to reduce, the electric current (i.e. charging current IC) flowed through on PMOS transistor MP10 is also reduced, thus make the cycle of oscillator elongated, the cycle T A=VP.C1/ (I3-IA) of oscillator when controlling by the first current signal IA; The cycle T B=VP.C1/ (I3-IB) of oscillator when controlling by the second current signal IB.
The course of work of the oscillator shown in Fig. 4 is: the electric current flowing through PMOS transistor MP10 charges to electric capacity C1, when the voltage rise on electric capacity C1 is to when being greater than reference voltage V 1, the output of comparator com1 becomes high level, cause nmos pass transistor MN9 conducting, by the tension discharge to zero of electric capacity C1, the time delay after should meeting comparator com1 during design enough allows nmos pass transistor MN9 conducting that electric capacity C1 is discharged to zero completely; After electric capacity C1 is discharged to zero, the output of comparator com1 becomes low level, and nmos pass transistor MN9 is turned off, and the electric current on PMOS transistor MP10 charges to electric capacity C1 again, like this, goes round and begins again, and forms vibration.Please refer to shown in Fig. 5, it is the oscillogram of the Ramp signal that the oscillator in Fig. 4 exports.Wherein, peak value VP equals the magnitude of voltage of voltage source V 1, and valley equals 0V, and Ramp waveform is triangular wave, and because the velocity of discharge is fast, therefore, the trailing edge of Ramp signal is very steep, again because charging current is less, so the rising edge of Ramp signal is very slow.
Above-mentioned explanation fully discloses the specific embodiment of the present invention.It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (10)
1. a PWM/PFM control circuit, it has pwm pattern and PFM control model, it is characterized in that, it comprises feedback circuit, error amplifier, PWM comparator, oscillator and oscillator frequency control circuit,
Described feedback circuit sample a power-switching circuit output voltage VO and formed reflection described output voltage VO feedback voltage, the control signal that described power-switching circuit exports based on PWM/PFM control circuit converts an input voltage to described output voltage VO;
Described error amplifier obtains error amplification voltage based on the error of a reference voltage V REF and feedback voltage;
Described oscillator produces triangular wave oscillation signal;
Described PWM comparator is used for more described triangular wave oscillation signal and described error amplifies voltage to export described control signal;
Described oscillator frequency control circuit amplifies voltage based on described error and exports corresponding current signal to described oscillator, described oscillator regulates the size of the charging current of described oscillator based on described current signal, to change the frequency of the triangular wave oscillation signal that described oscillator exports.
2. PWM/PFM control circuit according to claim 1, it is characterized in that, described oscillator frequency control circuit comprises the first reference voltage VRH and the second reference voltage VRL, wherein, 0 < VRL < VRH < VP, VP is the crest voltage of the triangular wave oscillation signal that described oscillator exports, and VEAO is the magnitude of voltage that described error amplifies voltage
As VEAO > VRH, described oscillator frequency control circuit exports the first current signal IA to described oscillator, and (VEAO-VRH) is larger, the first current signal IA that described oscillator frequency control circuit exports is larger, cause the charging current of described oscillator less, and then the frequency of the triangular wave oscillation signal that described oscillator is exported is lower;
As VEAO < VRL, described oscillator frequency control circuit exports the second current signal IB to described oscillator, and (VRL-VEAO) is larger, the second current signal IB that described oscillator frequency control circuit exports is larger, cause the charging current of described oscillator less, and then the frequency of the triangular wave oscillation signal making described oscillator export is lower
As VRL < VEAO < VRH, the electric current of the first current signal IA that described oscillator frequency control circuit exports and the second current signal is zero, now the charging current of described oscillator is fixed, and the frequency of the triangular wave oscillation signal that described oscillator is exported is fixed.
3. PWM/PFM control circuit according to claim 2, is characterized in that, described oscillator frequency control circuit comprises the first trsanscondutance amplifier and the second trsanscondutance amplifier,
First input end and the described error of described first trsanscondutance amplifier are amplified voltage and are connected, its second input is connected with the first reference voltage VRH, described first trsanscondutance amplifier is used for more described error and amplifies voltage and the first reference voltage VRH, produce and export the first current signal IA, as VEAO < VRH, the electric current of the first current signal IA is zero; As VEAO > VRH, and (VEAO-VRH) is larger, and the electric current of the first current signal IA is larger;
Second input and the described error of described second trsanscondutance amplifier are amplified voltage and are connected, its first input end is connected with the second reference voltage VRL, described second trsanscondutance amplifier is used for more described error and amplifies voltage and the second reference voltage VRL, produce and export the second current signal IB, as VEAO > VRL, the electric current of the second current signal IB is zero; As described VEAO < VRL, and (VRL-VEAO) is larger, and the electric current of the second current signal IB is larger.
4. PWM/PFM control circuit according to claim 3, is characterized in that,
The first input end of described first trsanscondutance amplifier and the second input are respectively positive input and the negative input of the first trsanscondutance amplifier;
The first input end of described second trsanscondutance amplifier and the second input are respectively positive input and the negative input of the second trsanscondutance amplifier.
5. PWM/PFM control circuit according to claim 1, is characterized in that, described oscillator frequency control circuit comprises the first trsanscondutance amplifier, first trsanscondutance amplifier comprises the first current source I1, PMOS transistor MP1, MP2, MP3 and MP4, nmos pass transistor MN1, MN2 and MN3
The negative pole of described first current source I1 is connected with a power end, and the described positive pole of the first current source I1 is connected with the connected node between the source electrode of PMOS transistor MP1 and the source electrode of PMOS transistor MP2; The grid of PMOS transistor MP1 amplifies voltage as the first input end of described first trsanscondutance amplifier with described error and is connected, the grid of PMOS transistor MP2 is connected with the first reference voltage VRH as the second input of described first trsanscondutance amplifier, the drain electrode of nmos pass transistor MN1 is connected with the drain electrode of PMOS transistor MP1, the grid of nmos pass transistor MN1 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN1; The drain electrode of nmos pass transistor MN2 is connected with the drain electrode of PMOS transistor MP2, and the grid of nmos pass transistor MN2 is connected with the grid of nmos pass transistor MN1, the source ground of nmos pass transistor MN2; The source electrode of PMOS transistor MP3 and the source electrode of PMOS transistor MP4 are all connected with the negative pole of described first current source I1, the grid of PMOS transistor MP3 is connected with the drain electrode of himself, the grid of PMOS transistor MP4 is connected with the grid of PMOS transistor MP3, and the drain electrode of PMOS transistor MP4 exports the first current signal IA to described oscillator as the output of described first trsanscondutance amplifier; The drain electrode of nmos pass transistor MN3 is connected with the drain electrode of PMOS transistor MP3, and the grid of nmos pass transistor MN3 is connected with the drain electrode of nmos pass transistor MN2, the source ground of nmos pass transistor MN3.
6. PWM/PFM control circuit according to claim 5, is characterized in that, described oscillator frequency control circuit also comprises the second trsanscondutance amplifier, described second trsanscondutance amplifier comprises the second current source I2, PMOS transistor MP5, MP6, MP7 and MP8, nmos pass transistor MN5, MN6 and MN7
The negative pole of described second current source I2 is connected with a power end, and the described positive pole of the second current source I2 is connected with the connected node between the source electrode of PMOS transistor MP5 and the source electrode of PMOS transistor MP6; The grid of PMOS transistor MP5 is connected with the second reference voltage VRL as the first input end of described second trsanscondutance amplifier, and the grid of PMOS transistor MP6 amplifies voltage as the second input of described second trsanscondutance amplifier with described error and is connected; The drain electrode of nmos pass transistor MN5 is connected with the drain electrode of PMOS transistor MP5, and the grid of nmos pass transistor MN5 is connected with the drain electrode of himself, the source ground of nmos pass transistor MN5; The drain electrode of nmos pass transistor MN6 is connected with the drain electrode of PMOS transistor MP6, and the grid of nmos pass transistor MN6 is connected with the grid of nmos pass transistor MN5, the source ground of nmos pass transistor MN6; The source electrode of PMOS transistor MP7 and the source electrode of PMOS transistor MP8 are all connected with the negative pole of described second current source I2, the grid of PMOS transistor MP7 is connected with the drain electrode of himself, the grid of PMOS transistor MP8 is connected with the grid of PMOS transistor MP7, and the drain electrode of PMOS transistor MP8 exports the second current signal IB to described oscillator as the output of described second trsanscondutance amplifier; The drain electrode of nmos pass transistor MN7 is connected with the drain electrode of PMOS transistor MP7, and the grid of nmos pass transistor MN7 is connected with the drain electrode of nmos pass transistor MN6, the source ground of nmos pass transistor MN7,
Wherein, 0 < VRL < VRH < VP, VP are the crest voltage of the triangular wave oscillation signal that described oscillator exports.
7., according to the arbitrary described PWM/PFM control circuit of claim 2-6, it is characterized in that, described oscillator comprises electric capacity C1, charging circuit, discharge circuit and comparison circuit,
Described charging circuit comprises the 3rd current source I3, and described charging circuit produces charging current Ic based on the difference of the 3rd current source I3 and the first current signal IA and the second current signal IB, and charging current Ic charges to electric capacity C1;
Described comparison circuit compares the voltage of a reference voltage V 1 and described electric capacity C1, and when the voltage of described electric capacity C1 is greater than described reference voltage V 1, control described discharge circuit and carry out repid discharge to described electric capacity C1, the voltage signal of described electric capacity C1 just defines described triangular wave oscillation signal.
8. PWM/PFM control circuit according to claim 7, is characterized in that,
Described charging circuit also comprises PMOS transistor MP9 and MP10, and described discharge circuit comprises a discharge control switch, and described comparison circuit comprises comparator com1,
The input of described oscillator receives the first current signal IA and the second current signal IB, and the negative pole of the 3rd current source I3 is connected with the input of described oscillator, the plus earth of the 3rd current source I3; The source electrode of PMOS transistor MP9 is all connected with a power end with the source electrode of MP10, and the grid of PMOS transistor MP9 is connected with the drain electrode of himself, and the drain electrode of PMOS transistor MP9 is connected with the input of described oscillator; The grid of PMOS transistor MP10 is connected with the grid of PMOS transistor MP9, and the drain electrode of PMOS transistor MP10 is connected with described electric capacity C1 one end, the other end ground connection of electric capacity C1; Described discharge control switch is in parallel with described electric capacity C1; The first input end of comparator com1 is connected with the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1, second input of comparator com1 is connected with reference voltage V 1, the output of comparator com1 is connected with the control end of discharge control switch, and the connected node between the drain electrode of PMOS transistor MP10 and electric capacity C1 exports triangular wave oscillation signal as the output of oscillator.
9. PWM/PFM control circuit according to claim 8, is characterized in that,
The first input end of described comparator com1 and the second input are respectively positive input and the negative-phase input of comparator com1;
Described discharge control switch is nmos pass transistor MN9, and nmos pass transistor MN9 drain electrode is connected with one end of described electric capacity C1, and its source electrode is connected with the other end of described electric capacity C1, and its grid is connected with the output of described comparator com1.
10. PWM/PFM control circuit according to claim 1, is characterized in that,
The peak value of described triangular wave oscillation signal is fixed value, and its valley is fixed value.
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