CN104967412B - A kind of differential pair input circuit that mutual conductance is constant - Google Patents
A kind of differential pair input circuit that mutual conductance is constant Download PDFInfo
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- CN104967412B CN104967412B CN201510309771.3A CN201510309771A CN104967412B CN 104967412 B CN104967412 B CN 104967412B CN 201510309771 A CN201510309771 A CN 201510309771A CN 104967412 B CN104967412 B CN 104967412B
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Abstract
The invention discloses a kind of differential pair input circuit that novel mutual conductance is constant, the differential pair input circuit includes NMOS differential input pair and PMOS Differential Inputs pair, and the NMOS differential input pair and the tail current source numerical value of PMOS Differential Inputs pair are, the differential pair input circuit is by monitoring the voltage of the intermediate node A of PMOS Differential Inputs pair and the intermediate node B of NMOS differential input pair and being switched on or off by the floating of its voltage value with controlling 3 times of tail current source switching tubesCurrent source, it is describedCurrent source is connected to input difference to the part as its tail current, the voltage that the present invention passes through monitoring node A, B, whether 3 times of tail current source switching tube bias voltage values are floated to suitable value being opened to control switching tube, mutual conductance and constant is inputted to reach to achieve the purpose that control the variation of differential-pair tail current.
Description
Technical field
The present invention relates to CMOS Analog Circuit Designs fields, and electricity is inputted more particularly to a kind of differential pair that mutual conductance is constant
Road.
Background technology
In rail-to-rail operational amplifier (rail to rail operational amplifier, Rail-to-Rail
OPAMP in) designing, it is desirable that input stage has constant transconductance from power supply low potential to high potential that is, in rail-to-rail voltage range
Function (constant transconductance).And individually PMOS or NMOS differential input are in full voltage range
In cut-off, subthreshold value, linear and four working regions of saturation, mutual conductance maximum value will be changed to by zero.
Since PMOS tube is opened under low gate voltage, end under high gate voltage；And NMOS tube is then on the contrary, it is low
Gate voltage under end, opened under high gate voltage.According to this characteristic, make NMOS differential pair conduct in parallel with PMOS differential pair
When input stage, then NMOS to cut-off when PMOS to open or PMOS to cut-off when NMOS open；At this time circuit across
It leads permanent more than zero.On the other hand, when input voltage is in high or low level, input stage only have NMOS pairs or PMOS to open,
Then total mutual conductance G of circuitM, totalFor：
Or
Wherein kNAnd kpFor proportionality coefficient, its can be kept equal by adjusting circuit size and electrical parameter；ID, NMOSWith
ID, PMOSThe respectively drain-source current of NMOS differential input pair and PMOS Differential Inputs pair.Assuming that parameter k and IdSo that exist with
Lower relationship：
kN=kp=k, ID, NMOS=Id,PMOS=Id (3)
Then when input voltage is high and low level, circuit mutual conductance is constant.And when input voltage be in compared with median when,
PMOS Differential Inputs pair and NMOS differential is set to input to being switched on and when in saturation region, the mutual conductance of circuit at this time is：
This numerical value is twice when input voltage is in higher or lower level.At this time in the input range of full voltage
Interior, Differential Input is not steady state value to the mutual conductance of pipe.Therefore need to change circuit structure to realize constant transconductance.
In the prior art a kind of available circuit structure for realizing constant transconductance be by change input to the tail current of pipe come
Keep its mutual conductance constant under different input voltages.Its schematic diagram is as shown in Figure 1.PM1, PM2 pipe be PMOS Differential Inputs pair, NM1,
NM2 pipes are NMOS differential input pair；ITail, NMOSAnd ITail, PMOSRespectively NMOS differential input pair and PMOS Differential Inputs pair
Tail current source, and adjusting circuit parameter makes：
ITail, NMOS=ITail, PMOS=Itail (5)
NM3 and PM3 pipes are switching tube, and gate voltage is respectively VBIASN and VBIASP；3XCM_N and 3XCM_P points of module
It Wei 1:3 and 3:1 current-mirror structure, by by the leakage current of NM3 and PM3 amplify 3 times be input to NMOS differential input pair and
The source electrode of PMOS Differential Inputs pair.
Its concrete operating principle is as described below：
When input voltage is in rail-to-rail voltage range, change the tail of PMOS Differential Inputs pair and NMOS differential input pair
Electric current makes its drain current be changed so that its mutual conductance changes.Wherein VAAnd VBThe respectively voltage of A nodes and B node；VthNWith
VthPThe respectively threshold voltage of NMOS differential input pair and PMOS Differential Inputs pair.
1. as 0≤Vin＜ VthN+VBWhen, NMOS differential input pair gate source voltage less than VthN to be in cut-off region,
PMOS Differential Inputs are to being in saturation region.Total mutual conductance G of input pairM, totalFor：
2. working as VA+|VthP|≤Vin＜ VDDWhen, the gate source voltage absolute values of PMOS Differential Inputs pair less than VthP absolute values from
And it is in cut-off region, NMOS differential input is to being in saturation region, total mutual conductance G for inputting coupleM, totalFor：
3. working as VthN+VB＜ Vin＜ VA+|VthP| when, the gate source voltage absolute value of PMOS is higher than VthP absolute values and NMOS
Differential Input is to the gate source voltage of Differential Input pair higher than VthN to all in open state, at this time total mutual conductance of input pair
For：
Due to ID, NMOSWith VinI while increasing and increaseD, PMOSWith VinIncrease and reduce, so its square root it
The variable quantity of sum is smaller.Particularly when PMOS, NMOS differential input are to all in saturation region, GM, totelSize is：
It is constant to the mutual conductance in full voltage range that input difference is realized at this time, and here it is 3 times of current mirror mutual conductances are constant
Principle.
A kind of physical circuit that realizing the available circuit structure such as Fig. 2.NM4 and PM4 pipes are as NMOS differential input pair
With the tail current source of PMOS Differential Inputs pair；NM3 and PM3 are as switching tube；NM5, NM6 pipe form 3 times of current mirror module 3XCM_
N, PM5, PM6 pipe form 3 times of current mirror module 3XCM_P.
The circuit theory is as previously described.But in the structure, individually electricity is done with such a MOSFET of PM4 or NM4
Stream source, while changing with input common mode voltage, A, B node voltage can be such that its current value changes, especially when switching tube exists
In the state of unlatching, the drain-source voltage of switching tube is larger, and tail current source capsule NM4, PM4 is forced to enter linear zone sometimes, to
Influence current source current precision.On the other hand gate voltage VBIAS5, VBIAS6 of 3 times of tail current source switching tubes PM3, NM3 are required
Precision is higher, this is life of relatively having difficult labour in circuit, and under the variation of the conditions such as manufacturing process, supply voltage and temperature,
The bias voltage of required voltage bias and generation is all changing, and the bias voltage generated under certain limiting cases may not be inconsistent
Close circuit requirement, this great limit value performance of circuit.
In the theory of 3 times of current mirror constant transconductance circuits using input to pipe from opening to during shutdown, cause B to save
Point current potential VBReduction, as shown in Figure 2 so that the V of NM3 pipesgsIncrease, until Vgs≥VthNWhen, NM3 pipes are opened so that entire 3 times
Current mirror module 3XCM_P is opened, and similarly opens 3XCM_N modular circuits, to make NMOS and PMOS input to pipe complementary output electricity
Stream, to keep entire input pipe mutual conductance constant.And the variation of B points current potential can bring tail current source current value in this process
Variation.Especially switching tube NM3, PM3, when common mode input is in median, it is desirable that switching tube NM3, PM3, which are in, to close
Under disconnected state, leakage current is small, then requires switching tube raceway groove long enough and breadth length ratio is sufficiently small；And when common mode input is in pole
In the case of end, then requires switching tube NM3, PM3 unlatching and conducting resistance is sufficiently small, this requires its raceway groove long ratios short and wide enough
It is sufficiently large.This is not easy to reconcile to contradiction, often occur in some circuit analyses switching tube open while its drain-source voltage too
Greatly, tail current source capsule is caused to be in linear zone.On the other hand, 3 times of current mirror constant transconductance circuit requirements generate accurate biasing
Voltage VBIASN, VBIASP, as shown in Fig. 2, which increase the design complexities of circuit；Simultaneously in some extreme circuit works
Under skill, environment, power conditions, the bias voltage of generation is most probably no longer complies with circuit requirement.
Invention content
In order to overcome the deficiencies of the above existing technologies, purpose of the present invention is to provide a kind of differential pairs that mutual conductance is constant
3 times of tail current source switching tube bias voltage values are floated to suitable value by input circuit by the voltage of monitoring node A, B
Whether unlatching to control switching tube, to reach the variation of control differential-pair tail current to reach input mutual conductance and constant mesh
's；Monitor A simultaneously, the circuit of B node voltage will not influence the current value of tail current pipe NM4, PM4 in turn.
In view of the above and other objects, the present invention proposes a kind of differential pair input circuit that mutual conductance is constant, the differential pair
Input circuit includes that NMOS differential is inputted to (NM1, NM2 are managed) with PMOS Differential Inputs to (PM1, PM2 are managed), the NMOS differential
Input pair and the tail current source numerical value of PMOS Differential Inputs pair are I0, the differential pair input circuit is by monitoring PMOS difference
The voltage of the intermediate node A of the input pair and intermediate node B of NMOS differential input pair simultaneously floats by its voltage value to control 3 times
Tail current source switching tube (NM3, PM3) is switched on or off 3I0Current source, the 3I0Current source is connected to input difference to as it
A part for tail current.
Further, the differential pair input circuit includes：
Input difference is to basic circuit, for amplifying input signal, including NMOS input differences to pipe (NM1, NM2),
PMOS input differences are to pipe (PM1, PM2) and respective tail current source (NM3, PM3)；
NMOS differential input is to 3 times of current source modules, for being turned on and off 3 times of constant currents of N-type according to input voltage dynamic
Source, including 3 times of current source probe tubes (NM6, NM7) of N-type, 3 times of current supply switch circuits (NM4) of N-type and 3 times of current sources of N-type
(NM5)；
3 times of current source modules of PMOS Differential Inputs pair, for being turned on and off 3 times of constant currents of p-type according to input voltage dynamic
Source, including 3 times of current source probe tubes (PM6, PM7) of p-type, 3 times of current supply switch circuits (PM4) of p-type and 3 times of current sources of p-type
(PM5)。
Further, the drain electrode of the source electrode, NMOS tube (NM6) of the PMOS tube (PM3, PM5, PM7) connects power supply, described
The drain electrode of the source electrode, PMOS tube PM6 of NMOS tube (NM3, NM5, NM7) connects power ground, and PMOS tube (PM5) drain electrode connects PMOS tube
(PM4) source electrode, PMOS tube (PM3, PM4) drain electrode and PMOS tube (PM1, PM2) source electrode and NMOS tube NM6 grids form the section
Point A, the PMOS tube (PM7) drains and is connected to the PMOS tube (PM4) grid after PMOS tube (PM6) source series, described
PMOS tube (PM7) grid connects bias voltage (VBIAS3), and PMOS tube (PM5) grid and the PMOS tube PM3 grids connect
And it is connected to p-type tail current bias voltage (VBIAS1), NMOS tube (NM1) grid and the PMOS tube (PM1) grid phase
Positive input terminal (VIN) is connect and is connected to, NMOS tube (NM2) grid and the PMOS tube (PM2) grid connect and be connected to
The drain electrode of positive input terminal (VIP), the PMOS tube (PM1, PM2) and NMOS tube (NM1, NM2) is output node, the NMOS tube
(NM5) drain electrode connects NMOS tube (NM4) source electrode, NMOS tube (NM3, the NM4) drain electrode and NMOS tube (NM1, NM2) source electrode and
PMOS tube (PM6) grid forms node B, is connected to after NMOS tube (NM7) drain electrode and NMOS tube NM6 source series described
NMOS tube (NM4) grid, NMOS tube (NM7) grid connect bias voltage (VBIAS4), NMOS tube (NM5) grid and
NMOS tube (NM3) grid connects and is connected to N-type tail current bias voltage (VBIAS2), and each NMOS tube substrate meets NWL, each PMOS
Tube lining bottom meets PWL.
Further, the current value of the NMOS tube (NM5) is set as 3 times of tail current source NMOS tube (NM3).
Further, the current value of the PMOS tube (PM5) is set as 3 times of tail current source PMOS tube (PM3).
Further, bias voltage (VBIAS1, VBIAS2) and the ruler of the PMOS tube (PM3), NMOS tube (NM3) are adjusted
It is very little to keep PM3 pipes equal with the drain current of NM3 pipes.
Further, in the input range of full voltage, ensure PMOS tube (PM3) and NMOS tube (NM3) pipe all in full
The area and.
Further, adjusting NMOS tube (NM6, NM7) pipe makes turning off the PMOS Differential Inputs when common mode input
Clock synchronization is just turned on the NMOS tube (NM4) pipe.
Further, adjusting PMOS tube (PM6, PM7) makes turning off the NMOS differential input pair when common mode input
When be just turned on the PMOS tube (PM4 pipes).
Further, the PMOS tube (PM5) is used as p-type current source, and the W of the PMOS tube (PM5) is the PMOS
Manage 3 times of (PM3), the L and gate voltage of the PMOS tube (PM5) and the PMOS tube (PM3) it is identical；The NMOS tube
(NM5) it is used as N-type current source, and 3 times that the W of the NMOS tube (NM5) is the NMOS tube (NM3), the NMOS tube (NM5)
L and gate voltage and the NMOS tube (NM3) it is identical.
Compared with prior art, a kind of differential pair input circuit that mutual conductance is constant of the present invention is in NMOS, PMOS parallel connection difference
In the circuit of input pair, being turned on and off for 3 times of tail current sources is controlled by the voltage value of monitoring node A, B, from without
Circuit is wanted additionally to generate the accurate bias voltage VBIASN (Fig. 1) of 3 times of tail current source switching tubes, VBIAS5 (Fig. 2), VBIASP
(Fig. 1) VBIAS6 (Fig. 2)；And switching tube can be reduced to inputting the influence to tail current source current value.
Description of the drawings
Fig. 1 is traditional 3 times of current mirror constant transconductance structure principle charts；
Fig. 2 is that 3 times of current mirror constant transconductance circuits of tradition realize circuit diagram；
Fig. 3 is a kind of structure diagram for the differential pair input circuit that mutual conductance is constant of the present invention；
Fig. 4 is the realization circuit diagram of Fig. 3.
Specific implementation mode
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
The present invention is modified traditional 3 times of current-mirror structures (as shown in Figure 1), is illustrated in figure 3 the knot of the present invention
Structure block diagram.NMOS differential input for NM1, NM2 to managing；PMOS Differential Inputs for PM1, PM2 to managing；Its tail current source numerical value is
I0.Suitable voltage is floated to control 3 times of tail current source switching tubes by the voltage of monitoring node A, B and by its voltage value
NM3, PM3 are switched on or off 3I0Current source.3I0Current source is connected to input difference to the part as its tail current.
A kind of realization circuit of Fig. 3 structure of the invention block diagrams as shown in Figure 4, including input difference to basic circuit 10,
NMOS differential is inputted to 3 times of 3 times of current source modules 20, PMOS Differential Inputs pair current source modules 30.Input difference is to substantially electric
Road 10 for amplifying input signal, including NMOS input differences to pipe NM1-NM2, PMOS input difference to pipe PM1-PM2 and
Respective tail current source NM3, PM3, breadth length ratio areIts current value size is all I0；NMOS differential is inputted to 3
Times current source module 20 is used to be turned on and off 3 times of constant-current sources of N-type, including 3 times of electric current source samplings of N-type according to input voltage dynamic
Pipe NM6-NM7,3 times of current supply switch circuit NM4 of N-type and N-type 3 times of current sources NM5, NM5 current value be set as tail current
3 times of source NM3, i.e. 3I0；3 times of current source modules 30 of PMOS Differential Inputs pair are used to be turned on and off P according to input voltage dynamic
3 times of constant-current sources of type, including 3 times of 3 times of current source probe tube PM6-PM7 of p-type, 3 times of current supply switch circuit PM4 of p-type and p-type electricity
The current value of stream source PM5, PM5 are set as 3 times of tail current source PM3, i.e. 3I0。
The drain electrode of the wherein source electrode of PMOS tube PM3, PM5, PM7, NMOS tube NM6 meets power vd D, NMOS tube NM3, NM5,
The drain electrode of the source electrode, PMOS tube PM6 of NM7 connects power ground, and PMOS tube PM5 drain electrodes meet PMOS tube PM4 source electrodes, PMOS tube PM3-PM4
Drain electrode and PM1-PM2 source electrodes and NMOS tube NM6 grids form node A, are connected after PMOS tube PM7 drain electrodes and PM6 source series
To PMOS tube PM4 grids, PMOS tube PM7 grids meet bias voltage VBIAS3, and PMOS tube PM5 grids and PM3 grids connect and connect
It is connected to p-type tail current bias voltage VBIAS1, NMOS tube NM1 grids and PMOS tube PM1 grids connect and be connected to positive input terminal
VIN, NMOS tube NM2 grids and PMOS tube PM2 grids connect and are connected to positive input terminal VIP, PMOS tube PM1-2 and NMOS tube
The drain electrode of NM1-2 is output node iout-p-, iout-p+, iout-n-, iout-n+, and NMOS tube NM5 drain electrodes meet NMOS tube NM4
Source electrode, NMOS tube NM3-4 drain electrodes and NM1-2 source electrodes and PMOS tube PM6 grids form node B, NMOS tube NM7 drain electrodes and NM6
Be connected to NMOS tube NM4 grids after source series, NMOS tube NM7 grids meet bias voltage VBIAS4, NMOS tube NM5 grids and
NM3 grids connect and are connected to N-type tail current bias voltage VBIAS2, and each NMOS tube substrate meets NWL, and each PMOS tube substrate connects
PWL。
Such as preceding analysis：
1. as 0≤Vin＜ VthN+VBWhen, NMOS differential input pair gate source voltage less than VthN to be in cut-off region,
PMOS Differential Inputs are to being in saturation region.Total mutual conductance G of input pairM, totalFor：
2. working as VA+|VthP|≤Vin＜ VDDWhen, the gate source voltage absolute values of PMOS Differential Inputs pair less than VthP absolute values from
And it is in cut-off region, NMOS differential input is to being in saturation region, total mutual conductance G for inputting coupleM, totalFor：
3. working as VthN+VB＜ Vin＜ VA+|VthP| when, the gate source voltage absolute value of PMOS is higher than VthP absolute values and NMOS
Differential Input is to the gate source voltage of Differential Input pair higher than VthN to all in open state, at this time total mutual conductance of input pair
For：
Due to ID, NMOSWith VinI while increasing and increaseD, PMOSWith VinIncrease and reduce, so its square root it
The variable quantity of sum is smaller.Particularly when PMOS, NMOS differential input are to all in saturation region, GM, totalSize is：
It is constant to the mutual conductance in full voltage range that input difference is realized at this time.
The present invention changes from principle, by the voltage of monitoring node A, B, inputs to Voltage change modules to control
3I processed0Whether current source is opened, 3I0A part of tail current of the current source as differential pair.Voltage change modules are CMOS
Circuit, input gate resistance theory is infinity, so theory analysis Voltage change modular circuits will not shadow in turn
Ring the voltage of A, B node.
The present invention can apply in the design of the rail-to-rail operational amplifier in 55nm CMOS technologies.
The input stage of rail-to-rail operational amplifier is required from power supply low-voltage to high voltage, i.e., defeated in rail-to-rail voltage
Entering has constant mutual conductance in range.Apply the present invention in 3 times of current mirror constant transconductance schematic circuits, as shown in Figure 4.It can
See, following constraints should be met：
1, the size of adjusting two bias voltages of VBIAS1, VBIAS2 and PM3, NM3 pipe makes the leakage of PM3 pipe and NM3 pipes
Electrode current is equal；
2, in the input range of full voltage, ensure PM3 and NM3 pipes all in saturation region；
3, the gate voltage and breadth length ratio for adjusting NM5 and PM5 pipes make it be saturated the output that output current value is NM3 and PM3 pipes
3 times of value；The grid short circuit of specifically NM5 and NM3 pipes, PM5 and PM3 pipes, and the grid width of NM5 pipes is than 3 times for NM3 pipes, PM5 pipes
Grid width than 3 times for PM3 pipes；The grid length of NM5 pipes is equal to PM3 equal to NM3, the grid length of PM5；
4, adjusting NM6, NM7 pipe makes to be just turned on NM4 pipes in shutdown PMOS inputs clock synchronization when common mode input；
5, adjusting PM6, PM7 pipe makes to be just turned on PM4 pipes in shutdown NMOS inputs clock synchronization when common mode input.
In conclusion a kind of differential pair input circuit that mutual conductance is constant of the present invention is in NMOS, PMOS parallel connection Differential Input pair
Circuit in, being turned on and off for 3 times of tail current sources is controlled by the voltage value of monitoring node A, B, without circuit
Additionally generate accurate bias voltage VBIASN (Fig. 1) VBIAS5 (Fig. 2), the VBIASP (Fig. 1) of 3 times of tail current source switching tubes
VBIAS6 (Fig. 2)；And switching tube can be reduced to inputting the influence to tail current source current value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Field technology personnel can without violating the spirit and scope of the present invention, and modifications and changes are made to the above embodiments.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (9)
1. a kind of differential pair input circuit that mutual conductance is constant, it is characterised in that：The differential pair input circuit includes：
Input difference is to basic circuit, for amplifying input signal, including NMOS input differences to pipe, PMOS input differences to pipe
And respective tail current source；
3 times of current source modules are wrapped in NMOS differential input for being turned on and off 3 times of constant-current sources of N-type according to input voltage dynamic
Include 3 times of 3 times of current source probe tubes of N-type, 3 times of current supply switch circuits of N-type and N-type current sources；
3 times of current source modules of PMOS Differential Inputs pair are wrapped for being turned on and off 3 times of constant-current sources of p-type according to input voltage dynamic
Include 3 times of 3 times of current source probe tubes of p-type, 3 times of current supply switch circuits of p-type and p-type current sources；
The NMOS differential input pair and the current value of PMOS Differential Inputs pair and respective tail current source are I0, the N-type
The current value of 3 times of current sources is 3 times of the tail current source, and the current value of 3 times of current sources of the p-type is the tail current source
3 times, the centre that the differential pair input circuit passes through the intermediate node A and NMOS differential input pair of monitoring PMOS Differential Inputs pair
The voltage of node B is simultaneously switched on or off 3 times of electric currents of 3 times of current sources of N-type or p-type by the floating of its voltage value to control tail current source
Source, 3 times of current sources of 3 times of current sources of the N-type or p-type are connected to input difference to the part as its tail current.
2. a kind of differential pair input circuit that mutual conductance is constant as described in claim 1, it is characterised in that：
The NMOS input differences include the first NMOS tube and the second NMOS tube to pipe, and the PMOS input differences include the to pipe
One PMOS tube and the second PMOS tube, the NMOS input differences are third NMOS tube to the tail current source of pipe, the PMOS inputs
The tail current source of differential pair tube is third PMOS tube, and 3 times of current source probe tubes of the N-type are the 6th NMOS tube and the 7th NMOS
Pipe, 3 times of current supply switch circuits of the N-type are the 4th NMOS tube, and 3 times of current sources of the N-type are the 5th NMOS tube, the p-type 3
Times current source probe tube is the 6th PMOS tube and the 7th PMOS tube, and 3 times of current supply switch circuits of the p-type are the 4th PMOS tube,
3 times of current sources of the p-type are the 5th PMOS tube；
The drain electrode of source electrode, the 6th NMOS tube of the source electrode of the third PMOS tube, the source electrode of the 5th PMOS tube, the 7th PMOS tube connects
Power supply, the source electrode of the third NMOS tube, the source electrode of the 5th NMOS tube, the 7th NMOS tube source electrode, the 6th PMOS tube drain electrode
Connect power ground, the 5th PMOS tube drain electrode connects the 4th PMOS tube source electrode, the drain electrode of third PMOS tube, the drain electrode of the 4th PMOS tube and the
One PMOS tube source electrode, the second PMOS tube source electrode and the 6th NMOS tube grid form the node A, the 7th PMOS tube drain electrode
With the 4th PMOS tube grid is connected to after the 6th PMOS tube source series, the 7th PMOS tube grid connects third biased electrical
Pressure, the 5th PMOS tube grid and the third PMOS tube grid connect and are connected to p-type tail current bias voltage, and described the
One NMOS tube grid and the first PMOS tube grid connect and are connected to the first positive input terminal, the second NMOS tube grid and
The second PMOS tube grid connects and is connected to the second positive input terminal, the drain electrode of first PMOS tube, the second PMOS tube
Drain electrode and the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube are output node, and the 5th NMOS tube drain electrode connects the 4th
NMOS tube source electrode, third NMOS tube drain electrode, the drain electrode of the 4th NMOS tube and the first NMOS tube source electrode, the second NMOS tube source electrode with
And the 6th PMOS tube grid form node B, be connected to after the 7th NMOS tube drain electrode and the 6th NMOS tube source series described
4th NMOS tube grid, the 7th NMOS tube grid meet the 4th bias voltage, the 5th NMOS tube grid and the 3rd NMOS
Tube grid connects and is connected to N-type tail current bias voltage, and each NMOS tube substrate lead connects high potential, each PMOS tube substrate lead
Connect low potential.
3. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：5th NMOS tube
Current value be set as 3 times of third NMOS tube.
4. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：5th PMOS tube
Current value be set as 3 times of third PMOS tube.
5. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：Adjust p-type tail current
Bias voltage makes third PMOS tube and with N-type tail current bias voltage and the third PMOS tube, the size of third NMOS tube
The drain current of three NMOS tubes is equal.
6. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：In the input of full voltage
In range, ensure third PMOS tube and third NMOS tube pipe all in saturation region.
7. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：Adjust the 6th NMOS tube
Make to be just turned on the 4th NMOS tube in the shutdown PMOS Differential Inputs clock synchronization when common mode input with the 7th NMOS tube.
8. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：Adjust the 6th PMOS tube
Make to be just turned on the 4th PMOS tube in the shutdown NMOS differential input clock synchronization when common mode input with the 7th PMOS tube.
9. a kind of differential pair input circuit that mutual conductance is constant as claimed in claim 2, it is characterised in that：5th PMOS tube
As p-type current source, and the grid width of the 5th PMOS tube is than 3 times for the third PMOS tube, the 5th PMOS tube
Grid length and gate voltage and the third PMOS tube it is identical；5th NMOS tube is as N-type current source, and the 5th NMOS
The grid width of pipe is than 3 times for the third NMOS tube, the grid length and gate voltage of the 5th NMOS tube and the third NMOS tube
It is identical.
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