CN104934005B - Display panel and display device - Google Patents
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- CN104934005B CN104934005B CN201510379531.0A CN201510379531A CN104934005B CN 104934005 B CN104934005 B CN 104934005B CN 201510379531 A CN201510379531 A CN 201510379531A CN 104934005 B CN104934005 B CN 104934005B
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Abstract
The invention provides a display panel and a display device, belongs to the display technology field, and helps to solve the problem that the frame of a conventional display panel is wide. The display panel comprises a display area and surrounding areas. The display area includes multiple grid lines and multiple data lines, the grid lines and the data lines crossing each other. The grid lines and the data lines cross each other to define multiple pixel units. At least one grid line includes at least two grid line segments that are disconnected from each other, and each grid line segment correspondingly controls at least one pixel unit. The display area is divided into at least two sub-display areas according to the disconnection positions of the grid line segments. A shift register unit connected to the grid line segments is arranged in at least one sub-display area, and is used for providing grid scan signals to the grid line segments connected to the shift register unit. At least part of the shift register units are arranged in the display area, so the frame of the display panel is narrow.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
The basic principle of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) for displaying one frame of picture is to input a square wave with a certain width to each row of pixels in sequence from top to bottom through gate (gate) driving, and then output signals required for driving each row of pixels from top to bottom through source (source) in sequence. At present, a gate driving circuit and a source driving circuit are usually manufactured On a Glass panel through a COF (Chip On Film) or COG (Chip On Glass) process, but when the resolution is high, the output of the gate driving circuit and the output of the source driving circuit are both high, the length of the driving circuit is increased, and the Bonding process of the module driving circuit is not facilitated.
In order to overcome the above problems, the conventional display device is manufactured by adopting a design of a goa (gate Drive On array) circuit, which not only saves cost, but also can achieve an aesthetic design of panel bilateral symmetry, and simultaneously can save a Bonding area and a peripheral wiring space of a gate driving circuit, thereby realizing the design of a narrow frame of a display device and improving the productivity and yield of the display device. However, with the increase of the resolution and size of the display panel, the load of each GOA increases, that is, the size of the Thin Film Transistor (TFT) of each shift register in the GOA circuit is larger, thereby causing the charging of the pixel to be more difficult and the frame of the corresponding display panel to be wider.
Disclosure of Invention
The present invention provides a display panel and a display device with a narrow frame and a uniform display effect, aiming at the above problems of the existing display panel.
The technical scheme adopted for solving the technical problem is that the display panel comprises a display area and a peripheral area, wherein the display area comprises a plurality of grid lines and a plurality of data lines which are arranged in a crossed mode, the grid lines and the data lines are crossed to define a plurality of pixel units, at least one grid line comprises at least two grid line segments which are arranged in a disconnected mode, each grid line segment correspondingly controls at least one pixel unit, the display area is divided into at least two sub-display areas according to the disconnected position of the grid line segment, a shift register unit connected with the grid line segment is arranged in at least one sub-display area, and the shift register unit is used for providing grid scanning signals for the grid line segment connected with the shift register unit.
Preferably, each gate line includes at least two gate line segments arranged in a disconnected manner, and the gate line segments located in the same row are connected to at least one shift register unit.
It is further preferable that the gate line segments in each row of the gate lines have the same disconnection position, each gate line segment located in the same sub-display region is connected to a different shift register unit, and the shift register units driving the gate line segments in the same sub-display region are cascaded together.
It is further preferable that each of the gate line segments in each of the gate lines in each row is connected to a separate shift register unit, and the shift register units located in the same sub-display region are cascaded together.
Still further preferably, the display region includes three sub-display regions, each of the gate lines is divided into three gate line segments, and each of the sub-display regions includes the same gate line segment of all the gate lines.
It is further preferable that each of the gate lines includes a plurality of gate line segments having the same length, the gate line segments located in the same sub-display region are respectively connected to different shift register units, and the shift register units located in the same sub-display region are cascaded together.
Preferably, the shift register unit is connected to a plurality of signal lines, and the signal lines are arranged in parallel with the data lines.
Preferably, the shift register unit includes 9 switch units and a storage capacitor, the gate line segment correspondingly controls 9 pixel units, each pixel unit is provided with one switch unit, and the storage capacitor is arranged in one of the pixel units.
More preferably, the 9 switching units are corresponding first to ninth transistors; wherein,
the first pole of the first transistor is connected with the control pole and the signal input end of the first transistor, and the second pole of the first transistor is connected with the first end of the storage capacitor;
the first pole of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the low power supply end, and the control pole of the second transistor is connected with the reset signal end;
a first pole of the third transistor is connected with the clock signal input end, a second pole of the third transistor is connected with the second end of the storage capacitor and the signal output end, and a control pole of the third transistor is connected with the first end of the storage capacitor;
a first electrode of the fourth transistor is connected with the second end of the storage capacitor and the signal output end, a second electrode of the fourth transistor is connected with a low power supply end, and a control electrode of the fourth transistor is connected with a second electrode of the fifth transistor;
the first pole of the fifth transistor is connected with the high-voltage end, the second pole of the fifth transistor is connected with the first poles of the sixth transistor and the seventh transistor, and the control pole of the fifth transistor is connected with the second pole of the ninth transistor;
the first electrode of the sixth transistor is connected with the control electrode of the fourth transistor, the second electrode of the sixth transistor is connected with the low power supply end, and the control electrode of the sixth transistor is connected with the first end of the storage capacitor;
the first electrode of the seventh transistor is connected with the control electrode of the fourth transistor, the second electrode of the seventh transistor is connected with the low power supply end, and the control electrode of the seventh transistor is connected with the first end of the storage capacitor;
a first pole of the eighth transistor is connected with a second pole of the ninth transistor, the second pole of the eighth transistor is connected with a low power supply end, and a control pole of the eighth transistor is connected with a control pole of the sixth transistor;
and the first pole of the ninth transistor is connected with the control pole and the high-voltage end, and the second pole of the ninth transistor is connected with the control pole of the fifth transistor.
The clock signal end is arranged in parallel to the data line; the signal input end is a grid line; the first transistor to the ninth transistor are respectively located in the pixel unit between nine data lines, specifically, the ninth transistor is located between the first data line and the second data line, the eighth transistor is located between the second data line and the third data line, the fifth transistor is located between the third data line and the fourth data line, the sixth transistor is located between the fourth data line and the fifth data line, the seventh transistor is located between the fifth data line and the sixth data line, the fourth transistor is located between the sixth data line and the seventh data line, the first transistor is located between the seventh data line and the eighth data line, the third transistor is located between the eighth data line and the ninth data line, and the second transistor is located on the other side of the ninth data line away from the eighth data line; particularly, the first electrode of the first transistor and the control electrode thereof are connected with a row of grid lines, namely signal input ends; the second pole of the third transistor and the first pole of the fourth transistor are connected with the grid line of the row, namely the signal output end; the grid electrode of the second transistor is connected with the next row of grid lines; the storage capacitor is arranged between the eighth data line and the ninth data line.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the display panel.
The invention has the following beneficial effects:
in the display panel of the present invention, at least one of the sub-display regions is provided with a shift register unit connected to the gate line segment, that is, at least a part of the shift register units are disposed in the display region of the display panel, so that it can be understood that the number of the shift register units in the peripheral region of the display panel is smaller than that of the shift register units in the peripheral region of the display panel, and the position of the remaining shift register units can be reasonably arranged to make the frame of the display panel narrower; in addition, in the invention, at least part of the grid lines are divided into a plurality of grid line segments, and compared with the existing load connected with the grid lines, the load connected with the grid line segments is obviously reduced, so that the driving capability of the shift register unit can be improved, the problem of voltage drop of the grid lines is solved, and the display of the display panel is more uniform.
The display device of the invention comprises the display panel, so the display device has better display effect and narrower frame.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to embodiments 1 and 2 of the present invention;
fig. 2 is a schematic view of a preferred structure of a display panel according to embodiment 2 of the present invention;
fig. 3 is a circuit diagram of a shift register unit of a display panel in embodiments 1 to 5 of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
the embodiment provides a display panel, which includes a display area and a peripheral area, wherein the display area includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of pixel units, at least one gate line includes at least two gate line segments, the gate line segments are disconnected, each gate line segment correspondingly controls at least one pixel unit, the display area is divided into at least two sub-display areas according to the disconnection positions of the gate line segments, at least one sub-display area is provided with a shift register unit connected with the gate line segments, and the shift register unit is used for providing gate scanning signals for the gate line segments connected with the shift register unit.
Since in the display panel of this embodiment, at least one of the sub-display regions is provided with the shift register units connected to the gate line segments, that is, at least some of the shift register units are disposed in the display region of the display panel, it can be understood that the number of the shift register units in the peripheral region of the display panel is smaller than that of the shift register units in the peripheral region of the display panel, and the position of the remaining shift register units can be reasonably arranged, so that the frame of the display panel is narrower; in addition, in this embodiment, at least a portion of the gate lines are divided into a plurality of gate line segments, and the load connected to the gate line segments is significantly reduced compared to the existing load connected to the gate lines, so that the driving capability of the shift register unit can be improved, the problem of voltage drop of the gate lines is also alleviated, and the display of the display panel is more uniform.
Each grid line comprises at least two grid line segments which are arranged in a disconnected mode, and the grid line segments located on the same row are connected with at least one shift register unit. That is, the gate line segments in the same row may be driven by one shift register unit, or each gate line segment may be driven by a separate shift register unit. The display panel of example 1 will be further described with reference to the following examples.
Example 2:
as shown in fig. 1, the present embodiment provides a display panel, which includes M gate lines and N data lines arranged in a crossing manner, wherein g (i) is any one of the gate lines, and i is greater than or equal to 1 and less than or equal to M; m is an integer, S (j) is any one of the data lines, and j is more than or equal to 1 and less than or equal to N; n is an integer. The intersection of all the grid lines G (i) and all the data lines S (j) defines a plurality of pixel units A, the disconnection positions of all the grid lines G (i) are the same, and each row of the grid lines G (i) is divided into a plurality of grid line segments g; dividing a display area of the display panel into a plurality of sub-display areas Q arranged at intervals according to the disconnection position of each row of grid lines G (i); each gate line segment g is connected to an independent shift register unit GOA, which is used to provide gate scanning signals for the gate line segment g connected thereto. Each shift register unit GOA in the same sub-display area Q is driven to be cascaded together to form a gate driving circuit.
In this embodiment, each gate line segment g passes through one shift register unit GOA, that is, each shift register unit GOA is only used for driving one gate line segment g, and the size of the thin film transistor required by the shift register unit GOA is not large as compared with the size of the thin film transistor required by the shift register unit GOA for driving the whole gate line g (i). It should be noted that, although the shift register unit GOA is disposed in the area where the pixel unit a is located, that is, the display area will affect the aperture ratio of the display panel, resulting in the reduction of the display brightness, since each gate line segment g is driven by a single shift register unit GOA, the display brightness of the entire display panel is uniformly reduced, and the problem of display non-uniformity does not occur, and for the display brightness, the brightness of the display panel can be increased by increasing the brightness of the backlight source.
Specifically, a display panel including six gate lines G (1) to G (6) and nine data lines S (1) to S (9) is taken as an example; preferably, each row of the gate lines g (i) has three gate line segments g, a width of one gate line segment g corresponds to a width of one sub-display region Q, each sub-display region Q is in a vertical column shape, and each sub-display region Q is spaced in the row direction. Each column is controlled by a gate driving circuit, which is helpful for controlling the gate driving circuit, so that the display is more uniform.
Preferably, each of the gate driving circuits further includes a plurality of signal lines for providing signals to the shift register units GOA, and the plurality of signal lines are disposed in parallel with the data lines s (j). Wherein the plurality of signal lines may include: a signal lead-in line when a signal is introduced from the signal INPUT terminal INPUT, a signal lead-in line when a signal is introduced from the clock signal INPUT terminal CLK, a signal lead-in line when a signal is introduced from the high voltage terminal VGH, and the like.
As shown in fig. 2, fig. 2 only shows a shift register unit GOA connected to a gate line segment g of a gate line g (i), where the shift register unit GOA in this embodiment includes 9 switch units (i.e., M1-M9 shown in the figure) and a storage capacitor C1, the gate line segment correspondingly controls 9 pixel units, each pixel unit a is provided with a switch unit, and the storage capacitor is disposed in one of the pixel units a.
Specifically, the clock signal CLK is arranged in parallel with the data line S (9); the signal INPUT end INPUT is a grid line G (i-1); the first transistor M1 through the ninth transistor M9 are respectively located in the pixel unit between the nine data lines S (1) through S (9), specifically, the ninth transistor M9 is located between the first data line S (1) and the second data line S (2), the eighth transistor M8 is located between the second data line S (2) and the third data line S (3), the fifth transistor M5 is located between the third data line S (3) and the fourth data line S (4), the sixth transistor M6 is located between the fourth data line S (4) and the fifth data line S (5), the seventh transistor M7 is located between the fifth data line S (5) and the sixth data line S (6), the fourth transistor M4 is located between the sixth data line S (6) and the seventh data line S (7), the first transistor M1 is located between the seventh data line S (7) and the eighth data line S (8), the third transistor M3 is located between the eighth data line S (8) and the ninth data line S (9), and the second transistor M2 is located at the other side of the ninth data line S (9) from the eighth data line S (8); specifically, the first electrode of the first transistor M1 and the control electrode thereof are connected to a gate line G (i-1), i.e., a signal input terminal; the second pole of the third transistor M3 and the first pole of the fourth transistor M4 are connected to the gate line g (i), i.e. the signal output end; the gate of the second transistor M2 is connected to the next row of gate lines G (i + 1); the storage capacitor C1 is disposed between the eighth data line S (8) and the ninth data line S (9).
This kind of setting mode can make the even distribution of the switch unit of each in each shift register GOA at different pixel A to make display panel's shading position more even, also make display panel's opening more even promptly, and then make the luminance uniformity of the picture that display panel shows.
As shown in fig. 3, the shift register unit GOA in this embodiment includes 9 switch units corresponding to the first transistor M1 to the ninth transistor M9; a first pole of the first transistor M1 is connected to the control pole thereof and the signal INPUT terminal INPUT, and a second pole is connected to the first end of the storage capacitor C1; a first electrode of the second transistor M2 is connected with a second electrode of the first transistor M1, the second electrode is connected with a low power supply end VGL, and a control electrode is connected with a RESET signal end RESET; a first pole of the third transistor M3 is connected to the clock signal input terminal CLK, a second pole is connected to the second terminal of the storage capacitor C1 and the signal OUTPUT terminal OUTPUT, and a control pole is connected to the first terminal of the storage capacitor C1; a first electrode of the fourth transistor M4 is connected to the second end of the storage capacitor C1 and the signal OUTPUT terminal OUTPUT, a second electrode is connected to the low power source terminal VGL, and a control electrode is connected to the second electrode of the fifth transistor M5; a first pole of the fifth transistor M5 is connected to the high voltage terminal VGH, a second pole is connected to the first poles of the sixth transistor M6 and the seventh transistor M7, and a control pole is connected to the second pole of the ninth transistor M9; the first electrode of the sixth transistor M6 is connected to the control electrode of the fourth transistor M4, the second electrode is connected to the low power supply terminal VGL, and the control electrode is connected to the first end of the storage capacitor C1; the first electrode of the seventh transistor M7 is connected to the control electrode of the fourth transistor M4, the second electrode is connected to the low power supply terminal VGL, and the control electrode is connected to the first end of the storage capacitor C1; the first electrode of the eighth transistor M8 is connected to the second electrode of the ninth transistor M9, the second electrode is connected to the low power source terminal VGL, and the control electrode is connected to the control electrode of the sixth transistor M6; the ninth transistor M9 has a first electrode connected to the control electrode thereof and the high voltage terminal VGH, and a second electrode connected to the control electrode of the fifth transistor M5. Of course, the shift register unit GOA of the present embodiment may be laid out in the above-mentioned case, as long as the shift register unit GOA includes an input module, an output pull-up module, and a reset module.
Wherein, in each row of pixel units a, the shift register unit GOA is located at the opposite side of the gate line segment g connected thereto. The reason for this is that the gate line segment g is connected with a pixel driving circuit for driving the pixel unit a, and the shift register unit GOA is disposed on the opposite side of the gate line segment g, that is, on the opposite side of the pixel driving circuit, so that the distribution of the opaque region of the display panel is more uniform, and the display panel is more uniform when displaying.
Since the shift register unit GOA in the display panel of this embodiment is disposed in the area where the pixel unit a is located, that is, in the display area of the display panel, compared with the existing display panel in which the shift register unit GOA is disposed in the peripheral area, the frame of the display panel of this embodiment is narrower; in addition, in the embodiment, each gate line g (i) is divided into a plurality of gate line segments g, and the load connected to the gate line segments g is significantly reduced compared to the load connected to the gate lines g (i) in the prior art, so that the driving capability of the shift register unit GOA can be improved, the problem of voltage drop of the gate lines g (i) is also alleviated, and the display of the display panel is more uniform.
Example 3:
the present embodiment also provides a display panel, which has a structure similar to that of the display panel in embodiment 2, except that in the display panel of this embodiment, the gate line segments g located in the same row are connected to the same shift register unit GOA, that is, one shift register unit GOA is used to provide a gate scanning signal for one row of gate line segments g.
In this embodiment, since the gate line segments g located in the same row are connected to the same shift register unit GOA, only a plurality of signal OUTPUT terminals OUTPUT need to be added to each shift register unit GOA at this time, the process is simple, and the shift register unit GOA is arranged in the area where the pixel unit a is located, that is, in the display area of the display panel, compared with the existing display panel in which the shift register unit GOA is arranged in the peripheral area, the frame of the display panel of this embodiment is narrower. Other structures of the display panel in this embodiment are the same as those in embodiment 2, and will not be described in detail here.
Example 4:
the present embodiment also provides a display panel, which includes M gate lines and N data lines arranged in a crossing manner, where g (i) is any one of the gate lines and has i being greater than or equal to 1 and less than or equal to M, and s (j) is any one of the data lines and has j being greater than or equal to 1 and less than or equal to N. The intersection of all the grid lines G (i) and all the data lines S (j) defines a plurality of pixel units A, each row of grid lines G (i) is divided into a plurality of grid line segments g, the lengths of the grid line segments g are the same, and the display area of the display panel is divided into a plurality of sub-display areas Q arranged at intervals according to the disconnection position of each row of grid lines G (i); each gate line segment g is connected to an independent shift register unit GOA, which is used to provide gate scanning signals for the gate line segment g connected thereto. Each shift register unit GOA in the same sub-display area Q is driven to be cascaded together to form a gate driving circuit.
Since the lengths of the gate line segments g are the same in the embodiment, but the turn-off positions of the gate lines g (i) and g (i) in each row cannot be guaranteed to be the same, it can be understood that the arrangement of the sub-display regions Q on the display panel may be irregular, but nevertheless, each shift register unit GOA is only used for driving one gate line segment g, and the size of the thin film transistor required by the shift register unit GOA is not large compared with the size of the thin film transistor required by the shift register unit GOA used for driving the whole gate line g (m). It should be noted that, although the shift register unit GOA is disposed in the area where the pixel unit a is located, that is, the display area will affect the aperture ratio of the display panel, resulting in the reduction of the display brightness, since each gate line segment g is driven by a single shift register unit GOA, the display brightness of the entire display panel is uniformly reduced, and the problem of display non-uniformity does not occur, and for the display brightness, the brightness of the display panel can be increased by increasing the brightness of the backlight source.
The structure of the shift register unit in the display panel of this embodiment, and other components, are the same as those in embodiments 1 and 2, and will not be described in detail here.
Example 5:
the present embodiment also provides a display panel, which has a structure similar to that of the display panel in embodiment 4, that is, the lengths of the gate line segments g are the same, except that in the display panel of this embodiment, the gate line segments g in the same row are connected to the same shift register unit GOA, that is, one shift register unit GOA is used to provide a gate scanning signal for the gate line segment g in one row.
In this embodiment, since the gate line segments g located in the same row are connected to the same shift register unit GOA, only a plurality of signal OUTPUT terminals OUTPUT need to be added to each shift register unit GOA at this time, the process is simple, and the shift register unit GOA is arranged in the area where the pixel unit a is located, that is, in the display area of the display panel, compared with the existing display panel in which the shift register unit GOA is arranged in the peripheral area, the frame of the display panel of this embodiment is narrower. The other structures of the display panel in this embodiment are the same as those in embodiment 4, and will not be described in detail here.
Example 6:
the present embodiment provides a display device, which includes the display panel. Therefore, the display panel of the embodiment has better display effect.
The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A display panel comprises a display area and a peripheral area, wherein the display area comprises a plurality of grid lines and a plurality of data lines which are arranged in a crossed mode, and a plurality of pixel units are defined by the grid lines and the data lines in a crossed mode.
2. The display panel according to claim 1, wherein each of the gate lines includes at least two gate line segments arranged in a disconnected manner, and the gate line segments in the same row are connected to at least one of the shift register units.
3. The display panel according to claim 2, wherein the gate line segments in each row of the gate lines have the same disconnection position, each gate line segment in the same sub-display region is connected to a different shift register unit, and the shift register units driving the gate line segments in the same sub-display region are cascaded together.
4. The display panel according to claim 3, wherein each of the gate line segments in each row of the gate lines is connected to a separate shift register unit, and each of the shift register units in the same sub-display region are cascaded together.
5. The display panel of claim 3, wherein the display region comprises three sub-display regions, each gate line is divided into three gate line segments, and each sub-display region comprises the same gate line segment of all gate lines.
6. The display panel according to claim 2, wherein each gate line comprises a plurality of gate line segments with the same length, the gate line segments in the same sub-display region are respectively connected to different shift register units, and the shift register units in the same sub-display region are cascaded together.
7. The display panel according to any one of claims 1 to 6, wherein the shift register unit is connected to a plurality of signal lines, and the signal lines are arranged in parallel with the data lines.
8. The display panel according to any one of claims 1 to 6, wherein the shift register unit comprises 9 switch units and a storage capacitor, the switch units correspondingly control 9 pixel units, each pixel unit is provided with a switch unit, and the storage capacitor is arranged in one of the pixel units.
9. The display panel according to claim 8, wherein the 9 switching units are corresponding first to ninth transistors; wherein,
the first pole of the first transistor is connected with the control pole and the signal input end of the first transistor, and the second pole of the first transistor is connected with the first end of the storage capacitor;
the first pole of the second transistor is connected with the second pole of the first transistor, the second pole of the second transistor is connected with the low power supply end, and the control pole of the second transistor is connected with the reset signal end;
a first pole of the third transistor is connected with the clock signal input end, a second pole of the third transistor is connected with the second end of the storage capacitor and the signal output end, and a control pole of the third transistor is connected with the first end of the storage capacitor;
a first electrode of the fourth transistor is connected with the second end of the storage capacitor and the signal output end, a second electrode of the fourth transistor is connected with a low power supply end, and a control electrode of the fourth transistor is connected with a second electrode of the fifth transistor;
the first pole of the fifth transistor is connected with the high-voltage end, the second pole of the fifth transistor is connected with the first poles of the sixth transistor and the seventh transistor, and the control pole of the fifth transistor is connected with the second pole of the ninth transistor;
the first electrode of the sixth transistor is connected with the control electrode of the fourth transistor, the second electrode of the sixth transistor is connected with the low power supply end, and the control electrode of the sixth transistor is connected with the first end of the storage capacitor;
a control electrode of the seventh transistor is connected with a control electrode of the fourth transistor, a second electrode of the seventh transistor is connected with a low power supply end, and a first electrode of the seventh transistor is connected with a first end of the storage capacitor;
a first pole of the eighth transistor is connected with a second pole of the ninth transistor, the second pole of the eighth transistor is connected with a low power supply end, and a control pole of the eighth transistor is connected with a control pole of the sixth transistor;
and the first pole of the ninth transistor is connected with the control pole and the high-voltage end, and the second pole of the ninth transistor is connected with the control pole of the fifth transistor.
10. A display device characterized in that it comprises a display panel according to any one of claims 1 to 9.
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| CN105139806B (en) * | 2015-10-21 | 2018-05-01 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN105427791B (en) * | 2016-01-04 | 2018-09-11 | 京东方科技集团股份有限公司 | A kind of array substrate and display device |
| CN105575318B (en) * | 2016-03-18 | 2019-02-26 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN105739208A (en) * | 2016-05-13 | 2016-07-06 | 京东方科技集团股份有限公司 | Display device and driving device |
| KR102518746B1 (en) * | 2016-06-01 | 2023-04-07 | 삼성디스플레이 주식회사 | Display device |
| CN106023944B (en) * | 2016-08-03 | 2019-03-15 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN106097968A (en) * | 2016-08-26 | 2016-11-09 | 京东方科技集团股份有限公司 | Display floater and display device |
| CN106873273B (en) * | 2017-02-23 | 2021-01-29 | 京东方科技集团股份有限公司 | Array substrate, partition driving method thereof, display module and display device |
| CN107045850A (en) * | 2017-04-05 | 2017-08-15 | 京东方科技集团股份有限公司 | Array base palte, display panel and display device |
| CN106898324B (en) * | 2017-04-25 | 2019-09-17 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| TWI657699B (en) * | 2017-05-12 | 2019-04-21 | 友達光電股份有限公司 | Display panel |
| CN106952607B (en) * | 2017-05-25 | 2020-04-17 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| CN110265454A (en) * | 2019-06-25 | 2019-09-20 | 上海天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
| US11876100B2 (en) | 2019-11-29 | 2024-01-16 | Boe Technology Group Co., Ltd. | Array substrate and method of manufacturing the same, pixel driving method, and display panel |
| CN111261094A (en) | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Grid driving array type display panel |
| CN111429828A (en) | 2020-04-13 | 2020-07-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| US11798487B2 (en) | 2021-03-01 | 2023-10-24 | Hefei Boe Joint Technology Co., Ltd. | Display panel and display device |
| CN114664245B (en) * | 2022-05-25 | 2022-11-15 | 惠科股份有限公司 | Driving substrate and display panel thereof |
| CN115079477A (en) * | 2022-05-25 | 2022-09-20 | 重庆惠科金渝光电科技有限公司 | Driving substrate and display panel thereof |
-
2015
- 2015-07-01 CN CN201510379531.0A patent/CN104934005B/en not_active Expired - Fee Related
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| CN104934005A (en) | 2015-09-23 |
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