CN104900703A - Trench MOSFET terminal structure, trench MOSFET device and manufacture method thereof - Google Patents

Abstract

The invention discloses a trench MOSFET terminal structure, comprising: a substrate of a first conductivity type; an epitaxial sheet layer of a first conductivity type, which is arranged on one side of the substrate of the first conductivity type; The nip area includes a plurality of first grooves, a first oxide layer is deposited on the groove walls and bottom of the first grooves, and a polysilicon layer is provided inside the first grooves, and the polysilicon A layer is deposited on the groove wall of the first trench, and a second conductivity type injection layer is provided in the first conductivity type epitaxial wafer on both sides and below the first trench; several second voltage dividing regions, It includes a plurality of second trenches, a first oxide layer is deposited on the trench walls and bottom of the second trenches, and a polysilicon layer is deposited in the second trenches. The invention also discloses a trench MOSFET device and a preparation method thereof. The invention reduces the chip area and reduces the production cost.

Description

A trench MOSFET terminal structure and trench MOSFET device and preparation method thereof

technical field

The invention relates to a terminal structure, more precisely a trench MOSFET terminal structure. The invention also discloses a trench MOSFET terminal device and a preparation method thereof.

Background technique

With the continuous maturity of power MOS device technology and design, the competition of power MOS devices at home and abroad is becoming more and more fierce, and it is more and more urgent to reduce the cost of devices and improve the performance and reliability of devices. Under the premise of not affecting the performance of the device, reducing the number of photolithography in the device manufacturing process and reducing the size of the chip are two important means to reduce the cost of the device.

As shown in FIG. 14 , it is a schematic diagram of a reverse withstand voltage simulation of a trench-type power MOS device manufactured by a method for manufacturing a trench-type semiconductor power device in the prior art, and its depletion layer distribution and electric field analysis are observed through simulation analysis, It can be seen that only a small part of the second conductivity type region at the bottom of the first trench outside the two voltage division regions is depleted, and the potential line is relatively loose, the electric field strength is very low, and the withstand voltage effect in the terminal ring is very strong. Small; therefore, the use of large-sized trenches in this area is a complete waste of chip area.

Contents of the invention

The object of the present invention is to provide a trench MOSFET terminal structure, a trench MOSFET device and a preparation method thereof, which can solve the shortcomings of insufficient chip area utilization and high cost in the prior art.

The present invention adopts following technical scheme:

A trench MOSFET termination structure comprising:

a first conductivity type substrate;

A first conductivity type epitaxial layer, which is arranged on one side of the first conductivity type substrate;

A plurality of first voltage dividing regions, which include a plurality of first trenches, a first oxide layer is deposited on the trench walls and bottom of the first trenches, and a polysilicon layer is provided inside the first trenches, and the polysilicon layer is deposited on the groove wall of the first trench, and a second conductivity type injection layer is provided in the first conductivity type epitaxial wafer on both sides and below the first trench;

A plurality of second voltage-dividing regions, including a plurality of second trenches, a first oxide layer is deposited on the trench walls and bottom of the second trenches, and a polysilicon layer is deposited in the second trenches .

Also included is a cut-off zone comprising:

A second groove, which is arranged in the epitaxial layer of the first conductivity type, and a first oxide layer is deposited on the groove wall and groove bottom of the second groove, and in the second groove Depositing a polysilicon layer;

It also includes a first conductivity type injection layer, which is arranged in the second conductivity type injection layer and at the edge of the second conductivity type injection layer.

A contact hole, and impurity of the second conductivity type is injected into the contact hole, which is arranged inside the first trench and the second conductivity type injection layer, and the contact hole arranged in the second conductivity type injection layer is connected to the first conductivity type injection layer contacts;

A second oxide layer, which is provided on the outside of the first oxide layer and the second trench;

A second metal layer is arranged on the outside of the second oxide layer, and the second metal layer is connected with the contact hole.

The width of the first groove is larger than the width of the second groove.

The width of the first trench is greater than or equal to 2um.

A trench MOSFET device including the above-mentioned trench MOSFET terminal structure further includes a drain region electrode disposed on the other side of the substrate of the first conductivity type.

Also includes:

A source electrode, which is connected to the source region and the channel region in the epitaxial wafer layer of the first conductivity type through a contact hole;

a gate electrode, which is connected to the polysilicon in the second trench in the source region through the contact hole;

A method for preparing a trench MOSFET device, comprising the steps of:

growing an epitaxial layer of the first conductivity type doped with the same type on the substrate layer of the first conductivity type;

performing trench etching on the epitaxial wafer layer of the first conductivity type to form a first trench and a second trench;

growing a first oxide layer as gate oxide in the first trench and the second trench;

Depositing polysilicon on the first oxide layer, and performing etching, so that the second trench is completely filled, and polysilicon is deposited on the groove wall of the first trench;

Impurity ions of the second conductivity type are implanted into the first conductivity type epitaxial wafer layer and the first groove, and the second conductivity type implantation layer is formed by heat treatment, and the second conductivity type injection layer is arranged on the first conductivity type epitaxial layer. the upper surface and the lower part of the second trench;

Photoetching an implantation region of the first conductivity type impurity on the surface of the first conductivity type epitaxial layer, implanting the first conductivity type impurity ions, and forming the first conductivity type implantation layer by heat treatment;

depositing a second oxide layer to form a dielectric layer;

Contact hole lithography and etching, the contact hole is in contact with the source region and the channel region,

Depositing a third metal layer, and performing photolithography to form source, gate and stop regions;

Prepare the drain electrode.

Also includes:

Depositing a third oxide layer on the surface of the epitaxial wafer layer of the first conductivity type;

Photolithography and etching are performed on the third oxide layer to form etching windows and masking layers of the first trench and the second trench.

The third oxide layer is removed.

The advantage of the present invention is that: the first voltage dividing region contains several first trenches, and since the first trenches are not completely filled with polysilicon, when the channel region is implanted, impurities of the second conductivity type can be implanted under the trenches , forming the second conductivity type injection layer, when the drain is at a high potential, the second conductivity type injection layer can be completely depleted, and the depletion layer will be extended to the depth of the first conductivity type epitaxial layer; the second voltage division region contains several A small-sized trench, since most of the electric field in the terminal ring is distributed at the bottom of the trench close to the source region, the electric field in the second voltage-dividing region has been significantly reduced, and the second trench in the second voltage-dividing region is replaced. The small-sized groove reduces the chip area and reduces the production cost.

Description of drawings

The present invention is described in detail below in conjunction with embodiment and accompanying drawing, wherein:

FIG. 1 is a structural schematic diagram of a trench MOSFET terminal structure of the present invention.

Fig. 2 to Fig. 13 are structural schematic diagrams of the preparation intermediate of the trench MOSFET device of the present invention.

FIG. 14 is a schematic diagram of reverse withstand voltage simulation of a trench-type power MOS device manufactured by a method for manufacturing a trench-type semiconductor power device in the prior art.

Detailed ways

Further set forth the specific embodiment of the present invention below in conjunction with accompanying drawing:

As shown in Figure 1, a trench MOSFET termination structure includes a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a plurality of first voltage division regions 3, a plurality of second voltage division regions 4 and a Cutoff zone 5. The first and second voltage division areas are used as pressure-resistant rings, most of the electric field is distributed in the first voltage division area, and the second voltage division area further improves the withstand voltage through the second groove, while saving the chip area; the cut-off area is designed by equipotential, Improve device reliability.

The epitaxial layer 2 of the first conductivity type is disposed on one side of the substrate 1 of the first conductivity type. The first voltage dividing region includes a plurality of first trenches 7, a first oxide layer 11 is deposited on the trench walls and bottom of the first trenches 7, and a polysilicon layer is provided inside the first trenches 7 12, and the polysilicon layer 12 is deposited on the groove wall of the first trench 7, and the two sides and the bottom of the first trench 7 are provided with a second conductivity type epitaxial wafer 2 in the first conductivity type Inject layer 9. The second voltage dividing region includes a plurality of second trenches 8, a first oxide layer 11 is deposited on the trench walls and bottom of the second trenches 8, and polysilicon is deposited in the second trenches 8 Layer 12.

The present invention also includes a first conductivity type injection layer 10 disposed in the second conductivity type injection layer 9 and at the edge of the second conductivity type injection layer 9 .

The stop region 5 includes: a second trench 8 , a contact hole 13 , a second oxide layer 6 and a second metal layer 15 . The second trench 8 is disposed in the epitaxial layer 2 of the first conductivity type, and a first oxide layer 11 is deposited on the trench wall and bottom of the second trench 8, and the second trench A polysilicon layer 12 is deposited in the trench, and the polysilicon layer 12 fills up the second trench. Impurities of the second conductivity type are injected into the contact hole 13, which are arranged inside the second trench 8 and the second conductivity type injection layer 9, and the contact hole 13 arranged in the second conductivity type injection layer 9 is in contact with the first conductivity type. Type injection layer 10 contacts. The second oxide layer 6 is disposed outside the first oxide layer 11 and the second trench 8 . The second metal layer 15 is disposed outside the second oxide layer 6 , and the second metal layer 6 is connected to the contact hole 13 .

In the present invention, the width of the first trench is greater than the width of the second trench, and the width of the first trench is greater than or equal to 2um.

The present invention also discloses a trench type semiconductor power device, which includes the above-mentioned trench MOSFET terminal structure and also includes a drain electrode, a source electrode and a gate electrode, and the drain electrode is arranged on the first conductive Type the other side of the substrate. The source electrode is connected to the source region and the channel region in the epitaxial wafer layer of the first conductivity type through the contact hole; the gate electrode is connected to the polysilicon in the second trench of the source region through the contact hole; the terminal structure includes a first voltage dividing region , a second partial pressure area and a cut-off area.

The invention discloses a method for preparing a trench MOSFET semiconductor power device, which comprises the following steps:

growing an epitaxial layer of the first conductivity type doped with the same type on the substrate layer of the first conductivity type;

performing trench etching on the epitaxial wafer layer of the first conductivity type to form a first trench and a second trench;

growing a first oxide layer as gate oxide in the first trench and the second trench;

Depositing polysilicon, filling the second trench completely, and depositing polysilicon on the walls of the first trench;

Impurity ions of the second conductivity type are implanted into the first conductivity type epitaxial wafer layer and the first groove, and the second conductivity type implantation layer is formed by heat treatment, and the second conductivity type injection layer is arranged on the first conductivity type epitaxial layer. the upper surface and the underside of the first trench;

Photoetching an implantation region of the first conductivity type impurity on the surface of the first conductivity type epitaxial layer, implanting the first conductivity type impurity ions, and forming the first conductivity type implantation layer by heat treatment;

depositing a second oxide layer to form a dielectric layer;

Contact hole photolithography and etching, the contact hole is in contact with the source region and the channel region;

Depositing a third metal layer, and performing photolithography to form source, gate and stop regions;

Prepare the drain electrode.

As shown in Figures 2 to 13, it is a schematic diagram of an embodiment of a method for preparing a trench MOSFET semiconductor power device of the present invention, including the following steps:

As shown in FIG. 2 , on the substrate layer 1 of the first conductivity type, an epitaxial wafer layer 2 of the first conductivity type doped with the same type is grown; on the substrate layer of the first conductivity type, the epitaxial wafer layer of the first conductivity type doped with the same type is grown layer, the doping concentration and thickness of the epitaxial layer of the first conductivity type will directly affect the breakdown voltage of the MOSFET device.

As shown in Figure 3, a third oxide layer 16 is deposited on the surface of the epitaxial wafer layer of the first conductivity type; the third oxide layer is deposited on the surface of the epitaxial layer, and the third oxide layer is photolithographically formed The windows and the masking layer of the first trench and the second trench are etched to leave a window for trench etching, and the remaining third oxide layer is used as a masking layer for trench etching.

As shown in FIG. 4 , trench etching is performed on the epitaxial wafer layer of the first conductivity type to form a first trench and a second trench.

As shown in FIG. 5, the third oxide layer is removed.

As shown in FIG. 6 , a first oxide layer is grown in the first trench and the second trench as gate oxide.

As shown in FIG. 7 , polysilicon is deposited to completely fill the second trench, and polysilicon is deposited on the walls and bottom of the first trench.

As shown in Figure 8, the polysilicon etching is to etch away the polysilicon above the surface of the epitaxial layer and the bottom of the first trench. Since the thickness of the polysilicon on the sidewall of the first trench is relatively thick, polysilicon remains on the sidewall of the first trench. , the polysilicon filled in the second trench remains.

As shown in Figure 9, impurity ions of the second conductivity type are implanted in the epitaxial wafer layer of the first conductivity type and inside the first groove, and the implanted layer of the second conductivity type is formed by heat treatment, and the implanted layer of the second conductivity type is arranged on the first trench. The upper surface of the epitaxial layer of a conductivity type and the lower part of the first groove. The impurity of the second conductivity type is implanted on the surface of the epitaxial sheet layer of the first conductivity type, and is diffused under the thermal process, and the depth of the diffusion junction does not exceed the depth of the trench to form the channel region of the MOSFET.

As shown in Figure 10, the implantation region of the first conductivity type impurity is photoetched on the surface of the second conductivity type implantation layer, and the first conductivity type impurity ions are implanted, and the first conductivity type implantation layer is formed by heat treatment, and the MOSFET is formed at the same time source area.

As shown in FIG. 11, a second oxide layer is deposited to form a dielectric layer.

As shown in Figure 12, contact hole lithography and etching, the etching depth of the contact hole should exceed the junction depth of the source region, and be smaller than the junction depth of the channel region, so as to ensure that the contact hole can be in contact with the source region and the channel region; Carry out hole implantation afterward, inject the impurity of second conductivity type, make the metal in the contact hole form ohmic contact with the second conductivity type injection layer; The conductive type injection layer is in contact with the first conductive type injection layer, and excess metal is removed through a chemical mechanical polishing process.

As shown in Figure 13, the third metal layer is deposited, and photolithography is carried out, and the remaining third metal layer is used as the electrodes of the source and the gate, and the cut-off area at the edge of the device; the source is connected to the first through the contact hole. The second conductivity type injection layer in the conductivity type epitaxial layer is connected to the first conductivity type injection layer, and the gate is connected to the polysilicon in the second trench through the contact hole; the floating metal ring on the edge of the device is connected to the outermost ring through the contact hole The second trench and the outermost injection layer of the second conductivity type are connected to the injection layer of the first conductivity type to form a cut-off region, and the cut-off region of the present invention is an annular cut-off region.

Finally, a passivation layer 14 is deposited to form a protective layer on the surface of the device to improve the reliability of the device, and the PAD hole is etched in the area where packaging and wiring are required to remove the passivation layer.

Prepare the drain region electrode, thin the back of the substrate of the first conductivity type, and deposit a fourth metal layer to form the drain region electrode. The fourth metal layer can be a Ti+Ni+Ag layer or other metal layers that can be used for packaging.

The terminal structure of the present invention includes a first voltage dividing region formed by several first trenches, a second voltage dividing region formed by several second trenches, a second trench, an injection layer of the first conductivity type, and A cut-off region formed by connecting the injection layers of the second conductivity type through the metal layer.

The first voltage dividing region contains several first trenches. Since the first trenches are not completely filled with polysilicon, when the implantation layer of the second conductivity type is implanted, impurities of the second conductivity type can be implanted under the trenches to form the first trenches. The second conductivity type injection layer forms the second conductivity type injection region under the trench. When the drain is at a high potential, the second conductivity type injection layer can be completely depleted and the depletion layer will be extended to the depth of the epitaxial layer. To ensure The depletion of the second conductivity type region can ensure the optimization of electric field distribution by optimizing the width of each first trench.

The second voltage division region contains several second trenches. Since most of the electric field in the terminal ring is distributed at the bottom of the first trench near the source region, the electric field in the second voltage division region has been significantly reduced. The bottom of a trench is implanted with impurities of the second conductivity type, which will no longer completely deplete the implanted region of the second conductivity type. Therefore, the efficiency of using the first trench decreases rapidly, which wastes the chip area; using the second trench The groove can obtain an effect close to that of the original first groove, but save a lot of area. Through calculation, in a chip with a withstand voltage above 100V, the structure of the present invention can save 2% to 5% of the chip area compared with the original structure.

The cut-off area is a conventional cut-off ring design, which is composed of a second groove connected to a second conductivity type injection layer and a first conductivity type injection layer on the edge of the chip through a contact hole and a second metal layer, so that the second groove and the second metal layer are connected to each other. The injection layer of the second conductivity type and the injection layer of the first conductivity type form an equipotential ring, which can effectively prevent mobile charges on the edge of the chip from entering the interior of the chip under the action of an electric field, and improve the reliability of the device.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (8)

1. A trench MOSFET termination structure, characterized in that, comprising: a first conductivity type substrate; A first conductivity type epitaxial layer, which is arranged on one side of the first conductivity type substrate; A plurality of first voltage dividing regions, which include a plurality of first trenches, a first oxide layer is deposited on the trench walls and bottom of the first trenches, and a polysilicon layer is provided inside the first trenches, and the polysilicon layer is deposited on the groove wall of the first trench, and a second conductivity type injection layer is provided in the first conductivity type epitaxial wafer on both sides and below the first trench; A plurality of second voltage-dividing regions, including a plurality of second trenches, a first oxide layer is deposited on the trench walls and bottom of the second trenches, and a polysilicon layer is deposited in the second trenches . 2. The trench MOSFET termination structure according to claim 1, further comprising a cut-off region comprising: A second groove, which is arranged in the epitaxial layer of the first conductivity type, and a first oxide layer is deposited on the groove wall and groove bottom of the second groove, and in the second groove Depositing a polysilicon layer; A first conductivity type injection layer, which is disposed in the second conductivity type injection layer and at the edge of the second conductivity type injection layer; A contact hole, and impurity of the second conductivity type is injected into the contact hole, which is arranged inside the second trench and the second conductivity type injection layer, and the contact hole arranged in the second conductivity type injection layer is connected with the first conductivity type injection layer contact; a second oxide layer, which is provided on the outside of the first oxide layer and the first trench; A second metal layer is arranged on the outside of the second oxide layer, and the second metal layer is connected with the contact hole. 3. The trench MOSFET terminal structure according to claim 1 or 2, wherein the width of the first trench is greater than the width of the second trench. 4. A trench MOSFET device containing the trench MOSFET terminal structure according to any one of claims 1 to 3, further comprising a drain region electrode disposed on the base of the first conductivity type the other side of the sheet. 5. Trench MOSFET device according to claim 4, is characterized in that, also comprises: A source electrode, which is connected to the source region and the channel region in the epitaxial wafer layer of the first conductivity type through a contact hole; A gate electrode is connected with the polysilicon in the second trench in the source region through the contact hole. 6. A method for preparing a trench MOSFET device, comprising the following steps: growing an epitaxial layer of the first conductivity type doped with the same type on the substrate layer of the first conductivity type; performing trench etching on the epitaxial wafer layer of the first conductivity type to form a first trench and a second trench; growing a first oxide layer as gate oxide in the first trench and the second trench; Depositing polysilicon, filling the second trench completely, and depositing polysilicon on the walls of the first trench; Impurity ions of the second conductivity type are implanted into the first conductivity type epitaxial wafer layer and the first groove, and the second conductivity type implantation layer is formed by heat treatment, and the second conductivity type injection layer is arranged on the first conductivity type epitaxial layer. the upper surface and the underside of the first trench; Photoetching an implantation region of the first conductivity type impurity on the surface of the first conductivity type epitaxial layer, implanting the first conductivity type impurity ions, and forming the first conductivity type implantation layer by heat treatment; depositing a second oxide layer to form a dielectric layer; Contact hole lithography and etching, the contact hole is in contact with the source region and the channel region, Depositing a third metal layer, and performing photolithography to form source, gate and stop regions; Prepare the drain electrode. 7. The preparation method of trench MOSFET device according to claim 6, is characterized in that, also comprises: Depositing a third oxide layer on the surface of the epitaxial wafer layer of the first conductivity type; Photolithography is performed on the third oxide layer to form a window and a masking layer for etching the first trench and the second trench. 8. The method for manufacturing a trench MOSFET device according to claim 7, further comprising: removing the third oxide layer.