CN104698747B - A kind of process improving X-Y scheme resolution - Google Patents
A kind of process improving X-Y scheme resolution Download PDFInfo
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- CN104698747B CN104698747B CN201510144159.5A CN201510144159A CN104698747B CN 104698747 B CN104698747 B CN 104698747B CN 201510144159 A CN201510144159 A CN 201510144159A CN 104698747 B CN104698747 B CN 104698747B
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Abstract
The present invention relates to semiconductor process technique fields, the present invention provides a kind of processes for improving X-Y scheme resolution, by the way of re-expose, for being easy to produce the region of fillet and shortening in final design figure, when exposing first time, first figure of the first mask plate is pre-processed into the certain distance that extends outwardly, when exposing for second, it is coated with upper second photoresist layer, second mask is used for the regional occlusion extended in advance, it is etched through overexposure, keep finally formed figure consistent with design configuration, the phenomenon that avoiding figure from generating corner rounding and line end shortening, prevent aliasing, improve the resolution of X-Y scheme.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of technique sides for improving X-Y scheme resolution
Method.
Background technique
With being constantly progressive for semiconductor integrated circuit manufacturing process, the continuous reduction of line width, the area of semiconductor devices
Just becoming smaller and smaller.Semiconductor integrated circuit is ultra-large integrated also from initial integrated circuit to large scale integrated circuit
Circuit, until today very large scale integrated circuit, function more fully, it is powerful.Complexity, length in view of technique research and development
How the restriction of phase property and high cost etc. unfavorable factor further increases the integrated of device on the basis of existing technology
Density, the area for reducing chip obtain Effective number of chips with as much as possible on same piece of silicon wafer, to improve whole effect
Benefit, increasingly by chip designer, the attention of manufacturer.
In semiconductor integrated circuit manufacturing process, photoetching technique is undoubtedly a ring of wherein most critical.Carrying out ion
It before injection or etching, needs to form photoetching agent pattern by photoetching process, with pre-defined to be etched or ion implanting out
Region.Thus, entire chip technology attainable minimum dimension be to be determined by photoetching process.
Photoetching process (photolithography) is an important step in process for fabrication of semiconductor device, the step
Geometric figure structure is portrayed on photoresist layer using exposure and imaging, is then turned the figure on photomask by etching technics
It moves on on substrate.
Photoetching process substantially treatment process are as follows: specific graphic structure (such as electrical circuit) is obtained on mask first,
It then will be on the graph copying to silicon wafer on mask by optical lithography equipment.However, generating figure by optical lithography
Process can generate more or less distortion, and especially with the continuous diminution of line width, distortion is also further serious.Typically, it such as turns
Angle is rounded phenomena such as (Corner Rounding) or line end shortening (Line End Shortening).Please refer to Fig. 1 and figure
2, Fig. 1 be the figure being pre-designed, and Fig. 2 is the figure being actually formed, and comparison diagram 1 and Fig. 2 can be, it is evident that be actually formed
Figure compared with the figure being pre-designed, produce corner rounding and the problem of line end shortens.Lead to the original of these above-mentioned phenomenons
Because being due to optical proximity effect (Optical Proximity Effect, abbreviation OPE), optical proximity effect OPE is by light
Caused by the nonlinear filtering for learning imaging system.
In conclusion those skilled in the art avoid it is urgent to provide a kind of process for improving X-Y scheme resolution
Figure generates the phenomenon that corner rounding and line end shortening, prevents aliasing, improves the resolution of X-Y scheme.
Summary of the invention
It is an object of the present invention to provide a kind of processes for improving X-Y scheme resolution, and figure is avoided to generate corner rounding
And the phenomenon that line end shortening, aliasing is prevented, the resolution of X-Y scheme is improved.
To achieve the goals above, the present invention provides a kind of processes for improving X-Y scheme resolution, including with
Lower step:
Step S1, semi-conductor silicon chip is provided, the semiconductor silicon on piece is coated with the first photoresist layer；Wherein, the silicon
Piece successively includes substrate, layer to be etched and hard mask layer from the bottom up；
Step S2, development is exposed to first photoresist layer using the first mask plate with the first figure, and
By the first pattern transfer on the first mask plate into first photoresist layer；Wherein, first figure has to be greater than and set
Count the predeterminable area of figure；
Step S3, the hard mask layer is performed etching using first photoresist layer as exposure mask, makes first figure
It is transferred in the hard mask layer；
Step S4, first photoresist layer is removed, and is coated with the second photoresist layer on the surface of the hard mask layer；
Step S5, development is exposed to second photoresist using the second mask with second graph, it is described
The second graph of second mask covers the predeterminable area, by the binding transfer of the first figure and second graph to described second
In photoresist layer, layer to be etched performed etching to described；
Step S6, second photoresist layer and hard mask layer are removed, there is design configuration on the silicon wafer.
Preferably, in the step S2, the summation of the design configuration and predeterminable area is first figure.
Preferably, the predeterminable area is 10~50nm of linear extension on the basis of design configuration.
Preferably, in the step S5, the second graph covers the predeterminable area, and hanging down to the predeterminable area
Histogram to two sides extend pre-determined distance.
Preferably, the pre-determined distance is 100~500nm.
Preferably, the second graph extends 100~500nm to the straight line extending direction of the predeterminable area.
Preferably, the design configuration and the first figure are flagpole pattern.
Preferably, positive photoresist is respectively adopted in first photoresist layer and second photoresist layer.
It is right by the way of re-expose the present invention provides a kind of process for improving X-Y scheme resolution
The region of fillet and shortening is easy to produce in final design figure, when exposing first time, by the first of the first mask plate
Figure is pre-processed into the certain distance that extends outwardly, and when exposing for second, painting is covered with the second photoresist layer, by the second mask
For being etched through overexposure to the regional occlusion extended in advance, keeps finally formed figure consistent with design configuration, avoid figure
The phenomenon that generating corner rounding and line end shortening, prevents aliasing, improves the resolution of X-Y scheme.
Detailed description of the invention
The figure that Fig. 1 is pre-designed for photoetching process in the prior art；
The figure that Fig. 2 is actually formed for photoetching process in the prior art；
Fig. 3 is the flow diagram for the process that the present invention improves X-Y scheme resolution；
Fig. 4 is the structural schematic diagram of the first figure of the first mask in the present invention；
Fig. 5 is the structural schematic diagram of the second graph of the second mask in the present invention；
Fig. 6 to Figure 10 is that the present invention improves design drawing formed in the process preferred embodiment of X-Y scheme resolution
The schematic diagram of the section structure of shape.
Appended drawing reference in figure are as follows:
10. design configuration, 20. actual graphicals, 30. predeterminable areas, 40. second photoresist layers, 50. substrates, 60. is to be etched
Layer, 70. hard mask layers, 80. first photoresist layers, 90. first figures, 100. second graphs.
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.Secondly, the present invention has carried out detailed statement using schematic diagram, it is real the present invention is described in detail
When example, for ease of description, schematic diagram is not partially enlarged in proportion to the general scale, should not be in this, as limitation of the invention.
Above and other technical characteristic and beneficial effect, by conjunction with the embodiments and attached drawing 1 to Figure 10 to raising of the invention
The process of X-Y scheme resolution is described in detail.The figure that Fig. 1 is pre-designed for photoetching process in the prior art；
The figure that Fig. 2 is actually formed for photoetching process in the prior art；Fig. 3 is the technique side that the present invention improves X-Y scheme resolution
The flow diagram of method；Fig. 4 is the structural schematic diagram of the first figure of the first mask in the present invention；Fig. 5 is the in the present invention
The structural schematic diagram of the second graph of two masks；Fig. 6 to Figure 10 is the process that the present invention improves X-Y scheme resolution
The schematic diagram of the section structure of design configuration formed in preferred embodiment.
Referring to Fig. 3, Fig. 3 is the flow diagram for improving the process of X-Y scheme resolution in the present invention；In this reality
It applies in example, the present invention provides a kind of process for improving X-Y scheme resolution, comprising the following steps:
Step S1, semi-conductor silicon chip is provided, semiconductor silicon on piece is coated with the first photoresist layer 80；Wherein, silicon wafer is under
It up successively include substrate 50, layer to be etched 60 and hard mask layer 70.(as shown in Figure 6)
Specifically, in the present embodiment, the first photoresist layer 80 can be used positive photoresist, the substrate 50, layer to be etched 60 and
The material of hard mask layer 70 can be depending on conventional selection.
Step S2, first photoresist layer 80 is exposed using the first mask plate with the first figure 90 aobvious
Shadow, and the first figure 90 on the first mask plate is transferred in the first photoresist layer 80；Wherein, first figure 90 has
Greater than the predeterminable area 30 of design configuration 10.(as shown in Fig. 4,6)
In the present embodiment, design configuration 10 and the first figure 90 are preferably flagpole pattern, since actual graphical 20 is easy
There is the phenomenon that fillet and drop-head, therefore when designing the first figure 90, increases preset areas on the basis of design configuration 10
The summation of domain 30, i.e. design configuration 10 and predeterminable area 30 is the first figure 90.Preferably, predeterminable area 30 is in design configuration
10~50nm of linear extension on the basis of 10.
Step S3, it is that exposure mask performs etching hard mask layer 70 with the first photoresist layer 80, is transferred to the first figure 90
In hard mask layer 70.(as shown in Figure 7)
In the step, there is fillet and drop-head phenomenon in the figure formed in hard mask layer 70, which appears in it
In preceding corresponding predeterminable area 30.
Step S4, first photoresist layer 80 is removed, and is coated with the second photoresist layer 40 on the surface of hard mask layer 70.
(as shown in Figure 8)
In this step, positive photoresist is can be used in the second photoresist layer 40.
Step S5, development is exposed to the second photoresist layer 40 using the second mask with second graph 100, the
The second graph 100 of two masks covers predeterminable area 30, by the binding transfer of the first figure 90 and second graph 100 to second
In photoresist layer 40, performed etching to layer to be etched 60.(as shown in Figure 9)
As shown in figure 5, the second graph 100 of the second mask covers the predeterminable area 30 of the first figure 90, and can be to pre-
If the two sides of the vertical direction in region 30 and straight line extending direction extend pre-determined distance, pre-determined distance is preferably 100~
500nm。
The fillet for sheltering from hard mask layer 70 and drop-head region due to the second graph 100 of the second mask, with
The exposure mask that is combined into of first figure 90 and second graph 100 is performed etching to layer to be etched 60, will not be gone out on layer to be etched 60
The phenomenon that existing fillet or drop-head.
Step S6, the second photoresist layer 40 and hard mask layer 70 are removed, there is design configuration on silicon wafer.(such as Figure 10 institute
Show)
Finally the second photoresist layer 40 and hard mask layer 70 are removed, removal technique can depending on common process,
Finally the phenomenon that the design configuration formed on silicon wafer is not in fillet and drop-head, the figure and design configuration that are actually formed
Unanimously.
In conclusion using re-expose the present invention provides a kind of process for improving X-Y scheme resolution
Mode, for being easy to produce the region of fillet and shortening in final design figure, first time expose when, by the first exposure mask
First figure of version is pre-processed into the certain distance that extends outwardly, and when second exposes, painting is covered with the second photoresist layer, by the
Two masks are used to etch through overexposure to the regional occlusion extended in advance, keep finally formed figure consistent with design configuration,
The phenomenon that avoiding figure from generating corner rounding and line end shortening, prevents aliasing, improves the resolution of X-Y scheme.
Described above is only the description of the preferred embodiment of invention, it is noted that due to the finiteness of literal expression, and
Objectively there is unlimited specific structure, for those skilled in the art, is not departing from original of the invention
Under the premise of reason, several improvements and modifications can also be made, these modifications and embellishments should also be considered as the scope of protection of the present invention.Appoint
What simple modification, equivalent variation and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (6)
1. a kind of process for improving X-Y scheme resolution, which comprises the following steps:
Step S1, semi-conductor silicon chip is provided, the semiconductor silicon on piece is coated with the first photoresist layer；Wherein, the silicon wafer from
Under up successively include substrate, layer to be etched and hard mask layer；
Step S2, development is exposed to first photoresist layer using the first mask plate with the first figure, and by the
The first pattern transfer on one mask plate is into first photoresist layer；Wherein, first figure, which has, is greater than design drawing
The predeterminable area of shape；
Step S3, the hard mask layer is performed etching using first photoresist layer as exposure mask, makes first pattern transfer
To in the hard mask layer；
Step S4, first photoresist layer is removed, and is coated with the second photoresist layer on the surface of the hard mask layer；
Step S5, development is exposed to second photoresist using the second mask with second graph, described second
The second graph of mask covers the predeterminable area, and to the two sides of the vertical direction of the predeterminable area extend it is default away from
From；By the binding transfer of the first figure and second graph into second photoresist layer, layer to be etched performed etching to described；
Step S6, second photoresist layer and hard mask layer are removed, there is design configuration on the silicon wafer, wherein described
Design configuration, the first figure and second graph are flagpole pattern.
2. the process according to claim 1 for improving X-Y scheme resolution, which is characterized in that the step S2
In, the summation of the design configuration and predeterminable area is first figure.
3. the process according to claim 2 for improving X-Y scheme resolution, which is characterized in that the predeterminable area
It is 10~50nm of linear extension on the basis of design configuration.
4. the process according to claim 1 for improving X-Y scheme resolution, which is characterized in that the pre-determined distance
For 100~500nm.
5. the process according to claim 1 for improving X-Y scheme resolution, which is characterized in that the second graph
Extend 100~500nm to the straight line extending direction of the predeterminable area.
6. the process of any raising X-Y scheme resolution according to claim 1~5, which is characterized in that described
Positive photoresist is respectively adopted in first photoresist layer and second photoresist layer.
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| CN201510144159.5A CN104698747B (en) | 2015-03-30 | 2015-03-30 | A kind of process improving X-Y scheme resolution |
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| CN104977803B (en) * | 2015-07-22 | 2019-06-28 | 上海华力微电子有限公司 | A method of being formed simultaneously a peacekeeping two dimension photoetching offset plate figure |
| CN105161409B (en) * | 2015-09-27 | 2018-08-14 | 上海华力微电子有限公司 | The forming method of U-shaped grid |
| CN106328499B (en) * | 2016-08-25 | 2018-11-20 | 西安派瑞功率半导体变流技术股份有限公司 | Mask plate high-precision blocks semiconductor chip gate pole figure Vacuum Deposition processing film technique |
| CN109917616B (en) * | 2017-12-12 | 2022-07-05 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of mask for double patterning and double patterning method |
| CN110277372B (en) * | 2019-07-23 | 2024-05-31 | 南方电网科学研究院有限责任公司 | Integrated circuit photo-etching structure, preparation method and integrated circuit |
| CN113078057B (en) * | 2021-03-23 | 2022-09-23 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| US11710642B2 (en) | 2021-03-23 | 2023-07-25 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| US6566019B2 (en) * | 2001-04-03 | 2003-05-20 | Numerical Technologies, Inc. | Using double exposure effects during phase shifting to control line end shortening |
| US6787469B2 (en) * | 2001-12-28 | 2004-09-07 | Texas Instruments Incorporated | Double pattern and etch of poly with hard mask |
| CN103426810B (en) * | 2012-05-15 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Double-patterning method in back-end process |
| CN102915960B (en) * | 2012-10-19 | 2016-05-11 | 上海华虹宏力半导体制造有限公司 | The preparation method of metal interconnect structure |
| CN104020638B (en) * | 2014-06-19 | 2017-07-11 | 上海华力微电子有限公司 | The forming method of mask plate figure and photoetching and lithographic method |
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