CN104636290B - Fpga chip configuration structure and collocation method based on multi-configuration chain group - Google Patents
Fpga chip configuration structure and collocation method based on multi-configuration chain group Download PDFInfo
- Publication number
- CN104636290B CN104636290B CN201310545411.4A CN201310545411A CN104636290B CN 104636290 B CN104636290 B CN 104636290B CN 201310545411 A CN201310545411 A CN 201310545411A CN 104636290 B CN104636290 B CN 104636290B
- Authority
- CN
- China
- Prior art keywords
- configuration
- chain group
- group
- bit stream
- configuration chain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Logic Circuits (AREA)
- Stored Programmes (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of fpga chip configuration structure and collocation method based on multi-configuration chain group, the structure includes：Master controller receives and parses through multigroup bit stream file of external series transmission, generates serial multigroup bit stream configuration information；Wherein each group of bit stream configuration information is realizing a kind of application；Multiplexer receives configuration chain group selection signal, will be sent according to current configuration chain group selection signal when previous group bit stream configuration information；Multiple configuration chain groups, each chain group that configures include multiple configuration chain groups；In the multiple configuration chain group, the collection of each configuration chain group for configuring application identical in chain group is combined into one group of configuration chain group of the application；Each group of configuration chain group receives and stores corresponding one group of bit stream configuration information；Multiple demultiplexer receive and configuration of the bit stream configuration information startup to fpga chip are obtained from corresponding one group of configuration chain group according to configuration chain group selection signal respectively.
Description
Technical field
The present invention relates to field programmable gate arrays（Field Programmable Gate Array,FPGA）'s
The fpga chip configuration structure based on multi-configuration chain group and match somebody with somebody that chip configuration structure more particularly to can realize quickly reconfigures
Put method.
Background technology
FPGA is a kind of logic device with abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability
Part.These features cause FPGA to obtain more and more extensive uses in many fields such as data processing, communication, network.Especially
It is its Reconfigurability, and user can make it perform different functions by downloading different configuration files.Therefore, FPGA
It is often used in needing according to circumstances to change the embedded system of function, such as software radio (Software Defined
Radio, SDR) system, distance sensor (Remote Sensors, RS) system etc..But for the insertion of performance requirement harshness
Formula system, such as real-time embedded system, it is necessary to which system response meets stringent temporal constraint.These temporal constraints be typically with
Millisecond and microsecond calculate for unit.The configuration structure of traditional FPGA is as shown in Figure 1, its configuration and the flow diagram reconfigured
As shown in Figure 2.FPGA arrives correct perform function after the power-up to be needed to undergo three main process：Upper electro-detection and initialization, just
Under beginning bit stream file, start configuration process（startup）.It is after all configuration chains receive parsing wherein to start configuration process
Content and the process for completing all the elements configuration.When FPGA user mode need perform reconfigure handoff functionality when, Yong Huxu
It downloads complete bit stream file and performs and start configuration process.FPGA is constantly in the shape of break-off during this
State terminates until starting configuration process, and FPGA starts to perform new function.Reconfiguring for traditional FPGA is for entire device
, therefore the bit stream file downloaded during reconfiguring is as initialization bit stream file size, is complete bit
Stream file.With constantly increasing for user demand, the hardware resource that FPGA is included constantly is increasing, corresponding bit stream
The size of file is also increasing, and results in FPGA and reconfigures the required time and is also increasing.Therefore, using conventional arrangement mode into
The FPGA that row reconfigures has been increasingly difficult to the timing requirements for meeting Real-time System.FPGA reconfiguration times are long to have become FPGA
How one restraining factors of application accelerate the hot spot that the process that FPGA is reconfigured is always FPGA researchs.
The required time is reconfigured in order to strengthen the reconfigurable ability of FPGA, reduce FPGA.FPGA manufacturers Xilinx
Proposed the concept of partial reconfiguration (Partial Reconfiguration, PR) at 2004 and 2011 respectively with Altera.
The configuration of PR technologies and Reconfiguration Procedure figure are as shown in Figure 3.It is compared with traditional FPGA configurations, PR technologies arrive after the power-up performs use
The process of family pattern is the same, it is necessary to undergo three main process.The advantage of PR technologies maximum is during reconfiguring, it is only necessary to
Want download part bit stream file（Partial Bitstream）The dynamic area of configuration FPGA is gone to, FPGA is made dynamically to change
Function.The dynamic area of FPGA needs to change the region of function, be that user can define according to design, can be one
Block region can also make polylith region.It is compared with the bit stream file for configuring entire FPGA, partial bit stream file is only containing dynamic
The configuration data in state region, and dynamic area is generally only a part of region in FPGA, so partial bit stream file ratio
Traditional full bit stream file is much smaller, and it is also few many to download the required time.On the other hand, when PR technologies are not related to the overall situation
The configuration of the resources such as clock and input/output I/O, so when partial bit stream file downloads completion, it only need to be to local deposit
Device, look-up table etc. carry out startup configuration, you can perform user mode.So in configuration process is started, PR technologies are also than tradition
FPGA reconfigures fast.But existing PR technologies are only applicable to multiple and different application scenarios with public function, only pass through
Change the switching at runtime that local function makes FPGA realize multiple and different applications.Therefore PR, which reconfigures ability, certain limitation, and
FPGA cannot be made thoroughly to change institute functional.
The content of the invention
The defects of the purpose of the present invention is being directed to the prior art, provides a kind of fpga chip based on multi-configuration chain group and matches somebody with somebody
Structure and collocation method are put, by adding in multigroup configuration chain group, each chain group that configures includes multiple configuration chain groups to deposit
The bit stream configuration information of a function of different application is stored up, so as to which in FPGA configurations or reconfiguration course, phase only need to be selected
The configuration chain group of same application, which reads bit stream configuration information, in the multiple configuration chain groups answered completes to start configuration.
In a first aspect, an embodiment of the present invention provides a kind of fpga chip configuration structure based on multi-configuration chain group, bags
It includes：
Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is carried out successively
Parsing, generates serial multigroup bit stream configuration information；Wherein, each group of bit stream configuration information is realizing a kind of application；
Multiplexer receives configuration chain group selection signal, will work as previous group according to current configuration chain group selection signal
Bit stream configuration information is sent；
Multiple configuration chain groups, each chain group that configures include multiple configuration chain groups；In the multiple configuration chain group, Mei Gepei
The collection for putting a configuration chain group of application identical in chain group is combined into one group of configuration chain group of the application；Each group of configuration
Chain group receives and stores corresponding one group of bit stream that the multiplexer is sent according to the configuration chain group selection signal
Configuration information；
Multigroup demultiplexer receives the configuration chain group selection signal respectively, and according to the configuration chain group selection
Signal obtains configuration of the bit stream configuration information startup to fpga chip from corresponding one group of configuration chain group.
Preferably, the structure further includes configuration chain group selection signal input port, the configuration chain group selection that outside is sent
Signal is sent to the multiplexer or demultiplexer by the configuration chain group selection signal input port.
Preferably, each group of bit stream configuration information includes multiple functional configuration information, and each configuration chain is small
Group receives and stores the multiplexer and is believed according to the corresponding functional configuration that the configuration chain group selection signal is sent
Breath.
Preferably, the number of the demultiplexer and the number of the configuration chain group match.
Preferably, each demultiplexer selects accordingly according to configuration chain group selection signal from matched configuration chain group
Configuration chain group obtain the configuration that bit stream configuration information starts fpga chip.
Preferably, after the completion of serial multigroup bit stream configuration information stores in multiple configuration chain groups, fpga chip
Into working condition；It is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group choosing
When selecting signal and bit stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to configuration
Chain group selection signal is sent to corresponding configuration chain group and is stored, and covers the ratio formerly stored in the configuration chain group
Special stream configuration information.
In second aspect, an embodiment of the present invention provides a kind of matching somebody with somebody for fpga chip configuration structure based on multi-configuration chain group
Method is put, including：
Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is solved successively
Analysis, generates serial multigroup bit stream configuration information；Wherein, each group of bit stream configuration information is realizing a kind of application；
Multiplexer receives configuration chain group selection signal, will work as previous group ratio according to current configuration chain group selection signal
Special stream configuration information is sent；
Each group of configuration chain group receives and stores the multiplexer and is sent according to the configuration chain group selection signal
Corresponding one group of bit stream configuration information；Wherein described one group of configuration chain group is：In multiple configuration chain groups, chain is each configured
The set of a configuration chain group of identical application in group；
Demultiplexer receives the configuration chain group selection signal, and according to the configuration chain group selection signal from corresponding
One group of configuration chain group in obtain the configuration that bit stream configuration information starts fpga chip.
Preferably, it is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group
When selection signal and bit stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to matching somebody with somebody
It puts chain group selection signal and is sent to corresponding configuration chain group and stored, and cover what is formerly stored in the configuration chain group
Bit stream configuration information.
Fpga chip configuration structure and collocation method provided in an embodiment of the present invention based on multi-configuration chain group, pass through addition
Multigroup configuration chain group includes multiple configuration chain groups to store the ratio of different application function in each configuration chain group
Special stream configuration information, so as to fulfill can store to realize in each group of configuration chain group function for a variety of differences
The bit stream configuration information of application, so as in FPGA configurations or reconfiguration course, need to only select corresponding multiple configuration chain groups
The configuration chain group of middle same application, which reads bit stream configuration information, to complete to start configuration so that FPGA is being reconfigured
New bit stream file is downloaded without waiting for external, it becomes possible to realize bit stream configuration information parallel from multiple configurations in the process
It is read in chain group and starts configuration, having given full play to FPGA has the advantage of parallel deployment design feature of multiple configuration chains, pole
The earth accelerates the speed reconfigured, improves allocative efficiency.
Description of the drawings
Fig. 1 is the configuration structure schematic diagram for traditional FPGA that the prior art provides；
Fig. 2 is the configuration for traditional FPGA that the prior art provides and the flow diagram reconfigured;
Fig. 3 is the configurations of the FPGA based on PR technologies and the flow diagram reconfigured that the prior art provides;
Fig. 4 is the fpga chip configuration structure schematic diagram provided in an embodiment of the present invention based on multi-configuration chain group；
Fig. 5 is the configuration of FPGA provided in an embodiment of the present invention and the flow diagram reconfigured；
Fig. 6 is the configuration of FPGA provided in an embodiment of the present invention and the flow chart reconfigured.
Specific embodiment
Below by drawings and examples, technical scheme is described in further detail.
Fig. 4 is the fpga chip configuration structure schematic diagram provided in an embodiment of the present invention based on application memory.The core
Piece configuration structure includes：Master controller 1, multiplexer 2, multiple configuration chain groups（In figure with configure chain group 31, configuration chain group
32nd, chain group 33 and configuration chain group 34 are configured to exemplify）With multiple demultiplexer（With demultiplexer 41, more in figure
Road demultiplexer 42, demultiplexer 43 and demultiplexer 44 are to exemplify）.
Master controller 1 receives multigroup bit stream file that external series are sent, and the bit stream file is carried out successively
Parsing, generates serial multigroup bit stream configuration information；Wherein, each group of bit stream configuration information is realizing a kind of FPGA's
Using；
Preferably, between every two groups of adjacent bit stream files are inputted between meeting at regular intervals.
Multiplexer 2 receives configuration chain group selection signal, will work as previous group according to current configuration chain group selection signal
Bit stream configuration information is sent；
Multiple configuration chain groups, each chain group that configures include multiple configuration chain groups；In the multiple configuration chain group, Mei Gepei
The collection for putting a configuration chain group of application identical in chain group is combined into one group of configuration chain group of the application；Each group of configuration
Chain group receives and stores corresponding one group of bit stream that the multiplexer is sent according to the configuration chain group selection signal
Configuration information；
In the present embodiment, shown in Fig. 4 and specifically include configuration chain group 31, configuration chain group 32, configuration chain group 33 and match somebody with somebody
The situation of chain group 34 is put, each chain group that configures corresponds to a FPGA function, such as global clock（GCLK）, memory（Reg.）, look into
Look for table (LUT), input/output (I/O) etc..Exemplified by configuring chain group 31, that it is stored is the GCLK in bit stream configuration information
Information configures for the global clock to fpga chip.Include 4 configuration chain groups in chain group 31 is configured, respectively
Chain group 1, GCLK configuration chains group 2, GCLK configuration chains group 3 and GCLK configuration chains group 4 are configured for GCLK.Match somebody with somebody at these
In Zhi Lian groups, what is stored respectively is one group of global clock information of corresponding different FPGA applications.Accordingly other several
It configures in chain group, also stores one group of Reg. information, one group of LUT information and the one group of I/ of corresponding different FPGA applications accordingly
O information.
The set of a configuration chain group of identical application becomes corresponding FPGA applications in different configuration chain groups
One group of configuration chain group；GCLK configuration chains group 1, Reg. configuration chains group 1, LUT configuration chains group 1 and I/O in such as figure
Configuration chain group 1 constitutes one group of configuration chain group.This configuration chain group receives and stores multiplexer 2 according to configuration chain
One group of bit stream configuration information that group selection signal is sent.The effect of the bit stream configuration information can be configured to answer by FPGA
With 1.
Further specifically, each configuration chain group includes multiple configuration chains.
Multiple demultiplexer receive the configuration chain group selection signal respectively, and according to the configuration chain group selection
Signal obtains configuration of the bit stream configuration information startup to fpga chip from corresponding one group of configuration chain group.
Preferably, the number of demultiplexer matches with configuring the number of chain group.
It is shown in Fig. 4 and specifically includes demultiplexer 41, demultiplexer 42, demultiplexer 43 and multichannel
The situation of demultiplexer 44.FPGA is configured to obtain when above-mentioned each demultiplexer receives configuration chain group selection signal
Using 1 bit stream configuration information when, demultiplexer 41 is obtained from configuration chain group 31 to be stored in GCLK configurations chain group 1
GCLK information.Correspondingly, demultiplexer 42 obtains the Reg. stored in Reg. configuration chains group 1 from configuration chain group 31
Information；Demultiplexer 43 obtains the LUT information stored in LUT configuration chains group 1 from configuration chain group 33；Demultiplexing
Device 44 obtains the I/O information stored in I/O configuration chains group 1 from configuration chain group 34.These information are used to match somebody with somebody FPGA startups
It puts, makes FPGA that can realize the function using 1 after configuration.
Further, chip configuration structure provided in this embodiment further includes configuration chain group selection signal input port 5, outside
The configuration chain group selection signal that portion is sent is sent to the multiplexer by the configuration chain group selection signal input port 5
Or demultiplexer.
Below to the course of work of the fpga chip configuration structure provided in an embodiment of the present invention based on multi-configuration chain group into
Row is described in detail.
The number of chain group is configured to determine with the quantity of the configurable functionality of FPGA, it is each to configure in chain group, configure chain group
The application library number that is supported by the system of number determine（This patent is by taking four functions, four applications as an example.It is specific real at other
It applies in example, the number for configuring chain group or configuration chain group can be less or more）.In the present embodiment, configured in fpga chip
Structure includes：Configure chain group selection signal input port 5.Configure the configuration chain group that chain group selection signal input port 5 receives
Selection signal APP_ADDR [1:0] selection of the control to configuration chain group in each configuration chain group.
After fpga chip is by upper electro-detection, for the first time download bit stream file after the parsing of master controller 1,
The configuration chain group selection signal APP_ADDR [1 received according to multiplexer 2:0] by all bit stream configuration informations such as
Global clock GCLK, register Reg., look-up table LUT, I/O etc. are stored entirely in " using 1 " in corresponding configuration chain group.Together
Reason, second and third, the bit stream configuration information of the download of four times be separately stored in " using 2 ", " using 3 ", corresponding " using 4 "
It configures in chain group.There are four different applications for the application library that FPGA is supported at this time.In FPGA configurations or reconfiguration course, only
The configuration chain group of respective application need to be selected, according to the configuration content of storage PFGA is made to quickly complete startup configuration within several cycles
Process performs corresponding user mode.It is maximum without waiting for the download of any new bit stream file in reconfiguration course
Limit improve FPGA reconfigure speed.
Using after multi-configuration chain group structure in fpga chip configuration structure, matching somebody with somebody in different configuration chain groups is stored in
Configuration FPGA can repeatedly be read out according to system requirements by putting content.
In addition, after the completion of serial multigroup bit stream configuration information storage, fpga chip enters working condition；In FPGA
When chip is in running order, configuration system is supported to download the application that new bit stream configuration information supports configuration chain group
Storehouse is updated.When the multiplexer is received again by configuration chain group selection signal, currently received one group of bit stream is matched somebody with somebody
Confidence breath can be written to compare according to user demand to be stored in rarely needed configuration chain group, and is covered originally in the configuration chain
Bit stream configuration information in group, make stored bits stream configuration information FPGA can quickly in most common application into
Row function switch.
Therefore, fpga chip configuration structure of the invention is supported when FPGA is worked normally, by the bit stream of different application
File is separately stored in corresponding configuration chain group simultaneously energy by download and parsing under the control of configuration chain group selection signal
It is updated.This renewable mechanism can add new application in chain group is configured at any time, enable the FPGA moment multiple normal
It is dynamically switched fast in application, so as to enhance the adaptive ability of system.
Fig. 5 is the configuration of FPGA provided in an embodiment of the present invention and the flow diagram reconfigured.By can see in figure,
Between the FPGA working times of different application twice, the selection, reading and the setup time that are spent greatly reduce, this be because
The time is obtained for the fpga chip configuration structure of the present invention bit stream configuration information required when starting configuration to FPGA, than passing
It needs just obtain bit stream configuration information from outside download bit stream file before reconfiguring in system FPGA configuration structures
Time substantially reduces.
Compared with traditional fpga chip reconfiguration course and using PR technologies fpga chip reconfiguration course, use
Fpga chip provided in an embodiment of the present invention mainly can greatly accelerate what is reconfigured during reconfiguring from following 2 points
Speed.
1st, using the configuration structure of fpga chip provided in an embodiment of the present invention, in reconfiguration course, without waiting for
The process of new bit stream file is downloaded in outside, only the configuration chain group of different application need to be selected to connect, according to configuration chain group memory
The configuration content of storage makes fpga chip quickly complete startup configuration feature within short several clock cycle.
2nd, usual FPGA downloads the mode of bit stream as serial download, such as joint test behavior tissue（Joint Test
Action Group, JTAG）It downloads, the bit stream file downloaded using which configures content after master controller parses
Different configuration chains can be sequentially entered and perform configuration, it is impossible to which multiple configuration chains perform startup configuration process simultaneously, therefore configure effect
Rate is not high.After configuration structure using fpga chip provided in an embodiment of the present invention, by the institute for selecting some application of activation
After having configuration chain group state, all configuration chain groups of the application can the entire fpga chip of parallel deployment simultaneously, maximum limit
Degree improves allocative efficiency.
Correspondingly, the embodiment of the present invention additionally provides a kind of method, to realize to provided in above-described embodiment based on
The fpga chip configuration structure of application memory is configured.As shown in fig. 6, it the described method comprises the following steps：
Step 610, master controller receive external series send multigroup bit stream file, and to the bit stream file according to
It is secondary to be parsed, generate serial multigroup bit stream configuration information；
Wherein, each group of bit stream configuration information is realizing a kind of application；
Step 620, multiplexer receives configuration chain group selection signal, ought according to current configuration chain group selection signal
Previous group bit stream configuration information is sent；
Step 630, each group of configuration chain group receives and stores the multiplexer according to the configuration chain group selection
Corresponding one group of bit stream configuration information that signal is sent；Wherein described one group of configuration chain group is：In multiple configuration chain groups, often
The set of a configuration chain group of identical application in a configuration chain group；
Step 640, demultiplexer receives the configuration chain group selection signal, and according to the configuration chain group selection letter
The configuration that bit stream configuration information starts fpga chip is obtained number from corresponding one group of configuration chain group.
In addition, after the completion of serial multigroup bit stream configuration information storage, fpga chip enters working condition；In FPGA
When chip is in running order, configuration system is supported to download the application that new bit stream configuration information supports configuration chain group
Storehouse is updated.When the multiplexer is received again by configuration chain group selection signal, currently received one group of bit stream is matched somebody with somebody
Confidence breath can be written to compare according to user demand to be stored in rarely needed configuration chain group, and is covered originally in the configuration chain
Bit stream configuration information in group, make stored bits stream configuration information FPGA can quickly in most common application into
Row function switch.
Collocation method provided in this embodiment, to realize to providing in above-described embodiment based on application memory
Fpga chip configuration structure is configured.Concrete configuration process has been described in detail in the above-described embodiments, and details are not described herein again.
Professional should further appreciate that, be described with reference to the embodiments described herein each exemplary
Unit and algorithm steps can be realized with the combination of electronic hardware, computer software or the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are performed actually with hardware or software mode, specific application and design constraint depending on technical solution.
Professional technician can realize described function to each specific application using distinct methods, but this realization
It is it is not considered that beyond the scope of this invention.
The step of method or algorithm for being described with reference to the embodiments described herein, can use hardware, processor to perform
The combination of software module or the two is implemented.Software module can be placed in random access memory（RAM）, memory, read-only memory
（ROM）, electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific embodiment has carried out the purpose of the present invention, technical solution and advantageous effect further
It is described in detail, it should be understood that the foregoing is merely the specific embodiments of the present invention, is not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (3)
1. a kind of fpga chip configuration structure based on multi-configuration chain group, which is characterized in that the structure includes：
Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is parsed successively,
The serial multigroup bit stream configuration information of generation；Wherein, each group of bit stream configuration information is realizing a kind of application；It is inputting
Between every two groups adjacent bit stream files between meeting at regular intervals；
Multiplexer receives configuration chain group selection signal, will work as previous group bit according to current configuration chain group selection signal
Stream configuration information is sent；
Multiple configuration chain groups, each chain group that configures include multiple configuration chain groups；In the multiple configuration chain group, chain is each configured
The collection of a configuration chain group of identical application is combined into one group of configuration chain group of the application in group；Each group of configuration chain is small
Group receives and stores corresponding one group of bit stream configuration that the multiplexer is sent according to the configuration chain group selection signal
Information；Each configuration chain group includes multiple configuration chains；
Multiple demultiplexer receive the configuration chain group selection signal respectively, and according to the configuration chain group selection signal
Configuration of the bit stream configuration information startup to fpga chip is obtained from corresponding one group of configuration chain group；
The each group of bit stream configuration information includes multiple functional configuration information, and each configuration chain group receives and stores
The corresponding functional configuration information that the multiplexer is sent according to the configuration chain group selection signal；
The number of the demultiplexer and the number of the configuration chain group match；
Each demultiplexer selects corresponding configuration chain small according to configuration chain group selection signal from matched configuration chain group
Group obtains the configuration that bit stream configuration information starts fpga chip；
After the completion of serial multigroup bit stream configuration information stores in multiple configuration chain groups, fpga chip enters work shape
State；It is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group selection signal and ratio
During special stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to configuration chain group selection letter
It number is sent to corresponding configuration chain group to be stored, and covers the bit stream configuration letter formerly stored in the configuration chain group
Breath.
2. chip configuration structure according to claim 1, which is characterized in that the structure further includes configuration chain group selection letter
Number input port, the configuration chain group selection signal that outside is sent are sent to institute by the configuration chain group selection signal input port
State multiplexer or demultiplexer.
3. a kind of collocation method of the fpga chip configuration structure based on multi-configuration chain group, which is characterized in that the described method includes：
Master controller receives multigroup bit stream file that external series are sent, and the bit stream file is parsed successively,
The serial multigroup bit stream configuration information of generation；Wherein, each group of bit stream configuration information is realizing a kind of application；It is inputting
Between every two groups adjacent bit stream files between meeting at regular intervals；
Multiplexer receives configuration chain group selection signal, will work as previous group bit stream according to current configuration chain group selection signal
Configuration information is sent；
Each group of configuration chain group receives and stores the phase that the multiplexer is sent according to the configuration chain group selection signal
The one group of bit stream configuration information answered；Wherein described one group of configuration chain group is：It is each to configure in chain group in multiple configuration chain groups
The set of one configuration chain group of identical application；Wherein, each configuration chain group includes multiple configuration chains；
Demultiplexer receives the configuration chain group selection signal, and according to the chain group selection signal that configures from corresponding one
The configuration that bit stream configuration information starts fpga chip is obtained in group configuration chain group；
The each group of bit stream configuration information includes multiple functional configuration information；
The number of the demultiplexer and the number of the configuration chain group match；
After the completion of serial multigroup bit stream configuration information stores in multiple configuration chain groups, fpga chip enters work shape
State；It is in running order in the fpga chip, and when the multiplexer is received again by configuration chain group selection signal and ratio
During special stream configuration information, the multiplexer is by be currently received one group of bit stream configuration information according to configuration chain group selection letter
It number is sent to corresponding configuration chain group to be stored, and covers the bit stream configuration letter formerly stored in the configuration chain group
Breath.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310545411.4A CN104636290B (en) | 2013-11-06 | 2013-11-06 | Fpga chip configuration structure and collocation method based on multi-configuration chain group |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310545411.4A CN104636290B (en) | 2013-11-06 | 2013-11-06 | Fpga chip configuration structure and collocation method based on multi-configuration chain group |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104636290A CN104636290A (en) | 2015-05-20 |
| CN104636290B true CN104636290B (en) | 2018-05-25 |
Family
ID=53215064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310545411.4A Active CN104636290B (en) | 2013-11-06 | 2013-11-06 | Fpga chip configuration structure and collocation method based on multi-configuration chain group |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104636290B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958995B (en) * | 2016-04-27 | 2019-04-02 | 北京时代民芯科技有限公司 | A kind of circuit and method of quick start FPGA |
| CN108228529B (en) * | 2017-09-28 | 2019-07-26 | 清华大学无锡应用技术研究院 | For configuring the method and its system of reconfigureable computing array |
| US10141026B1 (en) | 2017-10-11 | 2018-11-27 | International Business Machines Corporation | Access control for hardware resources |
| CN113608919B (en) * | 2021-08-19 | 2024-02-02 | 无锡中微亿芯有限公司 | FPGA for improving reliability of key configuration code stream through multiplexing buffer memory |
| US11604696B2 (en) * | 2021-08-19 | 2023-03-14 | Wuxi Esiontech Co., Ltd. | Field programmable gate array (FPGA) for improving reliability of key configuration bitstream by reusing buffer memory |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1234923A (en) * | 1996-08-21 | 1999-11-10 | 新拉姆有限责任公司 | Reconfigurable computing system |
-
2013
- 2013-11-06 CN CN201310545411.4A patent/CN104636290B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1234923A (en) * | 1996-08-21 | 1999-11-10 | 新拉姆有限责任公司 | Reconfigurable computing system |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的动态可重配置方法研究;邹晨 等;《航空计算技术》;20120530;第42卷(第3期);正文第125－129页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104636290A (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104636290B (en) | Fpga chip configuration structure and collocation method based on multi-configuration chain group | |
| US8415974B1 (en) | Methods and circuits enabling dynamic reconfiguration | |
| AU2017202110B2 (en) | Runtime creation, assignment, deployment and updating of arbitrary radio waveform techniques for a radio waveform generation device | |
| JP3729943B2 (en) | Time-multiplexable logic device | |
| CN100530594C (en) | Switch methodology for mask-programmable logic devices | |
| US7418579B2 (en) | Component with a dynamically reconfigurable architecture | |
| CN104636151B (en) | Fpga chip configuration structure and collocation method based on application memory | |
| US7268581B1 (en) | FPGA with time-multiplexed interconnect | |
| CN106202604B (en) | The method and apparatus for reconfiguring region for configuring and reconfiguring part | |
| CN110515891B (en) | FPGA chip and configuration method thereof | |
| JP2004523056A5 (en) | ||
| CN110506393B (en) | FPGA with virtual array of logic tiles and method of configuration and operation thereof | |
| CN102841873B (en) | For at the system and method without configuring SOPC in the case of using external memory storage | |
| CN107704285A (en) | Multi-version configuration chip, system and method for field programmable gate array | |
| US20070075736A1 (en) | FPGA powerup to known functional state | |
| CN104049995B (en) | The method and apparatus that FPGA is configured in MCU chip | |
| CN104536917B (en) | Multifunctional storage-based dynamic configuration circuit applied to FPAA | |
| KR101181957B1 (en) | Method and Apparatus for reconfigurating of software in SDR access terminal | |
| US7626420B1 (en) | Method, apparatus, and system for synchronously resetting logic circuits | |
| CN107632910B (en) | Test method and device | |
| JPH05282895A (en) | Integrated circuit including standard cell, application cell, and test cell | |
| EP2166454A1 (en) | System and method for testing application-specific blocks embedded in reconfigurable arrays | |
| CN115310391A (en) | FPGA configuration control system, FPGA configuration method and FPGA chip | |
| JP2004200311A (en) | Logic verifying device | |
| KR20220027235A (en) | Regularity of Fabrics in Programmable Logic Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |