Nothing Special   »   [go: up one dir, main page]

CN104538380A - 小间距PoP封装单体 - Google Patents

小间距PoP封装单体 Download PDF

Info

Publication number
CN104538380A
CN104538380A CN201410759285.7A CN201410759285A CN104538380A CN 104538380 A CN104538380 A CN 104538380A CN 201410759285 A CN201410759285 A CN 201410759285A CN 104538380 A CN104538380 A CN 104538380A
Authority
CN
China
Prior art keywords
capsulation material
chip
layer
monomer
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410759285.7A
Other languages
English (en)
Inventor
陈南南
王宏杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN201410759285.7A priority Critical patent/CN104538380A/zh
Publication of CN104538380A publication Critical patent/CN104538380A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明涉及一种小间距PoP封装单体，包括芯片、塑封材料和焊球；其特征是：所述焊球包括铜核球，在铜核球表面镀覆镀层钎料。所述焊球为椭球形、矩形柱形或圆柱形，铜核球为椭球形、矩形柱形或圆柱形。所述封装单体可以采用扇出型晶圆级封装或者基板PoP封装结构。本发明能够解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。

Description

小间距PoP封装单体
技术领域
本发明涉及一种小间距PoP封装单体，属于半导体封装技术领域。
背景技术
作为目前封装高密集成的主要方式，PoP（package on package，层叠封装）得到越来越多的重视。芯片的堆叠是提高电子封装高密化的主要途径之间，PoP设计已经在业界得到比较广泛的开发和应用。
现有技术中，一般采用锡球互连的PoP解决方案，这种结构在坍塌、位移（shift）等方面存在一定难度和不足。基板多层PoP芯片堆叠时，需将锡球与芯片一起塑封，不利于返修。传统的锡球X轴方向尺寸与Y轴尺寸相当，限制了间距时一步减小。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种小间距PoP封装单体，解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。
按照本发明提供的技术方案，所述小间距PoP封装单体，包括芯片、塑封材料和焊球；其特征是：所述焊球包括铜核球，在铜核球表面镀覆镀层钎料。
进一步的，所述焊球为椭球形、矩形柱形或圆柱形，铜核球为椭球形、矩形柱形或圆柱形。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的背面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的正面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料全部覆盖基板的背面。
进一步的，所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料部分覆盖基板的背面。
本发明所述的小间距PoP封装单体及PoP封装结构，将非中心对称型球或柱应用于扇出型晶圆级封装或PoP封装，可以解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。
附图说明
图1为本发明所述小间距PoP封装单体第一种实施例的示意图。
图2为本发明所述小间距PoP封装单体第二种实施例的示意图。
图3为本发明所述小间距PoP封装单体第三种实施例的示意图。
图4为本发明所述小间距PoP封装单体第四种实施例的示意图。
图5为本发明所述小间距PoP封装单体第五种实施例的示意图。
图6为本发明所述小间距PoP封装单体第六种实施例的示意图。
图7为本发明所述小间距PoP封装单体第七种实施例的示意图。
图8为本发明所述小间距PoP封装单体第八种实施例的示意图。
图9为本发明所述小间距PoP封装结构第一种实施例的示意图。
图10为本发明所述小间距PoP封装结构第二种实施例的示意图。
具体实施方式
下面结合具体附图对本发明作进一步说明。
实施例一：
如图1所示，本发明包括塑封材料1-1，塑封材料1-1中塑封芯片1-2，芯片1-2的正面与塑封材料1-1的正面平齐，芯片1-2的高度小于塑封材料1-1的高度；在所述塑封材料1-1的正面设置RDL层1-3，RDL层1-3中设置再布线金属走线层1-4，再布线金属走线层1-4上设置UBM层1-5，再布线金属走线层1-4连接UBM层1-5和芯片1-2上的电极；在所述UBM层1-5上设置焊球100，焊球100包括铜核球200，在铜核球200表面镀覆镀层钎料300，镀层钎料300可以采用镍或合金材料（如SAC合金钎料）；所述焊球100为椭球形、矩形柱形或圆柱形，铜核球200为椭球形、矩形柱形或圆柱形。
实施例一在制作时，采用现有技术中常规的方法（fan out WLP face down工艺）进行，具体为：在载体晶圆表面涂覆一层临时键合胶，将芯片1-2的电极面朝下贴片；采用塑封材料1-1将芯片1-2塑封并固化，然后将载体晶圆及塑封材料1-1翻转并去除载体晶圆及临时键合胶；在芯片1-2的电极一面制作RDL层1-3，在RDL层1-3上进行电镀、沉积，制作再布线金属走线层1-4和UBM层1-5；在UBM层1-5上植本发明所述的焊球100，将封装体切割成单个封装单体。
实施例二：
如图2所示，结构同实施例一，其中，在塑封材料1-1中还塑封有金属层2-1，金属层2-1的一表面与塑封材料1-1的正面平齐，金属层2-1的厚度小于塑封材料1-1的高度。
实施例三：
如图3所示，结构同实施例二，其中，在塑封材料1-1中还塑封有金属柱3-1，金属柱3-1的一端连接金属层2-1，另一端与塑封材料1-1的背面平齐。
实施例四：
如图4所示，结构同实施例一，其中，芯片1-2的背面与塑封材料1-1的背面平齐。
实施例四在制作时，采用现有技术（Fan out WLP face up工艺）进行，具体为：在载体晶圆表面涂覆一层临时键合胶，将芯片1-2的电极面朝上贴片；采用塑封材料1-1将芯片1-2塑封并固化，然后去除载体晶圆和临时键合胶；在芯片1-2的电极一面的表面制作RDL层1-3，在RDL层1-3上电镀、沉积，制作再布线金属走线层1-4和UBM层1-5；在UBM层1-5上植本发明所述的焊球100，将封装体切割成单个封装单体。
实施例五：
如图5所示，结构同实施例二，其中，芯片1-2的背面与塑封材料1-1的背面平齐，金属层2-1的一表面与塑封材料1-1的背面平齐，金属层2-1的厚度小于塑封材料1-1的高度。
实施例六：
如图6所示，结构同实施例三，其中，芯片1-2的背面与塑封材料1-1的背面平齐，金属层2-1的一表面与塑封材料1-1的背面平齐，金属层2-1的另一表面与金属柱3-1的一表面连接，金属柱3-1的另一表面与塑封材料1-1的正面平齐。
实施例七：
如图7所示，本发明为基板PoP封装结构，包括基板7-1，在基板7-1上采用塑封材料7-2塑封芯片7-3，在基板7-1的正面设置焊盘7-4，在焊盘7-4上设置焊球100；其中，塑封材料7-2全部覆盖基板7-1的背面。
实施例七在制作时，采用现有技术进行，具体为：在基板7-1进行贴片，将芯片7-3采用塑封材料7-2进行塑封并固化；再将基板7-1及塑封材料7-2翻转，在基板7-1正面的焊盘7-4上植本发明所述的焊球100，再将封装体切割成封装单体。
实施例八：
如图8所示，结构同实施例七，其中，塑封材料7-2部分覆盖基板7-1的背面。
如图9、图10所示，将本发明所述的小间距PoP封装单体进行堆叠、回流，可以得到小间距PoP封装结构；如图9所示，为将实施例四和实施例六所述的封装单体进行进堆叠；如图10所示，为将实施例七和实施例八所述的封装单体进行堆叠。
本发明案采用非中心对称型球（椭球形、矩形柱形、圆柱形等）取向排布应用于Fan out WLP（扇出型晶圆级封装）及PoP工艺，可以解决PoP堆叠加坍塌、偏移问题，并进一步减小间距，提高I/O数量；非对称型焊球的铜核球起到一定的支撑作用，在Y轴方向上达到PoP芯片堆叠的设计需求；同时，对比传统锡球，焊球在X轴方向可以设计很小，且回流前后变化较小，可以满足芯片小间距植球。这样的植球方法及结构，可以应用于PoP多层芯片互连堆叠，有效地解决坍塌、偏移等工艺问题。

Claims (10)

1.一种小间距PoP封装单体，包括芯片、塑封材料和焊球（100）；其特征是：所述焊球（100）包括铜核球（200），在铜核球（200）表面镀覆镀层钎料（300）。
2.如权利要求1所述的小间距PoP封装单体，其特征是：所述焊球（100）为椭球形、矩形柱形或圆柱形，铜核球（200）为椭球形、矩形柱形或圆柱形。
3.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
4.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
5.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的背面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
6.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
7.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
8.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的正面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
9.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料全部覆盖基板的背面。
10.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料部分覆盖基板的背面。
CN201410759285.7A 2014-12-10 2014-12-10 小间距PoP封装单体 Pending CN104538380A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410759285.7A CN104538380A (zh) 2014-12-10 2014-12-10 小间距PoP封装单体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410759285.7A CN104538380A (zh) 2014-12-10 2014-12-10 小间距PoP封装单体

Publications (1)

Publication Number Publication Date
CN104538380A true CN104538380A (zh) 2015-04-22

Family

ID=52853883

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410759285.7A Pending CN104538380A (zh) 2014-12-10 2014-12-10 小间距PoP封装单体

Country Status (1)

Country Link
CN (1) CN104538380A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428260A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN105428331A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构
CN106505073A (zh) * 2016-09-23 2017-03-15 江西盛泰光学有限公司 一种晶圆级玻璃上芯片封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1492491A (zh) * 2002-10-21 2004-04-28 矽统科技股份有限公司 具有导电凸块的覆晶基板及其导电凸块的制造方法
US20040126927A1 (en) * 2001-03-05 2004-07-01 Shih-Hsiung Lin Method of assembling chips
CN103904057A (zh) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 PoP封装结构及制造工艺
CN103904056A (zh) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 一种PoP封装结构及制造工艺
CN104051355A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 层叠封装结构及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126927A1 (en) * 2001-03-05 2004-07-01 Shih-Hsiung Lin Method of assembling chips
CN1492491A (zh) * 2002-10-21 2004-04-28 矽统科技股份有限公司 具有导电凸块的覆晶基板及其导电凸块的制造方法
CN104051355A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 层叠封装结构及其形成方法
CN103904057A (zh) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 PoP封装结构及制造工艺
CN103904056A (zh) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 一种PoP封装结构及制造工艺

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428260A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN105428331A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构
CN105428260B (zh) * 2015-12-22 2017-12-19 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN105428331B (zh) * 2015-12-22 2018-04-20 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构
CN106505073A (zh) * 2016-09-23 2017-03-15 江西盛泰光学有限公司 一种晶圆级玻璃上芯片封装结构

Similar Documents

Publication Publication Date Title
CN103887291B (zh) 三维扇出型PoP封装结构及制造工艺
CN103887279B (zh) 三维扇出型晶圆级封装结构及制造工艺
CN202523706U (zh) 扇出晶圆级半导体芯片三维堆叠封装结构
CN103904057B (zh) PoP封装结构及制造工艺
WO2017049928A1 (zh) 一种芯片封装结构及封装方法
WO2017075929A1 (zh) 一种扇出型封装结构及其制作方法
CN105118823A (zh) 一种堆叠型芯片封装结构及封装方法
CN103904056A (zh) 一种PoP封装结构及制造工艺
CN103400830B (zh) 多层芯片堆叠结构及其实现方法
CN104332457A (zh) 高密度IO互连PoP堆叠封装结构及其制造工艺
CN104576579A (zh) 一种三维叠层封装结构及其封装方法
CN104538380A (zh) 小间距PoP封装单体
CN104659004A (zh) 一种PoP封装结构及其制造方法
CN105161474A (zh) 扇出型封装结构及其生产工艺
CN107946282B (zh) 三维扇出型封装结构及其制造方法
CN105810592B (zh) 一种用于堆叠式封装的铜针结构及其制备方法
CN103441111B (zh) 一种三维封装互连结构及其制作方法
CN204118064U (zh) 一种芯片倾斜堆叠的圆片级封装单元
CN104659021A (zh) 一种三维圆片级扇出PoP封装结构及其制造方法
CN104465609A (zh) 铜核球PoP互连的封装结构和封装方法
CN205039150U (zh) 一种芯片封装结构
CN104241216A (zh) 一种封装高度可控的扇出型封装结构及制造方法
CN207624678U (zh) 一种三维pop封装结构
CN104201168A (zh) 一种芯片倾斜堆叠的圆片级封装单元及封装方法
CN203491244U (zh) 一种封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20150422