CN104536939A - Method for configurable energy-saving dispatching of multi-core embedded cache - Google Patents
Method for configurable energy-saving dispatching of multi-core embedded cache Download PDFInfo
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Abstract
The invention discloses a method for configurable energy-saving dispatching of a multi-core embedded cache. The method for configurable energy-saving dispatching of the multi-core embedded cache comprises the steps that application performance monitor parameters of the multi-core embedded system cache are set, algorithm optimization and improvement are conducted on an optimizing configuration research method of the multi-core embedded system cache, and changes of performance indexes under different cache configuration conditions are simulated to achieve the most reasonable optimized performance matching. The method achieves application of hardware performance to the maximum extent, achieves the multi-core embedded system data management capacity, and improves the overall performance of power consumption.
Description
Technical field
The invention belongs to embedded system technology field, particularly relate to the method for the configurable energy-saving distribution of a kind of multinuclear embedded high-speed memory buffer.
Background technology
Along with the development of society, the progress of science and technology, embedding people's formula system is applied to each neck city in life more and more widely with its distinctive superior function.From high-end specific application area as network calculations, communications electronics, Avionic Products, to some handheld devices of low side as MP5, e-book etc., consumer wishes the power supply deliverability that processing speed is more and more faster, work efficiency is more and more higher and more powerful bar none.The accumulation of these phenomenons also makes the practitioner of embedded system aspect recognize, the frequency of independent increase embedded system process device can not the overall performance of increase embedded system at double, the raising of corresponding performance can not be there is especially as concurrent operation, prediction execution and pipe technology etc. along with the raising of frequency, and catch up with the growing requirement to embedded system data image procossing, audio frequency and video process etc.Need concerning often increasing frequency 50% monokaryon embedded system the cost paying energy ezpenditure twice, and the embedded system of double-core is only increased to the energy ezpenditure of 30%, and vital status is played concerning the consumption of energy embedded system.
Cache memory (Cache) internal memory as the integrated assembly of high-end embedded system one, the introducing of cache memory (Cache) also for embedded system performance raising and reduce energy ezpenditure unpredicted new problem be provided.The method for designing of current embedded system processor relies on and provides enough large chip space to cache memory (Cache), ensure the unification of die size, chip performance and chip low-power consumption, the processor platform based on application-specific (the Xtensa platform of Tensilica) as nearest allows Cache can be self-defined.In the flush bonding processor of existing low-power consumption, the consumption of Cache accounts for the consumption of very large part energy substantially, document [A160MHz, 32b, 0.5W CMOS RISCmicroprocessor.Montanaro et al.JSSC, 1996,31 (11): 1703-1712.] show that the consumption of cache memory (Cache) energy account for 43% of the whole energy ezpenditure of processor.So for the correct configuration just very crucial factor beyond doubt of Cache an application program repeatedly run within a processor or class cache memory (Cache) configurable embedded system, and correct cache memory (Cache) configuration will be selected, often need to carry out the result that com-parison and analysis just can obtain needs from many aspects.The hit rate of such as cache memory (Cache) and processor energy ezpenditure and program execution time etc., document [WFornaciari et.al.A DesignFrameworkto Effciently ExploreEnergy-Delay Tradeoffs.CODES, 2001.pp260-265.X.Veraet.al..A Fast andAccurate Framework to Analyze and Optimize Cache Memory Behavior.ACMTOPLAS, 2004, 26 (2): 263-300.] mainly through adopting heuristic to cache memory (Cache) hit ratio estimation to cache memory (Cache) parameter designing space, document [J.EdlerandM.D.Hill.Dinero IV Trace-Driven Uniprocessor Cache Simulator.] is estimated single cache memory (Cache) configuration accurately by using instrument.These methods are all studied from the cache performance of certain angle to embedded system.Also more deep about polycaryon processor cache memory (Cache) research at home, such as document [in multiple nucleus system Real-Time Scheduling Police design and analysis design [D]. Deng Qingxu. Northeastern University, 2009.] conduct in-depth research with regard to the Real-Time Scheduling Police that cache memory (Cache) communication is responsive, and achieve multinuclear Real-Time Scheduling prototype system, document [operating system scheduling research [J] of chip-scale multiline procedure processor. Shao Lisong, hole gold bead, wear East China. computer engineering, 2009,35 (15): 277-279.] theoretic discussion has been carried out to the problem of load balancing of polycaryon processor inside, and utilized cooperative scheduling to avoid cache memory (Cache) jitter problem, Xiong Wei, Yin Jianping, institute's light, Zhao Zhiheng. polycaryon processor is towards shared cache memory (Cache) splitting scheme of low-power consumption. computer engineering and science .2010, (32) 10:26-29.] polycaryon processor that have studied towards low-power consumption shares the partitioning technology of cache memory (Cache), the crash rate of dynamically collection procedure is carried out by adding crash rate watch-dog within a processor, then shared cache memory (Cache) partitioning algorithm towards low-power consumption is used, shared cache memory (Cache) partition strategy in calculated performance loss threshold range.
The energy ezpenditure that existing monokaryon and dual core embedded system increase processing speed existence is larger.
Summary of the invention
The object of the embodiment of the present invention is the method providing the configurable energy-saving distribution of a kind of multinuclear embedded high-speed memory buffer, is intended to solve the problem that the energy ezpenditure of existing monokaryon and the existence of dual core embedded system increase processing speed is larger.
The embodiment of the present invention realizes like this, a method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer, the method for the configurable energy-saving distribution of this multinuclear embedded high-speed memory buffer comprise multinuclear embedded system cache cache memory application performance monitor parameter is arranged, the research method of distributing rationally of multinuclear embedded system cache memory carries out algorithm optimization improvement, by emulating, realize the Performance Match of most reasonably optimizing to the change of performance index in different cache configuration situations;
Described setting multinuclear embedded system cache cache memory application performance monitor parameter refers to and utilizes the application performance monitor parameter of computer process to multinuclear embedded system cache cache memory repeatedly to arrange, and obtains best Optimal Parameters;
Described multinuclear embedded system cache memory distribute rationally research method carry out algorithm optimization improve refer to that monitor parameters that input is optimized arranges multinuclear embedded system cache memory distribute research method rationally, utilize computer program to carry out algorithm optimization improvement to research method, obtain optimum Research on configuration method;
By emulating the change of performance index in different cache configuration situations, described refers to that the Research on configuration method of utilization optimum carries out emulation experiment respectively by the change of the index in different cache configuration situations, obtain different experimental datas, select best experimental result.
The Performance Match of the most reasonably optimizing of described realization refers to that in selected experimental result, energy consumption runs out and little configuration may carry out building of actual items by the simulation experiment result above, thus realizes the Performance Match of most reasonably optimizing.
Further, described multinuclear embedded system cache memory distribute rationally research method carry out algorithm optimization improve step comprise based on performance and fairness be benchmark the dead block prediction of cache, cache access was lost efficacy, cache looks ahead, be that benchmark cache sharing divides, energy simulation calculates based on performance and fairness;
The described cache dead block prediction being benchmark based on performance and fairness refers to first by carrying out the prediction in data to the dead block of the cache based on performance and fairness being benchmark, ready for accessing cache;
Described cache accesses inefficacy and refers to when accessing cache process, there will be the result that cache access was lost efficacy;
Described cache looks ahead and refers to after cache access was lost efficacy, and takes the measure that cache looks ahead;
Described is after the division of benchmark cache sharing refers to that cache looks ahead based on performance and fairness, by based on performance and fairness being the division of benchmark, cache sharing;
Described energy simulation calculates the division referring to and utilize cache, arranges energy simulation model and carries out energy simulation calculating, obtains optimum result of calculation.
The method of the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer provided by the invention, by adopting corresponding cache memory (Cache) to distribute rationally, achieving and applying to greatest extent hardware performance; By emulating the configuration of different cache memories (Cache), and multinuclear embedded system emulation benchmark set compares research, find the correlativity between cache memory (Cache), and then demonstrate proposed research method correctness and validity from multinuclear embedded system in the unit area utilization ratio of energy ezpenditure and cache memory (Cache), finally achieve the raising on the overall performance of multinuclear embedded system data managerial ability, power consumption.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer that the embodiment of the present invention provides;
Fig. 2 is that the research method of distributing rationally of the multinuclear embedded system cache memory of the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer that the embodiment of the present invention provides carries out the process flow diagram that algorithm optimization improves step;
Fig. 3 is that the research method of distributing rationally of the multinuclear embedded system cache memory of the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer that the embodiment of the present invention provides is carried out in algorithm optimization improvement based on the process flow diagram that performance and fairness are benchmark cache sharing partiting step.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Below in conjunction with drawings and the specific embodiments, application principle of the present invention is further described.
As shown in Figure 1, a method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer, the method for the configurable energy-saving distribution of this multinuclear embedded high-speed memory buffer comprise S101 is arranged to multinuclear embedded system cache cache memory application performance monitor parameter, the research method of distributing rationally of multinuclear embedded system cache memory carries out algorithm optimization and improves S102, by carrying out emulation S103 to the change of performance index in different cache configuration situations, realizes the Performance Match S104 of most reasonably optimizing;
Described S101 is arranged to multinuclear embedded system cache cache memory application performance monitor parameter refer to and utilize the application performance monitor parameter of computer process to multinuclear embedded system cache cache memory repeatedly to arrange, obtain best Optimal Parameters;
Described multinuclear embedded system cache memory distribute that research method carries out that algorithm optimization improves that monitor parameters that S102 refers to that input is optimized arranges multinuclear embedded system cache memory rationally distribute research method rationally, utilize computer program to carry out algorithm optimization improvement to research method, obtain optimum Research on configuration method;
By carrying out emulating S103 to the change of performance index in different cache configuration situations, described refers to that the Research on configuration method of utilization optimum carries out emulation experiment respectively by the change of the index in different cache configuration situations, obtain different experimental datas, select best experimental result.
The Performance Match S104 of the most reasonably optimizing of described realization refers to that in selected experimental result, energy consumption runs out and little configuration may carry out building of actual items by the simulation experiment result above, thus realizes the Performance Match of most reasonably optimizing.
Further, as shown in Figure 2, described multinuclear embedded system cache memory distribute rationally research method carry out algorithm optimization improve S102 step cache dead block prediction S201, cache that to comprise based on performance and fairness be benchmark access inefficacy S202, cache look ahead S203, be that benchmark cache sharing divides S204, energy simulation calculates S205 based on performance and fairness;
The described cache dead block prediction S201 being benchmark based on performance and fairness refers to first by carrying out the prediction in data to the dead block of the cache based on performance and fairness being benchmark, ready for accessing cache;
Described cache accesses inefficacy S202 and refers to when accessing cache process, there will be the result that cache access was lost efficacy;
Described cache look ahead S203 refer to cache access lost efficacy after, take the measure that cache looks ahead;
Described is after benchmark cache sharing division S204 refers to that cache looks ahead based on performance and fairness, by based on performance and fairness being the division of benchmark, cache sharing;
Described energy simulation calculates S205 and refers to the division utilized cache, arranges energy simulation model and carries out energy simulation calculating, obtains optimum result of calculation.
As shown in Figure 3, the research method of distributing rationally of the multinuclear embedded system cache memory of the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer of the embodiment of the present invention to carry out in algorithm optimization improvement based on performance and fairness being that benchmark cache sharing partiting step comprises:
Step one, carries out thread and calculates based on the equitable degree variable of performance;
Step 2, according to cache correlation principle, to system can distributing cache block size and determine;
Step 3, carries out the confirmation of priority to thread;
Step 4, carries out the distribution of cache number of blocks to thread according to thread priority;
Step 5, carries out the calculating of crash rate fairness metric according to the cache quantity that thread has distributed;
Step 6, compares from the thread cache crash rate fairness metric calculated, if number of threads is greater than two, then therefrom selects maximal value and minimum value thread;
Whether step 7, be less than fairness metric variable critical value according to the difference of the cache crash rate fairness metric maxima and minima elected and judge; If be false, then the cache quantity of distributing two threads redistributed, repeat step 5 and seven;
Step 8, if be true, then delete these two threads, repeats step 6 and seven;
Step 9, if number of threads is one or is zero.Algorithm terminates.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer, it is characterized in that, the method for the configurable energy-saving distribution of this multinuclear embedded high-speed memory buffer comprise multinuclear embedded system cache cache memory application performance monitor parameter is arranged, the research method of distributing rationally of multinuclear embedded system cache memory carries out algorithm optimization improvement, by emulating, realize the Performance Match of most reasonably optimizing to the change of performance index in different cache configuration situations;
Cache memory application performance monitor parameter is carried out arranging and is referred to and utilize the application performance monitor parameter of computer process to multinuclear embedded system cache cache memory repeatedly to arrange, and obtains best Optimal Parameters;
The research method of distributing rationally of cache memory is carried out algorithm optimization and is improved and refer to that the monitor parameters that input is optimized arranges the Optimal Configuration Method of multinuclear embedded system cache memory, utilize computer program to carry out algorithm optimization improvement to method, obtain optimum collocation method;
Refer to that the collocation method of utilization optimum carries out emulation experiment respectively by the change of the index in different cache configuration situations by emulating the change of performance index in different cache configuration situations, obtain different experimental datas, select best experimental result;
The Performance Match realizing most reasonably optimizing refers to that in selected experimental result, energy consumption runs out and little configuration may carry out building of actual items by the simulation experiment result above, realizes the Performance Match of most reasonably optimizing.
2. the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer as claimed in claim 1, it is characterized in that, the Optimal Configuration Method of this multinuclear embedded system cache memory carry out algorithm optimization improve step comprise based on performance and fairness be benchmark the dead block prediction of cache, cache access was lost efficacy, cache looks ahead, be that benchmark cache sharing divides, energy simulation calculates based on performance and fairness;
The cache dead block prediction being benchmark based on performance and fairness refers to first by carrying out the prediction in data to the dead block of the cache based on performance and fairness being benchmark, for access cache is ready;
Cache accesses inefficacy and refers to when accessing cache process, there will be the result that cache access was lost efficacy;
Cache looks ahead and refers to after cache access was lost efficacy, and takes the measure that cache looks ahead;
Based on performance and fairness be benchmark cache sharing divide refer to that cache looks ahead after, by based on performance and fairness being the division of benchmark, cache sharing;
Energy simulation calculates the division referring to and utilize cache, arranges energy simulation model and carries out energy simulation calculating, obtains optimum result of calculation.
3. the method for the configurable energy-saving distribution of multinuclear embedded high-speed memory buffer as claimed in claim 1, it is characterized in that, the research method of distributing rationally of the multinuclear embedded system cache memory of the method for the configurable energy-saving distribution of this multinuclear embedded high-speed memory buffer to carry out in algorithm optimization improvement based on performance and fairness being that benchmark cache sharing partiting step comprises:
Step one, carries out thread and calculates based on the equitable degree variable of performance;
Step 2, according to cache correlation principle, can distribute cache block size to system and determine;
Step 3, carries out the confirmation of priority to thread;
Step 4, carries out the distribution of cache number of blocks to thread according to thread priority;
Step 5, carries out the calculating of crash rate fairness metric according to the cache quantity that thread has distributed;
Step 6, compares from the thread cache crash rate fairness metric calculated, if number of threads is greater than two, then therefrom selects maximal value and minimum value thread;
Whether step 7, be less than fairness metric variable critical value according to the difference of the cache crash rate fairness metric maxima and minima elected and judge; Be false, then the cache quantity of distributing two threads redistributed, repeat step 5 and seven;
Step 8 is true, then these two threads are deleted, repeat step 6 and seven;
Step 9, number of threads is one or is zero, and algorithm terminates.
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Cited By (4)
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| CN104991884A (en) * | 2015-06-18 | 2015-10-21 | 中国科学院自动化研究所 | Heterogeneous multi-core SoC architecture design method |
| CN105681306A (en) * | 2016-01-13 | 2016-06-15 | 华北水利水电大学 | Spatial data security control system based on access mode protection |
| CN106844235A (en) * | 2016-12-23 | 2017-06-13 | 北京北大众志微系统科技有限责任公司 | A kind of method and device for realizing cache replacement |
| CN115421918A (en) * | 2022-09-16 | 2022-12-02 | 河南省职工医院 | Transcranial magnetic stimulation equipment and system based on RT-Linux |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104991884A (en) * | 2015-06-18 | 2015-10-21 | 中国科学院自动化研究所 | Heterogeneous multi-core SoC architecture design method |
| CN104991884B (en) * | 2015-06-18 | 2017-12-05 | 中国科学院自动化研究所 | Heterogeneous polynuclear SoC architecture design method |
| CN105681306A (en) * | 2016-01-13 | 2016-06-15 | 华北水利水电大学 | Spatial data security control system based on access mode protection |
| CN106844235A (en) * | 2016-12-23 | 2017-06-13 | 北京北大众志微系统科技有限责任公司 | A kind of method and device for realizing cache replacement |
| CN115421918A (en) * | 2022-09-16 | 2022-12-02 | 河南省职工医院 | Transcranial magnetic stimulation equipment and system based on RT-Linux |
| CN115421918B (en) * | 2022-09-16 | 2023-05-12 | 河南省职工医院 | Transcranial magnetic stimulation equipment and system based on RT-Linux |
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