CN104517843B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN104517843B CN104517843B CN201310455829.6A CN201310455829A CN104517843B CN 104517843 B CN104517843 B CN 104517843B CN 201310455829 A CN201310455829 A CN 201310455829A CN 104517843 B CN104517843 B CN 104517843B
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Abstract
A kind of forming method of semiconductor devices, including：Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area, and the first area semiconductor substrate surface has first grid structure, and the second area semiconductor substrate surface has second grid structure；Form the side wall film of the covering first grid structure, second grid structure and Semiconductor substrate；Form the ARC of the covering side wall film；Form the photoresist layer positioned at first area anti-reflective coating layer surface；Using the photoresist layer as mask, etching removes the ARC of second area；Using the photoresist layer as mask, the side wall film of second area is etched back to, in second area semiconductor substrate surface formation side wall, and the side wall is located at second grid structure both sides.The present invention is while raising forms photoresist layer accuracy, it is to avoid formation process causes damage to Semiconductor substrate, improves the flatness of Semiconductor substrate, improves the electric property of semiconductor devices.
Description
Technical field
The present invention relates to the forming method of field of semiconductor fabrication, more particularly to semiconductor devices.
Background technology
In the process for making of semiconductor devices, the method that the photoetching of development is exposed to photoresist is realization figure
The main method of shape transfer, the specific region of the lower coating processed for protecting is not etched or adulterated, common, is located
The lower coating of reason is Semiconductor substrate.
With the development of chip technology, the feature dimensions of chip are less and less, the material of processed lower coating
It is more and more diversified, therefore during photolithographic exposure, due to produced by optical property difference between photoresist layer and its lower coating
Exposure reflection problems, into the key factor of influence exposure performance.So, only it is exposed using only conventional photoresist
Method has been difficult to the accurate transfer of fine pattern.
To meet the requirement of photoetching process, ARC (Anti-Reflective Coating：ARC) technology is answered
Precision for improving photoetching in photoetching.The effect of ARC is mainly：Prevent light by being covered after photoresist under
Bed boundary is reflected；And the light reflected can be interfered with incident light, photoresist is caused to be unable to uniform exposure.Anti-reflective coating
Layer includes reflection coating provided (Top Anti-Reflective Coating：) and bottom antireflective coating (Bottom TARC
Anti-Reflective Coating：BARC).
However, the Semiconductor substrate of the semiconductor devices of prior art formation is vulnerable to damage, influence semiconductor devices
Electric property.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of the semiconductor devices of optimization, is improving the photoetching of formation
While glue-line accuracy, it is to avoid semiconductor devices formation process causes damage to Semiconductor substrate, and reduces technique to side wall
Etching is caused, the electric property of semiconductor devices is improved.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor lining is provided
Bottom, the Semiconductor substrate includes first area and second area, and the first area semiconductor substrate surface has the first grid
Pole structure, the second area semiconductor substrate surface has second grid structure；Form the covering first grid structure, the
The side wall film of two grid structures and Semiconductor substrate；Form the ARC of the covering side wall film；In the first area
Anti-reflective coating layer surface formation photoresist layer；Using the photoresist layer as mask, etching removes the anti-reflective coating of second area
Layer；Using the photoresist layer as mask, the side wall film of second area is etched back to, in second area semiconductor substrate surface formation side
Wall, and the side wall is located at second grid structure both sides.
Optionally, the side wall film is single layer structure or sandwich construction.
Optionally, when the side wall film is single layer structure, the side wall film is silicon nitride layer or silicon oxide layer；The side wall
When film is sandwich construction, the side wall film is the sandwich construction of silicon oxide layer and silicon nitride layer.
Optionally, the side wall film of second area is etched back to using anisotropic etch process.
Optionally, the ARC is formed using spin coating proceeding.
Optionally, the thickness of the ARC is 100 angstroms to 2000 angstroms.
Optionally, it is in the forming step of the anti-reflective coating layer surface formation photoresist layer of the first area：Formation is covered
The initial lithographic glue-line of lid ARC；By exposure imaging technique, the anti-reflective coating layer surface positioned at second area is removed
Initial lithographic glue-line, the first area anti-reflective coating layer surface formation photoresist layer.
Optionally, the ARC for removing second area is etched using dry etch process.
Optionally, the dry etch process is reactive ion etching.
Optionally, the ARC is organic antireflective coating.
Optionally, in addition to step：Using the photoresist layer as mask, the semiconductor in the second grid structure both sides
Doped region is formed in substrate；Remove the photoresist layer and the ARC of first area.
Optionally, the technique of the photoresist layer of the removal first area and ARC is cineration technics.
Optionally, the doped region is lightly doped district or heavily doped region.
Optionally, the doped region is formed using ion implantation technology.
Compared with prior art, technical scheme has advantages below：
In the present embodiment, side wall film is formed between ARC and Semiconductor substrate, when etching removes the secondth area
During the ARC in domain, the side wall film protection Semiconductor substrate is not etched technique and destroyed, and improves Semiconductor substrate table
The flatness in face, improves the electric property of semiconductor devices.
Meanwhile, in the present embodiment, after the ARC of second area is removed, the side wall film of second area is etched back to,
Form the side wall positioned at second grid structure both sides, it is to avoid the technique that side wall is removed second area ARC is etched；
And when removing the ARC of second area, influenceed in the side wall film of second grid structure two side areas by etching technics
It is smaller；Compared with prior art, the present invention forms side wall after second area ARC is removed, it is to avoid remove second
Region anti-reflective coating layer process offside wall causes etching, therefore the width of the side wall of the invention formed is larger, can effectively hinder
The easy diffusion ion kept off in the metal silicide being subsequently formed, prevents the ion in metal silicide from diffusing into channel region；And
Because the width of side wall is larger, it can effectively stop and interpenetrate between the doped region being subsequently formed, improve semiconductor devices
Reliability, optimizes the electric property of semiconductor devices.
Further, the photoresist layer and ARC of first area are removed in the present embodiment using cineration technics, it is to avoid
Remove the photoresist layer and ARC and damage is caused to second area Semiconductor substrate, further improve semiconductor devices
Electric property.
Further, the present embodiment is in photoresist layer ARC formed below, and the ARC is deposited
Make it that photoresist layer exposure is uniform, improving the accuracy for the photoresist layer figure to be formed.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of embodiment formation semiconductor devices；
Fig. 2 is light reflectogram of the light in active area and isolation structure interface of photoresist layer exposure；
Fig. 3 to Figure 16 is the cross-sectional view of another embodiment of the present invention semiconductor devices forming process.
Embodiment
As stated in the Background Art, the electric property of the semiconductor devices of prior art formation is poor.
Therefore, the forming method for semiconductor devices is studied, the forming method of semiconductor devices includes following step
Suddenly, it refer to Fig. 1：Step S1, offer Semiconductor substrate, the Semiconductor substrate include first area and second area, and institute
Stating first area semiconductor substrate surface has first grid structure, and the second area semiconductor substrate surface has second gate
Pole structure；Step S2, the first area semiconductor substrate surface formation the first side wall, first side wall be located at the first grid
Pole structure both sides, in the second area semiconductor substrate surface the second side wall of formation, second side wall is located at second grid
Structure both sides；Step S3, the second area surface formed photoresist layer；Step S4, using photoresist layer as mask, to first
The first area Semiconductor substrate formation doping of grid structure both sides, forms doped region；Step S5, the photoetching for removing second area
Glue-line.
The forming method of the semiconductor devices of above-mentioned offer, after forming photoresist layer on second area surface, photoresist layer
Figure and the expected figure formed have deviation.Analyzing above mentioned problem Producing reason is：First, in photoresist layer exposure process
In, the light of exposure reflects in semiconductor substrate surface, causes photoresist layer exposure uneven.Next, in order to prevent half
Electrically connected in conductor device, first area and second area are isolated using isolation structure, refer to Fig. 2, AA1 is
One region（Active area）, AA2 is second area, and STI is isolation structure, and PR is photoresist layer；In photoresist layer exposure process,
The light 01 of exposure reflects in the interface of first area Semiconductor substrate and isolation structure, causes the side wall of photoresist layer
Uneven exposure, influence subsequently forms doped region in the Semiconductor substrate of first area.
To solve the above problems, ARC is formed between Semiconductor substrate and photoresist layer, the antireflection
Coating avoids photoresist layer in exposure imaging, and the light of exposure is in semiconductor substrate surface or Semiconductor substrate and isolation structure
Boundary layer reflects, and improves the accuracy in the anti-reflective coating layer surface formation photoresist layer of second area.
However, being formed after ARC, the follow-up technique for removing first area ARC is made to Semiconductor substrate
Into damage, the electric property of semiconductor devices has been had a strong impact on.Forming method for semiconductor devices is further studied
It was found that, the reason for causing above mentioned problem is as follows：
The technique of the ARC of the removal first area is dry etching, and the dry etch process is to the firstth area
The semiconductor substrate surface in domain causes etching；And because the thickness of ARC is thicker（The thickness of ARC is more than the
The thickness of one grid structure or second grid structure）, therefore the ARC of dry etching first area process time compared with
It is long, cause dry etch process to cause the etching of long period, the semiconductor lining of first area to first area Semiconductor substrate
Bottom sustains damage.Specifically, the dry etch process causes the semiconductor substrate surface of first area uneven, subsequently exist
During semiconductor substrate surface formation metal silicide, the interfacial state between the metal silicide and Semiconductor substrate is poor, unfavorable
In reducing contact of semiconductor device resistance, the electric property of semiconductor devices is influenceed.
Meanwhile, the first side wall of the semiconductor devices of above method formation is also removed the ARC of first area
Technique is influenceed, specifically, first side wall is etched, causes the width of the first side wall to reduce；Extended meeting is in the first side wall afterwards
There is the ion easily spread in the first area semiconductor substrate surface formation metal silicide of both sides, the metal silicide；
If the width of first side wall reduces, the ion easily spread in metal silicide can be caused to be diffused to by the first side wall and partly led
In the channel region of body device, the degraded performance of semiconductor devices is caused；And first lateral wall width it is smaller, can cause to be subsequently formed
Doped region easily interpenetrate, deteriorate semiconductor devices electric property.
Therefore, the present invention provides a kind of forming method of the semiconductor devices of optimization, served as a contrast in ARC and semiconductor
Side wall film is formed between bottom, and after the ARC of second area is removed, is etched back to the formation of side wall film and is located at second grid
The side wall of structure both sides.The present invention avoids removal anti-reflective coating double of conductor substrate of layer process from causing damage, and is removed in etching
Side wall is formed after ARC, it is to avoid side wall is etched technogenic influence, improves the electric property of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 16 is the cross-sectional view of another embodiment of the present invention semiconductor devices forming process.
Fig. 3 be refer to there is provided Semiconductor substrate 100, the Semiconductor substrate 100 includes first area I and second area
II, the first area I surface of Semiconductor substrate 100 have first grid structure 110, the semiconductor of the second area II
The surface of substrate 100 has second grid structure 120.
The Semiconductor substrate 100 is Si substrates, Ge substrates, GeSi substrates or GaAs substrates；The Semiconductor substrate 100
Surface can also form some epitaxial interface layers or strained layer to improve the electric property of semiconductor devices.In the implementation of the present invention
In example, the Semiconductor substrate 100 is Si substrates.
The first area I is NMOS area or PMOS area, and the second area II is NMOS area or PMOS area.
Wherein, when the first area I is NMOS area, the second area II is PMOS area, when the first area I is
During PMOS area, the second area II is NMOS area.In an embodiment of the present invention, using the first area I as NMOS
Region, second area II is that PMOS area does exemplary illustrated.
It should also be noted that, the first area I and second area II can be adjacent or interval, should not too it limit
Protection scope of the present invention.
Isolation structure 101 can also be formed in the Semiconductor substrate 100, existing isolation structure generally uses shallow ridges
Groove is isolated.The packing material of the isolation structure 101 can be the one or more in silica, silicon nitride, silicon oxynitride.
The first grid structure 110 includes being located at the first gate oxide 111, the position on the surface of Semiconductor substrate 100
First gate electrode layer 112 in the surface of the first gate oxide 111 and the first top positioned at 112 surface of first gate electrode layer
Portion's mask layer 113.
The second grid structure 120 includes being located at the second gate oxide 121, the position on the surface of Semiconductor substrate 200
The second gate electrode layer 122 in the surface of the second gate oxide 121 and the second top positioned at the surface of the second gate electrode layer 112
Portion's mask layer 123.
The material of the gate oxide 121 of first gate oxide 111 or second be silica or high K medium material, it is described
The material of first gate electrode layer 112 or the second gate electrode layer 122 is polysilicon, the polysilicon or metal of doping, first top
The material of the top mask layer 123 of portion's mask layer 113 or second is silicon nitride.
First top mask layer 113 or the second top mask layer 123 act as protection first grid structure 110 or
The top of second grid structure 120 is not destroyed by subsequent technique.
Fig. 4 is refer to, the covering first grid structure 110, second grid structure 120 and Semiconductor substrate 100 is formed
Side wall film.
The side wall film is act as：The surface of Semiconductor substrate 100 is protected not remove ARC by subsequent etching
Technique is destroyed；The side wall film can also be subsequently formed positioned at first grid structure 110 or the both sides of second grid structure 120
Side wall.
The formation process of the side wall film is chemical vapor deposition or ald.
The side wall film is single layer structure or sandwich construction.
In the present embodiment, the side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103.Using atomic layer
Depositing operation forms the silicon oxide layer 102 and silicon nitride layer 103.The thickness of the silicon oxide layer 102 is 10 angstroms to 100 angstroms,
The thickness of the silicon nitride layer 103 is 50 angstroms to 200 angstroms.
In other embodiments of the present invention, the side wall film is the single layer structure of silicon oxide layer or silicon nitride layer, the side
Wall film can also be the sandwich construction of silicon oxide layer, silicon nitride layer and silicon oxide layer.
Fig. 5 is refer to, the first ARC 104 of the covering side wall film is formed.
In the present embodiment, the top of first ARC 104 is higher than first grid structure 110 or second grid knot
The top of structure 120, it is to avoid because the top of the first ARC 104 is less than first grid structure 110 or second grid structure 120
During top, the photoresist layer being subsequently formed is uneven in first grid structure 110 or the exposure of the surface region of second grid structure 120
Even, influence forms the accuracy of photoresist layer.
The effect of first anti-reflecting layer 104 is mainly：When preventing that the initial lithographic glue-line being subsequently formed from exposing, light
Reflected by initial lithographic glue-line at the interface of Semiconductor substrate 100, it is to avoid the light of reflection can be interfered with incident light,
And avoiding occurring light reflection in isolation structure 101 and the interface of Semiconductor substrate 100 so that initial lithographic glue-line can uniformly expose
Light, so as to form the photoresist layer with preferable pattern.
In the present embodiment, first ARC 104 is located at the surface of silicon nitride layer 103.
The formation process of first ARC 104 is spin coating proceeding or chemical vapor deposition method, described first
The thickness of ARC 104 is 100 angstroms to 2000 angstroms.
First ARC 104 is inorganic anti-reflective coating or organic antireflective coating.
The material of the inorganic anti-reflective coating be titanium, titanium oxide, titanium nitride, chromium oxide, carbon, amorphous silicon, silicon nitride,
Silicon oxynitride or silicon oxide carbide；The material of the organic antireflective coating is made up of light absorbing material and polymeric material, described
Organic antireflective coating includes organic antireflective coating and siliceous organic antireflective coating without silicon.
In the present embodiment, first ARC 104 is organic antireflective coating, forms described using spin coating proceeding
First ARC 104.
Fig. 6 is refer to, the first photoresist layer 105 is formed on the surface of the first ARC 104 of the first area I.
The forming step of first photoresist layer 105 is：Form the initial light photoresist of the first ARC 104 of covering
Layer；By exposure imaging technique, the initial lithographic glue-line positioned at the second area II surface of the first ARC 104 is removed,
The first photoresist layer 105 is formed on the surface of the first ARC 104 of the first area I.
Due to being formed with the first ARC 104, described first between initial lithographic glue-line and Semiconductor substrate 100
ARC 104 make it that the exposure of initial lithographic glue-line is uniform, so as to accurately remove the initial lithographic positioned at second area II
Glue-line, in first area, the I surface of the first ARC 104 forms the first photoresist layer 105 with good pattern, it is to avoid
Generation process deviation.
Fig. 7 is refer to, is mask with first photoresist layer 105, etching removes second area II the first antireflection
Coating 104.
The first ARC 104 positioned at second area II is removed, partly leading for the both sides of second grid structure 120 is exposed
The surface of body substrate 100, subsequently to form doped region in the Semiconductor substrate 100 of the both sides of second grid structure 120.
First ARC 104 is removed using dry etch process or cineration technics.
During due to removing first ARC 104 using cineration technics, the cineration technics also can be to the first light
Photoresist layer 105 causes damage, reduces the figure accuracy of the first photoresist layer 105, the technique for influenceing to be subsequently formed doped region.Cause
This, in the present embodiment, the first ARC 104 for removing second area II is etched using dry etch process, it is to avoid to the
The figure of one photoresist layer 105 causes damage.
As one embodiment, the dry etch process is reactive ion etching, the reactive ion etching process
Technological parameter is：Reacting gas is H2、N2And CF4, wherein, H2Flow is 100sccm to 200sccm, N2Flow be 10sccm extremely
200sccm, CF4Flow be 10sccm to 100sccm, reaction chamber pressure be 100 millitorrs to 1 support, chamber temp be 200 degree extremely
350 degree, RF source power is 100 watts to 500 watts.
In the present embodiment, when being removed using dry etch process positioned at second area II the first ARC 104,
The second area II surface of Semiconductor substrate 100 has side wall film, and the side wall film stops the etching gas of reactive ion etching
Contacted with Semiconductor substrate 100, so as to avoid the dry etch process from causing to damage to second area II Semiconductor substrates 100
Wound, when subsequently forming metal silicide on the surface of Semiconductor substrate 100 of the both sides of second grid structure 120, the metal silication
Thing is contacted closely with the surface of Semiconductor substrate 100, so as to improve the electric property of semiconductor devices.
If side wall film is not formed between the first ARC 104 and Semiconductor substrate 100, due to the first anti-reflective coating
The thickness of layer 104 is thicker（200 angstroms to 2000 angstroms）, then the process time of reactive ion etching process is longer；And serve as a contrast semiconductor
Being placed in the reaction chamber of reactive ion etching process for the long period of bottom 100, can cause reactive ion etching process to second
Etching injury is caused on the surface of region II Semiconductor substrates 100, causes the surface irregularity of Semiconductor substrate 100, and influence is partly led
The electric property of body device.When etching the first ARC for removing the second area II using dry etch process, do
Method etching technics has anisotropic specific, and the etching gas of dry etching have the gas perpendicular with semiconductor substrate surface
Stream flow direction, therefore, the side wall film positioned at the both sides of second grid structure 120 by dry etch process is influenceed smaller, positioned at the
The width of the side wall film of the two side areas of two grid structure 120 is with differing smaller before dry etching.
Fig. 8 is refer to, is mask with first photoresist layer 105, second area II side wall film is etched back to, second
The surface of region II Semiconductor substrates 100 forms side wall, and the side wall is located at the both sides of second grid structure 120.
Second area II side wall film is etched back to using anisotropic etch process.
As one embodiment, the anisotropic etch process is dry etching, the technique of the dry etch process
Parameter is：Etching gas include CF4、CHF3And Ar, CHF3Flow is 65sccm to 200sccm, CF4Flow for 30sccm extremely
50sccm, Ar flow be 50sccm to 70sccm, reaction chamber pressure be 0 millitorr to 5 millitorrs, source power be 200 watts extremely
1000 watts, bias voltage is 200V to 1000V.
In the present embodiment, the side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103, therefore, formation
Side wall is the sandwich construction of monox lateral wall 132 and silicon nitride spacer 133.
If the side wall of the both sides of second grid structure 120 shape before second area II the first ARC 104 is removed
Into then when etching removes second area II the first ARC 104, the etching technics can also be carved to side wall
Erosion, causes the width of side wall to reduce；Extended meeting forms metal silicide on the surface of Semiconductor substrate 100 of side wall both sides afterwards, described
There is the ion easily spread in metal silicide；The reduction of lateral wall width can cause side wall to become the blocking capability of easy diffusion ion
Weak, the ion easily spread in metal silicide is easily diffused in the channel region below second grid structure by side wall, causes half
The reliability reduction of conductor device, electric property deteriorates.And in the present embodiment, due to the side of the both sides of second grid structure 120
Wall is formed after second area II the first ARC 104 is removed, it is possible to prevente effectively from dry etch process is to second
The side wall of the both sides of grid structure 120 causes etching, and the lateral wall width formed in the both sides of second grid structure 120 is larger, can be effective
Barrier metal silicide in easily diffusion ion diffuse to undesirable region, improve the reliability of semiconductor devices, optimization is partly led
The electric property of body device.
Fig. 9 is refer to, is mask with first photoresist layer 105, in partly leading for the both sides of second grid structure 120
The first doped region 106 is formed in body substrate 100.
First doped region 106 is lightly doped district or heavily doped region.
In the present embodiment, illustrate that the side wall is forms with first doped region 106 for presenting a demonstration property of heavily doped region
State the master wall of heavily doped region.
First is formed using ion implantation technology in the second area II Semiconductor substrates 100 of the side wall both sides to adulterate
Area 106.
The present embodiment illustrates by presenting a demonstration property of PMOS area of the second area II, and first doped region 106 is mixed
Miscellany type adulterates for p-type.As one embodiment, the concrete technology for forming the doped region 106 using ion implantation technology is joined
Number is：The p-type Doped ions are boron or indium, and the energy of ion implanting is 1kev to 50kev, and ion implantation dosage is
1E15atom/cm2To 5E19atom/cm2。
In other embodiments of the present invention, first doped region is lightly doped district, using ion implantation technology formation institute
State lightly doped district.
Figure 10 is refer to, first photoresist layer 105 is removed（It refer to Fig. 9）With first area I the first antireflection
Coating 104（It refer to Fig. 9）.
In the present embodiment, the first photoresist layer 105 and first area I the first ARC are removed using cineration technics
104, can farthest it reduce when removing the first photoresist layer 105 and the first ARC 104 to Semiconductor substrate 100
The damage caused.
As one embodiment, the specific process parameter of the cineration technics is：The gas that the cineration technics is used for
Oxygen, reaction temperature is 40 degree to 250 degree, and oxygen flow is 10sccm to 1000sccm.
Figure 11 is refer to, covering first area I side walls film, first grid structure 110, second grid structure 120, side is formed
Second ARC 107 of wall and Semiconductor substrate 100.
Top of the top of second ARC 107 higher than first grid structure 110 or second grid structure 120
Portion.
Formation process, material and the effect of second ARC 107 are referring to provided in an embodiment of the present invention first
ARC 104（It refer to Fig. 5）Formation process, material and effect, will not be repeated here.
Figure 12 is refer to, the second photoresist layer is formed on the surface of the second ARC 107 of the second area II
108。
The forming process of second photoresist layer 108 is referring to the first photoresist layer 105（It refer to Fig. 6）Formation
Journey, will not be repeated here.
Figure 13 is refer to, is mask with second photoresist layer 108, etching removes first area I the second antireflection
Coating 107.
The technique that the etching removes first area I the second ARC 107 removes second referring to present invention etching
Region II the first ARC 104（It refer to Fig. 7）Technique, will not be repeated here.
It should be noted that having side between first area I the second ARC 107 and Semiconductor substrate 100
Wall film, specifically, the side wall film is the sandwich construction of silicon oxide layer 102 and silicon nitride layer 103.Removing first area I's
During second ARC 107, the side wall film can protect first area I Semiconductor substrates 100 not to be destroyed.Cause
This, removes after the second ARC 107, and first area I Semiconductor substrates 100 still have smooth surface, after being conducive to
Continuous formed contacts close metal silicide with the surface of Semiconductor substrate 100, so that the contact resistance of semiconductor devices is reduced, it is excellent
Change the electric property of semiconductor devices.
Figure 14 is refer to, is mask with second photoresist layer 108, first area I side wall film is etched back to, first
The both sides of grid structure 110 form side wall.
In the present embodiment, the side wall of formation is monox lateral wall 142 and the sandwich construction of silicon nitride spacer 143.
The formation process of the side wall of the both sides of first grid structure 110 is referring to the both sides of second grid structure 120 of the present invention
Side wall formation process, will not be repeated here.
Figure 15 is refer to, is mask with second photoresist layer 108, half in the both sides of first grid structure 110
The second doped region 109 is formed in conductor substrate 100.
Second doped region 109 is lightly doped district or heavily doped region.
The present embodiment illustrates that the side wall is to form heavily doped with second doped region 109 for presenting a demonstration property of heavily doped region
The master wall in miscellaneous area.
As one embodiment, using ion implantation technology the side wall both sides first area I Semiconductor substrates 100
The second doped region 109 of interior formation.
The present embodiment illustrates the doping of second doped region 109 by presenting a demonstration property of NMOS area of the first area I
Type is n-type doping.As one embodiment, the concrete technology of second doped region 109 is formed using ion implantation technology
Parameter is：The n-type doping ion is arsenic or antimony, and the energy of ion implanting is 1kev to 40kev, and ion implantation dosage is
1E14atom/cm2To 5E18atom/cm2。
In other embodiments of the present invention, second doped region is lightly doped district, then the side wall is lightly doped to be formed
The offset side wall in area；It is follow-up to form master wall in offset side wall both sides, using institute's master wall as mask, in first grid structure both sides
Semiconductor substrate in formed heavily doped region.
Figure 16 is refer to, second photoresist layer 108 is removed（It refer to Figure 15）With second area II the second anti-reflective
Penetrate coating 107（It refer to Figure 15）.
The technique for removing the second photoresist layer 108 and second area II the second ARC 107 refer to the present invention
Remove the first photoresist layer 105（It refer to Fig. 9）With first area I the first ARC 104（It refer to Fig. 9）Work
Skill, will not be repeated here.
In the present embodiment, second doped region 109 and first doped region 106 are heavily doped region, the first grid
The side wall of the both sides of pole structure 110 and the side wall of the both sides of second grid structure 120 are the master wall to form heavily doped region.
In other embodiments of the present invention, doped region and the second area are partly led in the first area Semiconductor substrate
Doped region is lightly doped district and heavily doped region in body substrate.Formed heavily doped region before, in first area Semiconductor substrate and
Lightly doped district is formed in second area Semiconductor substrate, the forming step of the lightly doped district refers to the present embodiment Fig. 4 to figure
16 forming step provided, will not be repeated here.
Follow-up technique also includes：The Semiconductor substrate is made annealing treatment；In the first grid structure both sides
Semiconductor substrate surface the first metal silicide of formation, the semiconductor substrate surface in the second grid structure both sides formed
Second metal silicide.
To sum up, the technical scheme that the present invention is provided has advantages below：
First, in the present embodiment, ARC is formd in photoresist layer bottom, the ARC stops light
Reflection, so that photoresist layer uniform exposure, forms the accurate photoresist layer of figure, improves the accuracy of technique, it is to avoid hair
Raw process deviation.
Secondly, in the present embodiment, side wall film is formed between Semiconductor substrate and ARC, the side wall film is protected
The technique that shield Semiconductor substrate is not etched removal ARC is destroyed, it is to avoid damage is caused to Semiconductor substrate, is improved
The flatness of semiconductor substrate surface；It is follow-up in semiconductor substrate surface formation metal silicide, the metal silicide with
Semiconductor substrate surface interfacial state is good, is conducive to reducing the contact resistance of semiconductor devices, so as to improve semiconductor devices
Driveability.
Again, in the present embodiment, side wall is formed after being etched back to the side wall film；The side wall is to remove antireflection in etching
Formed after coating, it is to avoid side wall is influenceed by etching technics；Therefore, the width of the side wall formed in the present embodiment compared with
Greatly, the side wall can effectively stop that easy diffusion ion diffuses to undesirable region in the metal silicide being subsequently formed, from
And improve the reliability of semiconductor devices；And because the width of the side wall of formation is larger, distance between the doped region being subsequently formed
Farther out, prevent from interpenetrating between adjacent doped region, further the electric property of optimization semiconductor devices.
Finally, the present embodiment employs excellent technique and removes photoresist layer and remaining ARC, specifically, adopting
The photoresist layer and remaining ARC are removed with cineration technics, damage of the technique to Semiconductor substrate is further reduced
Wound, improves the flatness of Semiconductor substrate, improves the reliability of semiconductor devices.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (13)
1. a kind of forming method of semiconductor devices, it is characterised in that including：
Semiconductor substrate is provided, the Semiconductor substrate includes first area and second area, the first area semiconductor lining
Basal surface has first grid structure, and the second area semiconductor substrate surface has second grid structure；
Side wall film is formed, the side wall film covers the upper table of the first grid structure, second grid structure and Semiconductor substrate
Face；
The ARC of the covering side wall film is formed, the top of the ARC is higher than first grid structure or second
The top of grid structure；
Anti-reflective coating layer surface formation photoresist layer in the first area；
After side wall film is formed, using the photoresist layer as mask, etched using dry etch process and remove second area
ARC；
After the ARC that etching removes second area, using the photoresist layer as mask, second area is etched back to
Side wall film, in second area semiconductor substrate surface formation side wall, and the side wall is located at second grid structure both sides.
2. the forming method of semiconductor devices according to claim 1, it is characterised in that the side wall film is single layer structure
Or sandwich construction.
3. the forming method of semiconductor devices according to claim 2, it is characterised in that the side wall film is single layer structure
When, the side wall film is silicon nitride layer or silicon oxide layer；When the side wall film is sandwich construction, the side wall film is silicon oxide layer
With the sandwich construction of silicon nitride layer.
4. the forming method of semiconductor devices according to claim 1, it is characterised in that use anisotropic etch process
It is etched back to the side wall film of second area.
5. the forming method of semiconductor devices according to claim 1, it is characterised in that form described using spin coating proceeding
ARC.
6. the forming method of semiconductor devices according to claim 1, it is characterised in that the thickness of the ARC
For 100 angstroms to 2000 angstroms.
7. the forming method of semiconductor devices according to claim 1, it is characterised in that the anti-reflective in the first area
Penetrate coating surface formation photoresist layer forming step be：Form the initial lithographic glue-line of covering ARC；Pass through exposure
Developing process, removes the initial lithographic glue-line of the anti-reflective coating layer surface positioned at second area, the anti-reflective in the first area
Penetrate coating surface formation photoresist layer.
8. the forming method of semiconductor devices according to claim 1, it is characterised in that the dry etch process is anti-
Answer ion etching.
9. the forming method of semiconductor devices according to claim 1, it is characterised in that the ARC is organic
ARC.
10. the forming method of semiconductor devices according to claim 9, it is characterised in that also including step：With the light
Photoresist layer is mask, and doped region is formed in the Semiconductor substrate of the second grid structure both sides；Remove the photoresist layer
With the ARC of first area.
11. the forming method of semiconductor devices according to claim 10, it is characterised in that light is removed using cineration technics
Photoresist layer and the ARC of first area.
12. the forming method of semiconductor devices according to claim 10, it is characterised in that the doped region is to be lightly doped
Area or heavily doped region.
13. the forming method of semiconductor devices according to claim 12, it is characterised in that use ion implantation technology shape
Into the doped region.
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| CN107785421A (en) * | 2016-08-29 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108597991B (en) * | 2018-05-11 | 2021-08-10 | 上海华力集成电路制造有限公司 | Photoresist back etching process |
| CN118136500B (en) * | 2024-05-07 | 2024-07-23 | 合肥晶合集成电路股份有限公司 | Method for preparing semiconductor structure |
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| US6074905A (en) * | 1998-12-28 | 2000-06-13 | Taiwan Semiconductor Manufacturing Company | Formation of a thin oxide protection layer at poly sidewall and area surface |
| US6506653B1 (en) * | 2000-03-13 | 2003-01-14 | International Business Machines Corporation | Method using disposable and permanent films for diffusion and implant doping |
| KR20040056435A (en) * | 2002-12-23 | 2004-07-01 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| CN102789983B (en) * | 2011-05-16 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of transistor |
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