CN104485280A - 栅极的制作方法 - Google Patents
栅极的制作方法 Download PDFInfo
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- CN104485280A CN104485280A CN201410853051.9A CN201410853051A CN104485280A CN 104485280 A CN104485280 A CN 104485280A CN 201410853051 A CN201410853051 A CN 201410853051A CN 104485280 A CN104485280 A CN 104485280A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 238000001259 photo etching Methods 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 abstract 1
- 230000008961 swelling Effects 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了一种栅极的制作方法，包括步骤：1)按照常规方法在衬底上依次淀积多晶硅、第一层WSi、第一层SiO2、第二层WSi、第二层SiO2；2)第一次光刻刻蚀，在场氧区形成MIP电容；3)第二次光刻刻蚀，在有源区形成栅极；4)通入N2进行热退火；5)淀积栅极侧墙SiO2。本发明通过在侧墙二氧化硅淀积前加入一步氮气退火步骤，修复栅极表面受损的钨化硅，避免了侧墙二氧化硅淀积时，WSi被氧化为WOx，从而解决了栅极侧墙鼓包的问题。
Description
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及栅极的制作工艺。
背景技术
在半导体制造过程中，栅极表面WSi(硅化钨)如果前期被刻蚀，后续侧墙二氧化硅淀积后会产生鼓包，影响HCI(hot carrier injection，热载流子注入效应)，特别对OTP(一次性可编程)器件的编程能力不利。例如，参见图1所示，在MIP电容刻蚀过程中，多晶硅表面的WSi受到损伤，多晶硅表面WSi的结合键遭到破坏，导致后续侧墙SiO2淀积时，WSi被氧化，生成WOx(钨氧化物)鼓包，如图2所示，WOx鼓包使侧墙变大，如图3所示，影响HCI，导致OTP失效(参见图4)。
发明内容
本发明要解决的技术问题是提供一种栅极的制作方法，它可以避免栅极侧墙产生鼓包。
为解决上述技术问题，本发明的栅极的制作方法，步骤包括：
1)按照常规方法在衬底上依次淀积多晶硅、第一层WSi、第一层SiO2、第二层WSi、第二层SiO2；
2)第一次光刻刻蚀，在场氧区形成MIP电容；
3)第二次光刻刻蚀，在有源区形成栅极；
4)通入N2进行热退火；
5)淀积栅极侧墙SiO2。
上述热退火的温度为700～800℃，氮气的流量为大于或等于25L/min。
本发明通过在侧墙二氧化硅淀积前加入一步氮气退火步骤，修复栅极表面受损的钨化硅，这样，在淀积侧墙二氧化硅时，WSi就不会被氧化为WOx，从而避免了WOx鼓包的形成。
附图说明
图1是制作栅极过程中，MIP电容的刻蚀过程示意图。
图2是多晶硅表面的WSi在MIP电容刻蚀时受到损伤，后续侧墙SiO2淀积时，WSi被氧化为WOx而形成鼓包。
图3是WOx鼓包导致SiO2侧墙变大。其中，a图是没有WOx鼓包情况下的侧墙尺寸，b图是有WOx鼓包情况下的侧墙尺寸。
图4是有WOx鼓包情况下的CP(Circuit Probing，晶圆测试)图。
图5是N2流量为20L/min时，仍有少量鼓包。
图6是N2流量加大至25L/min后，无鼓包出现。
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合附图，详述如下：
本实施例的CMOS(互补金属氧化物半导体)栅极的制作方法，具体包括以下工艺步骤：
步骤1，按照常规方法在衬底上依次淀积多晶硅、第一层WSi、第一层SiO2、第二层WSi、第二层SiO2。
步骤2，第一次光刻刻蚀，在场氧区形成MIP电容。
步骤3，第二次光刻刻蚀，在有源区形成栅极。
以上步骤1～步骤3可参见图1所示。
步骤4，通入N2进行热退火，以修复第一层WSi。
热退火的温度为700～800℃。
热退火时，氮气的流量需要大于或等于25L/min，以防止空气卷入(如果有空气卷入，空气会与表面被刻蚀过的WSi反应生成鼓包，从图5中可以看到，当N2流量为20L/min时，仍有少量鼓包)。
步骤5，淀积栅极侧墙SiO2。
增加氮气退火步骤后，栅极表面受损的钨化硅得到了修复，后续侧墙二氧化硅淀积时，就没有出现WOx鼓包了，如图6所示。
Claims (3)
1.栅极的制作方法，其特征在于，步骤包括：
1)按照常规方法在衬底上依次淀积多晶硅、第一层WSi、第一层SiO2、第二层WSi、第二层SiO2；
2)第一次光刻刻蚀，在场氧区形成MIP电容；
3)第二次光刻刻蚀，在有源区形成栅极；
4)通入N2进行热退火；
5)淀积栅极侧墙SiO2。
2.根据权利要求1所述的方法，其特征在于，步骤4)，热退火的温度为700～800℃。
3.根据权利要求1所述的方法，其特征在于，步骤4)，氮气的流量为大于或等于25L/min。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853051.9A CN104485280A (zh) | 2014-12-31 | 2014-12-31 | 栅极的制作方法 |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410853051.9A CN104485280A (zh) | 2014-12-31 | 2014-12-31 | 栅极的制作方法 |
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| Publication Number | Publication Date |
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| CN104485280A true CN104485280A (zh) | 2015-04-01 |
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| CN201410853051.9A Pending CN104485280A (zh) | 2014-12-31 | 2014-12-31 | 栅极的制作方法 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
| US5946599A (en) * | 1997-07-24 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor IC device |
| CN101853811A (zh) * | 2009-04-03 | 2010-10-06 | 世界先进积体电路股份有限公司 | 半导体装置的制造方法 |
| CN103730344A (zh) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | 形成金属硅化钨栅极的氧化硅侧墙的方法 |
-
2014
- 2014-12-31 CN CN201410853051.9A patent/CN104485280A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5756392A (en) * | 1997-01-22 | 1998-05-26 | Taiwan Semiconductor Manuacturing Company, Ltd. | Method of formation of polycide in a semiconductor IC device |
| US5946599A (en) * | 1997-07-24 | 1999-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing a semiconductor IC device |
| CN101853811A (zh) * | 2009-04-03 | 2010-10-06 | 世界先进积体电路股份有限公司 | 半导体装置的制造方法 |
| CN103730344A (zh) * | 2012-10-12 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | 形成金属硅化钨栅极的氧化硅侧墙的方法 |
Non-Patent Citations (1)
| Title |
|---|
| 董颖: "硅化钨MIP电容侧墙淀积工艺优化", 《微电子学》 * |
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