CN104467857B - Gradually-appoximant analog-digital converter system - Google Patents

Abstract

The present invention provides a successive approximation analog-to-digital converter system. In this successive approximation analog-to-digital converter system, the array of analog-to-digital converters is designed in groups, and the estimation method of the chain loop is used, which can eliminate the capacitance mismatch of the single-channel SAR ADC itself, the gain mismatch between the SAR ADC arrays and Non-linearity introduced by non-ideal factors such as offset voltage mismatch can quickly and efficiently complete the calibration of the analog-to-digital converter array, greatly reducing design complexity and power consumption.

Description

Successive Approximation Analog-to-Digital Converter System

technical field

The invention relates to the technical field of electronic components in the electronics industry, in particular to a successive approximation analog-to-digital converter (SAR ADC) system.

Background technique

The analog-to-digital converter is the interface circuit between the analog circuit and the digital circuit in the signal processing process. Among them, SAR ADC is a very popular structure in recent years because it is suitable for process size reduction and has a simple structure. It is therefore widely used in medium precision array sensors.

In array ADCs, however, mismatches lead to severe nonlinearities. In addition to the nonlinearity of the single-channel ADC itself caused by capacitance mismatch, gain mismatch between channels, offset voltage mismatch, etc., further limit the linearity of the array ADC.

In recent years, the introduction of redundancy concepts and LMS filters has provided new ideas for calibrating SARADCs. With the support of corresponding auxiliary circuits, these techniques have been applied in the calibration of single-channel and time-interleaved SAR ADCs.

Contents of the invention

(1) Technical problems to be solved

In view of the above-mentioned technical problems, the present invention provides a successive approximation analog-to-digital converter system to eliminate the capacitance mismatch of the single-channel SAR ADC itself, and the introduction of non-ideal factors such as gain mismatch and offset voltage mismatch between SAR ADC arrays of non-linearity.

(2) Technical solution

The successive approximation analog-to-digital converter system of the present invention includes: a register unit for storing a mismatch parameter matrix, wherein the mismatch parameter matrix is a 2×Z matrix; a successive approximation analog-to-digital converter array, which includes 2Z modulus Converters, the 2Z analog-to-digital converters are divided into two groups - group M and group N, each group contains Z analog-to-digital converters, wherein, two adjacent analog-to-digital converters belong to different groups, and the same group The analog-to-digital converters use the same capacitor design, and different groups of analog-to-digital converters use different capacitor designs. In one signal period, each ADC in the successive approximation ADC array respectively performs a Preliminary quantization is performed to obtain a 0-1 code vector; and an LMS filter bank is connected to the successive approximation analog-to-digital converter array and the register unit, which performs the following operations during the signal period, and the mismatch parameters in the register Each element of the matrix is updated: sequentially receive the 0-1 code vectors output by two adjacent analog-to-digital converters belonging to different groups, and complete the estimation of the parameter vectors corresponding to the two analog-to-digital converters in the mismatch parameter matrix. After the signal period is completed, an estimation and update of the mismatch parameter matrix is completed. Wherein, the analog-to-digital converters in the successive-approximation analog-to-digital converter array are all successive-approximation analog-to-digital converters.

(3) Beneficial effects

In the successive approximation analog-to-digital converter system of the present invention, the array of analog-to-digital converters is designed in groups, and the estimation method of chain loop is adopted, which can quickly and efficiently complete the calibration of the array of analog-to-digital converters, greatly reducing the design complexity and reducing the power consumption.

Description of drawings

FIG. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an analog-to-digital converter in the analog-to-digital converter array in the successive approximation analog-to-digital converter system of the present embodiment;

FIG. 3 is a schematic diagram of mismatch parameter correction performed by an LMS filter bank in the successive approximation analog-to-digital converter system in FIG. 1;

FIG. 4 is a flow chart of mismatch parameter correction performed by the LMS filter.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be noted that, in the drawings or descriptions of the specification, similar or identical parts all use the same figure numbers. Implementations not shown or described in the accompanying drawings are forms known to those of ordinary skill in the art. Additionally, while illustrations of parameters including particular values may be provided herein, it should be understood that the parameters need not be exactly equal to the corresponding values, but rather may approximate the corresponding values within acceptable error margins or design constraints. The directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the protection scope of the present invention.

In the successive approximation analog-to-digital converter system of the present invention, the array of analog-to-digital converters is designed in groups, and the calibration of the array of analog-to-digital converters is performed by a chained cycle estimation method. Specifically:

(1) The capacitor array in the ADC in the ADC array: C=(C _MSB , C _MSB-1 , ...... C ₂ , C ₁ , C ₀ ) satisfy the following conditions:

1. For i ∈ {1, 2, ..., MSB-1, MSB}, satisfy

2,

3. MSB>log ₂ c

Among them, Equation 1 is a sufficient condition for the analog-to-digital converter to have good differential nonlinearity (DNL). C _i represents the capacitance value of the i-th capacitor, and c is the total area (size) of the capacitor, which is given in combination with system noise and other indicators during design.

Theoretically, there are different solutions to the capacitor array C based on the constraints of Equation 1, Equation 2, and Equation 3, and the capacitor array designed based on each solution has the same resolution.

The grouping design of the AD converter array means that in the AD converter array, the capacitor arrays of the same group of AD converters adopt the same C design, and different groups adopt different C designs.

(2) Calibration of the AD converter array using the chained loop estimation method means: the output results of the same input signal are sampled and quantized by different groups of AD converters, input into the LMS (least mean square) filter bank, and the chain The formula cyclically estimates the mismatch parameters of the analog-to-digital converter array; when the mismatch parameters converge to a certain accuracy, the calibration ends.

The following uses a plurality of embodiments to describe the successive approximation analog-to-digital converter system of the present invention in detail.

In an exemplary embodiment of the present invention, a successive approximation analog-to-digital converter system is provided. FIG. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter system according to an embodiment of the present invention. As shown in FIG. 1 , the successive approximation analog-to-digital converter system of this embodiment includes: a register unit, a successive approximation analog-to-digital converter (SARADC) array, an LMS filter bank, an output circuit, and a control module.

Each component of the successive approximation analog-to-digital converter system of this embodiment will be described in detail below.

Please refer to Figure 1, the successive approximation analog-to-digital converter (SAR ADC) array, which includes 4 analog-to-digital converters, the 4 analog-to-digital converters are divided into two groups - group M and group N, each group contains 2 analog-to-digital converter. The 4 ADCs are labeled as: ADC-M ₀ , ADC-N ₀ , ADC-M ₁ , ADC-N ₁ .

Wherein, the analog-to-digital converters in the same group adopt the same capacitor design, that is, adopt the same DAC design. In one signal period, each analog-to-digital converter in the successive approximation analog-to-digital converter (SAR ADC) array performs preliminary quantization on the input analog signal to obtain a 0-1 code vector.

FIG. 2 is a schematic diagram of an ADC in the ADC array in the SAC system of the present embodiment. As shown in Figure 2, the ADC includes:

The DAC capacitor sequence is used as a sample-and-hold circuit to sample the analog signal in the sampling stage of the ADC, and provides a suitable reference level in the successive approximation stage to complete the quantization of the analog signal;

A switch network that controls the progression of the successive approximation process by controlling how capacitors are connected in the DAC capacitor train;

A comparator, connected to the back end of the DAC capacitor array, is used to complete each comparison and obtain a binary output result ("0" or "1");

The output control circuit is used to control the analog-to-digital converter to work orderly and accurately.

Please refer to FIG. 2 , set MSB=6. As mentioned above, for group M and group N, the analog-to-digital converters of the same group adopt the same capacitor design, and the analog-to-digital converters of different groups adopt different capacitor designs.

For each ADC in group M, it includes 7 capacitors. In the case of taking the LSB bit capacitor as the unit capacitor, the vector composed of the capacitance values of the seven capacitors is:

C _M = (11, 7, 7, 3, 2, 1, 1) = (10+1, 7, 6+1, 3, 2, 1, 1)

For each ADC in group N, it includes 7 capacitors. In the case of taking the LSB bit capacitor as the unit capacitor, the vector composed of the capacitance values of the seven capacitors is:

C _N = (10, 8, 6, 4, 2, 1, 1) = (10, 7+1, 6, 3+1, 2, 1, 1)

It should be noted that only a specific capacitor combination is given here, and those skilled in the art can also choose other capacitor combinations that satisfy the formula 1-3 according to the actual situation, and should not be limited to this embodiment The seven capacitors in the capacitor can also realize the present invention, and will not be described in detail here.

In addition, it is assumed that the capacitance value in the process satisfies a normal distribution, and the standard deviation is 10% of the LSB capacitance value, and the distribution of other capacitances satisfy the central limit theorem.

As shown in Figure 1, the same input test signal is quantized by a 2×2 array of SAR ADCs (ADC-M ₀ , ADC-N ₀ , ADC-M ₁ , ADC-N ₁ ), and each ADC gets its corresponding The 6-dimensional output 0-1 code vector. 6-dimensional 0-1 code vectors obtained by the four analog-to-digital converters-D _M0 , D _N0 , D _M1 , D _N1 . Considering the existence of offset voltage, the successive approximation analog-to-digital converter array adds one dimension at the end of each vector, and the assignment value is 1 (the offset voltage always exists), represented by D' _M0 , D' _N0 , D' _M1 , D' _N1 . Gain mismatch has no effect on the parameter matrix expression.

The register unit is used to store the mismatch parameter matrix. In this embodiment, the AD converter array includes 4 AD converters, the 4 AD converters are divided into two groups - group M and group N, and each group contains 2 analog-to-digital converters. Correspondingly, the mismatch parameter matrix stored in the register is a 2×2 matrix: in:

W _Mi ＝(g _Mi *C _M e _Mi ，V _OSMi )

W _Ni ＝(g _Ni *C _N e _Ni ，V _OSNi )

Wherein, g _Mi and g _Ni are gain parameters, V _OSMi and V _OSNi are offset voltage parameters, e _Mi and e _Ni are diagonal matrices formed by mismatch parameters of capacitor arrays, i=0,1.

It should be noted that, in this embodiment, the register and the LMS filter bank are set separately. But in some cases, there are registers built into the LMS filter bank. In this case, the mismatch parameter matrix will be stored in the built-in register of the LMS filter bank, which should also be within the protection scope of the present invention.

Referring to Fig. 1, the LMS filter bank is connected to the successive approximation analog-to-digital converter array and the register unit, and it performs the following operations in the signal cycle to update each element of the mismatch parameter matrix in the register: Receive the 0-1 code vectors output by two adjacent analog-to-digital converters belonging to different groups, complete the estimation of the parameter vectors corresponding to the two analog-to-digital converters in the mismatch parameter matrix, and complete the An Estimation and Update of the Mismatch Parameter Matrix

FIG. 3 is a schematic diagram of mismatch parameter correction performed by an LMS filter bank in the successive approximation analog-to-digital converter system in FIG. 1 . Referring to Figure 3, on the basis of grouping the 4 ADCs in the ADC array, the LMS filter bank performs the following operations to update each element of the mismatch parameter matrix in the register:

Step A: Use the 7-dimensional vectors D' _M0 and D' _N0 output by the analog-to-digital converters ADC-M ₀ and ADC-N ₀ to complete the parameters (W _M0 , W _N0 ) corresponding to the first two analog-to-digital converters estimates and updates;

FIG. 4 is a flow chart of mismatch parameter correction performed by the LMS filter. As shown in Figure 4, the basic process of estimating parameters (W _M0 , W _N0 ) includes:

Sub-step A1: Calculate the error function e=D' _M0 ·W _M0 -D' _N0 ·W _N0 ;

Sub-step A2: Update the parameter vector stored in the register:

W _M0 ＝W _M0 -u·e·(D' _M0 -D' _N0 )

W _N0 ＝W _N0 + u·e·(D' _M0 -D' _N0 )

Among them, u is the learning rate parameter. According to the accuracy of the analog-to-digital converter, the convergence speed and convergence accuracy of the calibration process are chosen as a compromise, and generally take a value between 0.001 and 0.1. The estimation process is a general LMS filter bank, which will not be expanded in detail here.

Step B: Use the 7-dimensional vectors D' _N0 and D' _M1 output by the ADC-N ₀ and ADC-M ₁ to complete the estimation of the corresponding parameters (W _N0 , W _M1 ) of the two ADCs and update;

Wherein, the parameters W _N0 and W _M1 are consistent with the relevant sub-steps in step A, and will not be repeated here.

Step C: use the 7-dimensional vectors D' _M1 , D' _N1 output by the analog-to-digital converters ADC-M ₁ and ADC-N ₁ to complete the estimation and calculation of the parameters (W _M1 , W _N1 ) of the two analog-to-digital converters renew;

Wherein, the parameters W _M1 and W _N1 are consistent with the relevant sub-steps in step A, and will not be repeated here.

Step D: use the 7-dimensional vectors D' _N1 and D' _M0 output by the analog-to-digital converters ADC-N ₁ and ADC-M ₀ to complete the estimation and calculation of the parameters (W _N1 , W _M0 ) of the two analog-to-digital converters renew.

Wherein, the parameters W _N1 and W _M0 are consistent with the relevant sub-steps in step A, and will not be repeated here.

So far, the estimation and update of the parameter vector of the first signal cycle are completed.

Change the input signal, in the next signal cycle, repeat the above estimation process until the parameter matrix Converge to the accuracy required by the design.

It should be noted that the calibration of the parameter matrix requires certain convergence conditions. A sufficient condition is that if multiple sets of binary codes input during multiple iterations of the LMS filter form a matrix, then the rank of the matrix must be equal to the number of unknown parameter vectors in the mismatch parameter matrix to be calibrated.

The output circuit and the control module are connected to the back end of the LMS filter bank, and are used to control the SARADC array and the LMS filter bank to work orderly and accurately, and output the final digital signal of the successive approximation analog-to-digital converter system: (W _M0 · D' _M0 , W _N0 D" _N0 , W _M1 D' _M1 , W _N1 D' _N1 ).

In actual work, the update of the parameter matrix is independent of the output process of the whole successive approximation analog-to-digital converter array. Those skilled in the art are well aware of the relevant process, and will not be described in detail here.

It should be noted that the LMS filter in the prior art is often used to realize the calibration of a system containing only two sets of parameter vectors. However, in this embodiment, through the group design of the SAR ADC array and the parameter calibration in a chained loop mode, the first is to greatly reduce the convergence condition, and the second is to ensure that the local convergence of the parameter calibration is achieved by the LMS filter bank. global convergence.

In this embodiment, the A/D converter array includes 4 A/D converters, and the 4 A/D converters are divided into two groups—group M and group N, but the present invention is not limited thereto.

In other embodiments of the present invention, the array of analog-to-digital converters may include 2Z analog-to-digital converters, where Z is an integer. The 2Z analog-to-digital converters can also be divided into two groups—group M and group N, and two adjacent analog-to-digital converters belong to different groups. The mismatch parameter matrix stored in the register is a 2×Z matrix.

In this case, the LMS filter bank performs the following operations during one signal cycle, updating each element of the _mismatch parameter matrix in the register _: At the beginning, the 7-dimensional 0-1 code vectors output by two adjacent analog-to-digital converters are input into the LMS filter in turn to complete the estimation and update of the parameters of the two analog-to-digital converters, wherein the analog-to-digital converters ADC-N _Z and The analog-to-digital converter ADC-M ₀ is considered as an adjacent analog-to-digital converter. After the preset period is executed, the estimation and updating of the mismatch parameter matrix is completed.

So far, the present embodiment has been described in detail with reference to the drawings. Based on the above description, those skilled in the art should have a clear understanding of the SAC system of the present invention.

In summary, in the successive approximation analog-to-digital converter system of the present invention, the array of analog-to-digital converters is designed in groups, and the estimation method of chain loop is adopted, which can quickly and efficiently complete the calibration of the array of analog-to-digital converters, greatly reducing the Design complexity and reduced power consumption.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A successive approximation analog-to-digital converter system, characterized in that, comprising: A register unit, configured to store a mismatch parameter matrix, where the mismatch parameter matrix is a 2×Z matrix; A successive approximation analog-to-digital converter array comprising 2Z analog-to-digital converters divided into two groups - group M and group N, each group containing Z analog-to-digital converters, wherein adjacent The two A/D converters belong to different groups. The A/D converters in the same group use the same capacitor design, and the A/D converters in different groups use different capacitor designs. In one signal cycle, the successive approximation A/D converter Each analog-to-digital converter in the array performs preliminary quantization on the input analog signal to obtain a 0-1 code vector; and The LMS filter bank is connected to the successive approximation analog-to-digital converter array and the register unit, and it performs the following operations in the signal cycle to update each element of the mismatch parameter matrix in the register: receive two adjacent The 0-1 code vectors output by the analog-to-digital converters belonging to different groups complete the estimation of the parameter vectors corresponding to the two analog-to-digital converters in the mismatch parameter matrix, and complete the mismatch parameter after executing the signal cycle An estimation and update of the matrix; Wherein, the analog-to-digital converters in the successive approximation analog-to-digital converter array are all successive approximation analog-to-digital converters; Wherein, the 2Z analog-to-digital converters in the successive approximation analog-to-digital converter array are: ADC-M ₀ , ADC-N ₀ , ..., ADC-M _i , ADC-N _i , ..., ADC- M _z-1 , ADC-N _z-1 ; ADC-M _i , ADC-N _i are respectively the i-th analog-to-digital converter in the successive approximation analog-to-digital converter array group M and group N; the ADC-N _z-1 and ADC-M ₀ are regarded as adjacent analog-to-digital converters; Wherein, the analog-to-digital converter outputs a 0-1 code vector of the MSB dimension; the successive approximation analog-to-digital converter array adds one dimension at the end of the 0-1 code vector of the MSB dimension, and assigns a value of 1, and The 0-1 code vector of the MSB+1 dimension is input to the LMS filter bank; Wherein, the LMS filter bank sequentially receives the 0-1 code vectors output by two adjacent analog-to-digital converters belonging to different groups, and completes the parameter vector corresponding to the two analog-to-digital converters in the mismatch parameter matrix in the following manner estimate: Sub-step A1: Calculate the error function e=D' _Mp ·W _Mp -D' _Nq ·W _Nq ; Sub-step A2: Update the parameter vector stored in the register: W _Mp ＝W _Mp -u·e·(D' _Mp -D' _Nq ) W _Nq ＝W _Nq + u·e·(D' _Mp -D' _Nq ) Among them, D' _Mp is the MSB+1-dimensional 0-1 code vector corresponding to the p-th analog-to-digital converter-ADC-M _p in group M, and W _Mp is the parameter vector corresponding to ADC-M _p in the mismatch parameter matrix ; D' _Nq is the MSB+1-dimensional 0-1 code vector corresponding to the qth analog-to-digital converter-ADC-N _q in the group N, and W _Nq is the parameter vector corresponding to the ADC-N _q in the mismatch parameter matrix; u is the learning rate parameter; p=q or |pq|=1. 2. The successive approximation analog-to-digital converter system according to claim 1, wherein each analog-to-digital converter in the successive analog-to-digital converter array is an analog-to-digital converter of MSB dimension, which includes a DAC Capacitance sequence C=(C _MSB , C _MSB-1 ,...C ₂ , C ₁ , C ₀ ), the DAC capacitance sequence C satisfies the following conditions: ①For i∈{1,2,...,MSB-1,MSB}, satisfy ② ③MSB>log ₂ c; Among them, C _i represents the capacitance value of the i-th capacitor in the DAC capacitance sequence C, c is the total area of the capacitor, the analog-to-digital converters of the same group correspond to a solution that satisfies the above conditions, and the analog-to-digital converters of different groups correspond to the above conditions different solutions. 3. The successive approximation analog-to-digital converter system according to claim 2, wherein, for each analog-to-digital converter in the array of successive analog-to-digital converters, it further comprises: A switch network that controls the progression of the successive approximation process by controlling how capacitors are connected in the DAC capacitor train; A comparator, connected to the back end of the DAC capacitor array, is used to complete each comparison and obtain a binary output result; The output control circuit is used to control the analog-to-digital converter to work orderly and accurately. 4. The successive approximation analog-to-digital converter system according to claim 1, wherein the learning rate parameter u is between 0.001-0.1. 5. The successive approximation analog-to-digital converter system according to claim 1, wherein, through K signal periods, the convergence of the mismatch parameter matrix is realized, wherein each signal period corresponds to an input analog signal, so Said K≥20. 6. The successive approximation analog-to-digital converter system according to any one of claims 1 to 5, further comprising: The output circuit and control module are connected to the back end of the LMS filter bank, and are used to control the SAR ADC array and the LMS filter bank to work orderly and accurately, and output the final digital signal of the successive approximation analog-to-digital converter system. 7. The successive-approximation analog-to-digital converter system according to any one of claims 1 to 5, wherein the register unit is set independently, or arranged in the successive-approximation analog-to-digital converter array or LMS filter group.