CN104465352A - Method for removing polycrystalline silicon residues in polycrystalline silicon etching process - Google Patents
Method for removing polycrystalline silicon residues in polycrystalline silicon etching process Download PDFInfo
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- CN104465352A CN104465352A CN201410714842.3A CN201410714842A CN104465352A CN 104465352 A CN104465352 A CN 104465352A CN 201410714842 A CN201410714842 A CN 201410714842A CN 104465352 A CN104465352 A CN 104465352A
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- polycrystalline silicon
- time
- etching
- thickness
- reflection layer
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 86
- 238000005530 etching Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 28
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 238000004886 process control Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 230000003287 optical effect Effects 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 230000003595 spectral effect Effects 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000003607 modifier Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for removing polycrystalline silicon residues in the polycrystalline silicon etching process, and relates to the field of micro-electronics. The method includes the steps that an optical line width measuring instrument is used for measuring the thickness H1 of an original bottom anti-reflection layer in a polycrystalline silicon gate, and first-time etching time is set; first-time etching is conducted on the polycrystalline silicon gate according to the set first-time etching time, and the first-time etching thickness H2 is acquired; in accordance with the thickness H1 of the original bottom anti-reflection layer and the first-time etching thickness H2, a manufacturing procedure control system is used for monitoring, and second-time etching is conducted on the polycrystalline silicon gate. According to the method for removing the polycrystalline silicon residues in the polycrystalline silicon etching process, before the polycrystalline silicon gate is etched, the optical line width measuring instrument is used for measuring the thickness of the anti-reflection layer at the bottom of the polycrystalline silicon, the manufacturing procedure control system feeds back and corrects the etching time from time to time through the corresponding etching process parameter according to the thickness of the bottom anti-reflection layer so that the polycrystalline silicon gate of the polycrystalline silicon can be etched, the purpose of removing the polycrystalline silicon residues in the polycrystalline silicon etching process is achieved, and the yield of products is improved.
Description
Technical field
The present invention relates to microelectronic, particularly relate to a kind of method eliminating polycrystalline silicon residue.
Background technology
In 65 nanometers and following technology, service area and shallow plough groove isolation area have certain difference in height, owing to being subject to the impact of this difference in height, under identical etching condition, as shown in Figure 1, the polysilicon gate a photoetching bottom anti-reflective layer thickness be positioned at above substrate c has institute's difference.Under the condition of identical etching and cleaning, the silicon chip etching polysilicon gate that bottom anti-reflection layer is thicker has certain polycrystalline silicon residue b, affects overall performance.
The technological means used at present to eliminate polycrystalline silicon residue is: in the process of etching polysilicon bottom anti-reflection layer, observes the situation of spectral signal change in etching process, determines the time etched according to the variation tendency of spectral signal in etching process.But Problems existing has: spectral signal determination etch period has certain error, when complete by spectral signal determination bottom anti-reflection layer etching, in fact some bottom anti-reflection layer does not also etch complete.
Chinese patent (CN 101442001B) discloses a kind of method of etching polysilicon gate, the method comprised polysilicon deposition step, complete the step of polysilicon photoetching and complete the step of etching polysilicon; Described method also comprises the step of clean wafers back-side polysilicon, and this step completes the process of clean wafers back-side polysilicon.
This patent, by washing wafer back-side polysilicon, increases the tension stress of wafer, thus effectively can avoid formation, the raising wafer property of grid foot.But do not solve the problem of polycrystalline silicon residue in polycrystalline silicon etching process.
Chinese patent (CN 100383931C) discloses a kind of polycrystalline silicon gate grid etching process that can reduce particle in etching technics and produce, and comprises the following steps: stabilizing step 2 before BT step (hard mask etching step) front stabilizing step 1, BT step (hard mask etching step), main quarter step, main quarter step 1, main quarter step 2, cross step 1 and cross step 2 at quarter at quarter.
This patent has taken into account etching effect and Grain size controlling two aspects, cut off or maintain plasma according to different situations, BT step (hard mask etching step) to main quarter step transition can cut off plasma, and main quarter step to crossing the transition of carving step and crossing the stable build-up of luminance that the end of carving step needs maintain plasma.This invention can control the particle of reaction production effectively to the pollution of silicon chip, thus improves chip yield.But do not solve the problem of polycrystalline silicon residue in polycrystalline silicon etching process.
Summary of the invention
The present invention is the problem solving polycrystalline silicon residue in polycrystalline silicon etching process, thus provides the technical scheme of the method eliminating polycrystalline silicon residue in polycrystalline silicon etching process.
In elimination polycrystalline silicon etching process of the present invention, the method for polycrystalline silicon residue, comprises the steps:
Step 1. adopts optics live width measuring instrument to measure the thickness H1 of bottom anti-reflection layer original in polysilicon gate, and setting first time etch period;
Step 2. carries out first time etching according to the first time etch period of setting to described polysilicon gate, and obtains the thickness H2 of the first etching;
Step 3., according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer and first etching, adopts process control system to carry out monitoring and carry out second time to described polysilicon gate and etch.
Preferably, the detailed process adopting process control system to carry out monitoring to described polysilicon gate carries out second time etching in step 3 is:
Step 31. process control system obtains second time etch period according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer and first etching;
Step 32. carries out second time etching according to described second time etch period to described polysilicon gate.
Preferably, the detailed process obtaining second time etch period in step 31 is:
Secondary etch period Time is obtained according to formula (1):
Time＝(H1-H2)/ER (1)
Wherein, ER represents bottom anti-reflection layer etch rate.
Beneficial effect of the present invention:
The present invention, before etching polysilicon gate, adopts optics live width measuring instrument to measure polysilicon bottom anti-reflecting layer thickness; By the thickness of process control system for bottom anti-reflection layer, use corresponding etch process parameters, constantly feedback modifiers etch period, polysilicon polysilicon gate is etched, reach the object eliminating polycrystalline silicon residue in polycrystalline silicon etching process, improve the yield of product.
Accompanying drawing explanation
Fig. 1 is the structural representation of the polycrystalline silicon residue after existing etching polysilicon gate;
Fig. 2 is the method flow diagram of polycrystalline silicon residue in elimination polycrystalline silicon etching process of the present invention;
Fig. 3 is the schematic diagram adopting optics live width measuring instrument to measure bottom anti-reflection layer;
Fig. 4 is flow chart polysilicon gate being carried out to second time etching;
Fig. 5 adopts the present invention to the polysilicon gate schematic diagram obtained after etching polysilicon gate;
In accompanying drawing: a. polysilicon gate; B. polycrystalline silicon residue; C substrate; D. photoresistance; E. bottom anti-reflection layer; F. live width; H1. original bottom anti-reflective layer thickness.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
As shown in Figures 2 to 4, the invention provides the method eliminating polycrystalline silicon residue in polycrystalline silicon etching process, comprise the steps:
Step 1. adopts optics live width measuring instrument to measure the thickness H1 (as shown in Figure 3) of bottom anti-reflection layer e original in polysilicon gate a, and setting first time etch period, this first time etch period be shorter than the etch period of polysilicon gate under normal circumstances;
Step 2. carries out first time etching according to the first time etch period of setting to polysilicon gate a, and obtains the thickness H2 of the first etching;
Step 3. is according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer e and first etching, and adopt process control system to carry out monitoring and carry out second time to polysilicon gate a and etch, its detailed process is:
Step 31. process control system obtains second time etch period Time according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer e and first etching:
Secondary etch period Time is obtained according to formula (1):
Time＝(H1-H2)/ER (1)
Wherein, ER represents bottom anti-reflection layer etch rate;
Step 32. carries out second time etching according to second time etch period to polysilicon gate a, and the accurate control (etch period of every a slice is different) realizing every a slice silicon chip erosion time ensure that the regional of every a slice silicon chip is without polycrystalline silicon residue b (as shown in Figure 5).
While adopting optics live width measuring instrument to carry out measuring the live width f of photoresistance d above polysilicon gate a in the present embodiment, in same database, increase parameter to measure the thickness of polysilicon gate a photoetching bottom anti-reflection layer e, and adopt advanced process control system, for the bottom anti-reflective layer thickness that different silicon chip is different, use different etch process parameters respectively, feed back constantly, to eliminate the polycrystalline silicon residue b in polysilicon gate a etching technics.
The process control system that foregoing is mentioned has been widely used in the technique of etching polysilicon gate.It has the function of powerful automatic adjustment polysilicon live width, not only can make up the difference of front layer lithographic line width, and can also make up the difference of etching itself.The present invention applies to the etch period revising bottom anti-reflection layer by process control system.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (3)
1. eliminate the method for polycrystalline silicon residue in polycrystalline silicon etching process, it is characterized in that, comprise the steps:
Step 1. adopts optics live width measuring instrument to measure the thickness H1 of bottom anti-reflection layer original in polysilicon gate, and setting first time etch period;
Step 2. carries out first time etching according to the first time etch period of setting to described polysilicon gate, and obtains the thickness H2 of the first etching;
Step 3., according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer and first etching, adopts process control system to carry out monitoring and carry out second time to described polysilicon gate and etch.
2. eliminate the method for polycrystalline silicon residue in polycrystalline silicon etching process as claimed in claim 1, it is characterized in that, the detailed process adopting process control system to carry out monitoring to described polysilicon gate carries out second time etching in step 3 is:
Step 31. process control system obtains second time etch period according to the thickness H2 of the thickness H1 of original bottom anti-reflection layer and first etching;
Step 32. carries out second time etching according to described second time etch period to described polysilicon gate.
3. eliminate the method for polycrystalline silicon residue in polycrystalline silicon etching process as claimed in claim 2, it is characterized in that, the detailed process obtaining second time etch period in step 31 is:
Secondary etch period Time is obtained according to formula (1):
Time＝(H1-H2)/ER (1)
Wherein, ER represents bottom anti-reflection layer etch rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410714842.3A CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410714842.3A CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
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| Publication Number | Publication Date |
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| CN104465352A true CN104465352A (en) | 2015-03-25 |
| CN104465352B CN104465352B (en) | 2018-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410714842.3A Active CN104465352B (en) | 2014-11-28 | 2014-11-28 | The method for eliminating polycrystalline silicon residue in polycrystalline silicon etching process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109559986A (en) * | 2018-12-03 | 2019-04-02 | 上海华力微电子有限公司 | A kind of method of active area electric leakage in improvement etching polysilicon gate |
| CN112133631A (en) * | 2020-09-25 | 2020-12-25 | 上海华力微电子有限公司 | Method for improving stability of grid etching morphology and etching equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160621A (en) * | 1999-09-30 | 2000-12-12 | Lam Research Corporation | Method and apparatus for in-situ monitoring of plasma etch and deposition processes using a pulsed broadband light source |
| US6635573B2 (en) * | 2001-10-29 | 2003-10-21 | Applied Materials, Inc | Method of detecting an endpoint during etching of a material within a recess |
| CN1577786A (en) * | 2003-07-07 | 2005-02-09 | 应用材料有限公司 | Interferometric endpoint detection in a substrate etching process |
| CN1708837A (en) * | 2002-10-24 | 2005-12-14 | 朗姆研究公司 | Method and apparatus for detecting endpoint during plasma etching of thin films |
| CN1750237A (en) * | 2004-09-14 | 2006-03-22 | 东京毅力科创株式会社 | Etching method and apparatus |
| CN102881578A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for etching polycrystalline silicon gates |
-
2014
- 2014-11-28 CN CN201410714842.3A patent/CN104465352B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160621A (en) * | 1999-09-30 | 2000-12-12 | Lam Research Corporation | Method and apparatus for in-situ monitoring of plasma etch and deposition processes using a pulsed broadband light source |
| US6635573B2 (en) * | 2001-10-29 | 2003-10-21 | Applied Materials, Inc | Method of detecting an endpoint during etching of a material within a recess |
| CN1708837A (en) * | 2002-10-24 | 2005-12-14 | 朗姆研究公司 | Method and apparatus for detecting endpoint during plasma etching of thin films |
| CN1577786A (en) * | 2003-07-07 | 2005-02-09 | 应用材料有限公司 | Interferometric endpoint detection in a substrate etching process |
| CN1750237A (en) * | 2004-09-14 | 2006-03-22 | 东京毅力科创株式会社 | Etching method and apparatus |
| CN102881578A (en) * | 2012-10-12 | 2013-01-16 | 上海华力微电子有限公司 | Method for etching polycrystalline silicon gates |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109559986A (en) * | 2018-12-03 | 2019-04-02 | 上海华力微电子有限公司 | A kind of method of active area electric leakage in improvement etching polysilicon gate |
| CN112133631A (en) * | 2020-09-25 | 2020-12-25 | 上海华力微电子有限公司 | Method for improving stability of grid etching morphology and etching equipment |
| CN112133631B (en) * | 2020-09-25 | 2022-11-18 | 上海华力微电子有限公司 | Method for improving stability of grid etching morphology and etching equipment |
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| CN104465352B (en) | 2018-09-04 |
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