CN104425396A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a plurality of conductive elements, a chip, a package body, and a plurality of solder bumps. The conductive elements are separated from each other. The conductive elements each include a first conductive portion and a second conductive portion adjacent to each other. The chip is electrically connected to the conductive element. The packaging body wraps the chip and the first conductive part of the conductive element. The solder bump is in contact with only the second conductive portion of the conductive element.

Description

Semiconductor package structure and manufacturing method thereof

technical field

The present invention relates to a semiconductor packaging structure and its manufacturing method, and in particular to a semiconductor packaging structure with conductive elements and solder bumps and its manufacturing method.

Background technique

The semiconductor industry is one of the fastest-growing high-tech industries in recent years. With the rapid development of electronic technology and the emergence of high-tech electronic industries, more humanized and better-functional electronic products are constantly being introduced, and are moving toward light, Thin, short and small trend design. At present, in the semiconductor process, the lead frame is one of the frequently used structure carriers, and the lead frame type package using the lead frame as the carrier covers the pin insertion type (Pin Through) Hole, PTH) and surface mount type (Surface Mount Technology, SMT) and other two categories, among which the more common ones are the dual-in-line package structure (Dual In-Line Package, DIP), and the chip is equipped with a lead frame (Lead On Chip Package (LOC) package structure, Quad Flat Package (QFP), and Quad Flat Non-leaded package (QFN package).

However, the general quad flat no lead package structure only has planar pins, so it is difficult to comply with the warping deformation caused by heat when the product is used, thus limiting the board-mounting capability.

Contents of the invention

The invention relates to a semiconductor packaging structure and a manufacturing method thereof, which can improve the board loading capacity of the semiconductor packaging structure.

According to an embodiment, a semiconductor package structure is provided, which includes a plurality of conductive elements, a chip, a package body, and a plurality of solder bumps. The conductive elements are separated from each other. The conductive elements each include a first conductive portion and a second conductive portion adjacent to each other. The chip is electrically connected to the conductive element. The package body covers the chip and the first conductive part of the conductive element. The solder bump only contacts the second conductive portion of the conductive element.

According to another embodiment, a semiconductor package structure is provided, which includes several conductive elements, several conductive elements separated from each other, a chip, a package body, and several solder bumps. The conductive elements are separated from each other. The conductive elements each include a first conductive portion. The chip has several conductive pillars arranged on one active surface. The solder unit physically and electrically connects the conductive column and the first conductive part of the conductive element. The package body covers the chip, the solder unit and the first conductive part of the conductive element. The solder bumps are physically and electrically connected to the conductive elements.

According to another embodiment, a method for manufacturing a semiconductor package structure is provided, which includes the following steps. An upper portion of a conductive layer is removed to define a first conductive portion of each of the plurality of conductive elements. A chip is physically and electrically connected to the first conductive part by using several electrical connectors. A package is used to cover the chip, the electrical connector, and the first conductive part. A lower portion of the conductive layer is removed to define a second conductive portion of each of the conductive elements. Several solder bumps are arranged. The solder bumps are only in contact with the second conductive portion.

In order to make the above-mentioned content of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a cross-sectional view of a semiconductor package structure according to an embodiment.

FIG. 2 is a cross-sectional view of a semiconductor package structure according to an embodiment.

FIG. 3 is a cross-sectional view of a semiconductor package structure according to an embodiment.

FIG. 4 is a cross-sectional view of a semiconductor package structure according to an embodiment.

5A to 5E illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

6A to 6D illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

7A to 7B illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

8A to 8E illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

Description of main component symbols:

102, 202, 202A, 302: semiconductor package structure

104, 204, 304: chips

106: Encapsulation

108, 108A: Conductive elements

110: Solder bump

112, 312: electrical connectors

114: first conductive part

116: second conductive part

118: upper surface

120: side surface

122, 122A: tip

124: lower surface

126: side surface

130, 230, 330: active surface

132: lower surface

234: Conductive column

436: Conductive layer

438, 538: Groove

440: upper surface

442, 542: Groove

444: lower surface

348: lower surface

350: chip holder

352: Part I

354: Part II

356: upper surface

358: side surface

360: lower surface

362: side surface

364: cutting edge

366: Groove

D1, D2: height difference

H: height

W1, W2, W3, W4: Width

Detailed ways

Please refer to FIG. 1 , which illustrates a cross-sectional view of a semiconductor package structure 102 according to an embodiment. The semiconductor package structure 102 includes a chip 104 , a package body 106 , a plurality of conductive elements 108 , a plurality of solder bumps 110 and a plurality of electrical connectors 112 .

The separate conductive elements 108 each include a first conductive portion 114 and a second conductive portion 116 adjacent to each other. The first conductive portion 114 has an upper surface 118 and a side surface 120 adjacent to the upper surface 118 . The second conductive portion 116 has a lower surface 124 and a side surface 126 adjacent to the lower surface 124 . In one embodiment, the side surface 120 and the side surface 126 are inclined surfaces, which are not perpendicular to the adjacent upper surface 118 and lower surface 124 respectively, and a tip 122 is defined at the junction. Viewed from the cross-sectional view, the side surface 120 and the side surface 126 are not limited to the substantially inwardly concave curves as shown in FIG. 1 , and may also be straight lines or other suitable shapes in other embodiments.

In one embodiment, the width W1 of the junction between the first conductive portion 114 and the second conductive portion 116 (ie at the tip 122 ) is greater than the width W2 of the upper surface 118 of the first conductive portion 114 and greater than the width W2 of the second conductive portion 116 The lower surface 124 has a width W3. In addition, the width W3 is greater than the width W2. In one embodiment, the width of the conductive element 108 gradually increases from the upper surface 118 of the first conductive portion 114 to the junction of the first conductive portion 114 and the second conductive portion 116 , and then to the bottom of the second conductive portion 116 Surface 124 tapers. The material of the conductive element 108 is, for example, copper, copper alloy or other suitable metal materials.

In this example, the electrical connector 112 is a solder unit disposed on the active surface 130 of the chip 104 . The electrical connector 112 physically and electrically connects the chip 104 and the first conductive portion 114 of the conductive element 108 . The solder unit includes solder balls.

The package body 106 covers the chip 104 , the electrical connector 112 and the first conductive portion 114 of the conductive element 108 . The package body 106 has a lower surface 132 protruding from the tip 122 of the conductive element 108 , and the second conductive portion 116 of the conductive element 108 extends from the tip 122 to protrude from the lower surface 132 of the package body 106 . The lower surface 132 is not limited to the curved surface shown in the figure, and may also have other shapes in other embodiments. A height difference between the lower surface 132 of the package body 106 and the lower surface 124 of the second conductive portion 116 is D1. The conductive elements 108 are electrically insulated from each other by the package body 106 . The package body 106 may include Novolac-based resin, epoxy-based resin, silicone-based resin or other suitable encapsulating agents. The package body 106 may also include a suitable filler, such as powdered silicon dioxide.

The solder bump 110 only contacts the second conductive portion 116 of the conductive element 108 . More specifically, the solder bump 110 is only in contact with the lower surface 124 and the side surface 126 of the second conductive portion 116 . The solder bump 110 does not contact the package body 106 . In an embodiment, the solder bump 110 includes a solder ball, and the width W4 is the maximum width of the solder ball after reflow. Generally speaking, W4>W1>W3>W2. The height difference between the lower surface 124 of the second conductive portion 116 and the bottom of the solder bump 110 is D2. The height difference D2 may be greater than the height difference D1. The structure in which the width of the second conductive portion 116 gradually increases from the lower surface 124 to the connection with the first conductive portion 114 not only provides a large contact area for the solder bump 110, but also causes a locking effect on the solder bump 110, thus improving the performance of the solder bump 110. The bonding strength with the solder bump 110 is enhanced, and the structural strength of the solder bump 110 is enhanced to improve the properties of the ballshear due to shear force. In an embodiment, the shear force analysis result may be greater than 160 g, such as about 392.5 g. The soft solder bumps 110 can conform to and cushion the deformation stress caused by impact or thermal warpage when the product is in use, so it can improve the ability of the semiconductor package structure 102 to be mounted on a board (such as a printed circuit board (PCB)), so that the semiconductor The packaging structure 102 can be suitable for various packaging applications.

FIG. 2 shows a cross-sectional view of a semiconductor package structure 202 according to an embodiment, and the differences between it and the semiconductor package structure 102 of FIG. 1 are described as follows. The chip 204 has a plurality of conductive pillars 234 disposed on an active surface 230 thereof. The electrical connector 112 is a solder unit disposed on the conductive pillar 234 of the chip 204 . The electrical connector 112 physically and electrically connects the conductive post 234 on the chip 204 to the first conductive portion 114 of the conductive element 108 . The solder unit includes solder balls. The package body 106 covers the chip 204 , the electrical connector 112 and the first conductive portion 114 of the conductive element 108 .

FIG. 3 shows a cross-sectional view of a semiconductor package structure 202A according to an embodiment, and the differences between it and the semiconductor package structure 202 of FIG. 2 are described as follows. The conductive element 108A has only the first conductive portion 114 , in other words, the second conductive portion 116 of FIG. 2 is omitted. A tip 122A is defined between the non-perpendicular side surfaces 120 and the lower surface 348 of the first conductive portion 114, and its position may be substantially the same as that of the tip 122 shown in FIG. 2 (ie, the first conductive portion 114 of the conductive element 108A. The height is substantially equal to the first conductive portion 114 of the conductive element 108 of FIG. 2 ). The bottom surface 132 of the package body 106 protrudes from the tip 122A of the conductive element 108A. The solder bump 110 is physically and electrically connected to the lower surface 348 of the first conductive portion 114 and protrudes from the lower surface 132 of the package body 106 .

FIG. 4 shows a cross-sectional view of a semiconductor package structure 302 according to an embodiment, and the differences between it and the semiconductor package structure 102 of FIG. 1 are described as follows. The semiconductor package structure 302 includes a die pad 350 including a first pad portion 352 and a second pad portion 354 adjacent thereto. The first seat portion 352 has an upper surface 356 and a side surface 358 adjacent to the upper surface 356 . The second seat portion 354 has a lower surface 360 and a side surface 362 adjacent to the lower surface 360 . In one embodiment, the side surface 358 and the side surface 362 are inclined surfaces, which are not perpendicular to the adjacent upper surface 356 and lower surface 360 respectively, and a point 364 is defined at the junction. Viewed from the cross-sectional view, the side surface 358 and the side surface 362 are not limited to the substantially inwardly concave curves as shown in FIG. 4 , and may also be straight lines or other suitable shapes in other embodiments. The die 304 may be attached to the bottom of the recess 366 defining the first seat portion 352 of the die holder 350 via an adhesive layer (not shown). The adhesive layer is, for example, a conductive adhesive material or a non-conductive adhesive material, wherein the conductive adhesive material is, for example, silver glue, and the non-conductive adhesive material is, for example, non-conductive epoxy resin (epoxy). In this example, the electrical connector 312 is a wire, which physically and electrically connects the active surface 330 of the chip 304 , the first conductive portion 114 of the conductive element 108 and the first seat portion 352 of the chip holder 350 . The material of the wire may include gold, copper, nickel, palladium or alloys thereof.

5A to 5E illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

Referring to FIG. 5A , a conductive layer 436 is provided. In one embodiment, the conductive layer 436 is copper foil. An upper portion of the conductive layer 436 is removed to form a plurality of grooves 438 and define the first conductive portion 114 . In one embodiment, the method for removing the conductive layer 436 may include forming a patterned photoresist layer (not shown) on the upper surface 440 of the conductive layer 436, and then performing an etching step to expose the conductive layer 436 from the patterned photoresist layer. The conductive layer 436 is removed down the upper surface 440, and then the patterned photoresist layer is removed. In another embodiment, the method for removing the conductive layer 436 may include forming a patterned photoresist layer (not shown) on the upper surface 440 of the conductive layer 436, and then performing an electroplating process to expose the patterned photoresist layer. Form a metal plating layer (not shown) on the upper surface 440 of the upper surface 440, then remove the patterned photoresist layer, and use the metal plating layer as an etching mask, perform an etching step to remove the conductive layer 436 from the upper surface 440 downward, where the conductive Layer 436 can be copper foil, and the metal plating can be nickel, gold or other materials.

Referring to FIG. 5B , the flip-chip process is used to physically and electrically connect the chip 104 and the first conductive portion 114 with the electrical connector 112 of the solder unit.

Referring to FIG. 5C , the chip 104 and the electrical connector 112 are covered by the package body 106 , and the groove 438 between the first conductive parts 114 is filled. The package body 106 can be formed using several packaging techniques, such as compression molding, liquid encapsulation, injection molding, or transfer molding.

Referring to FIG. 5D , a lower part of the conductive layer 436 ( FIG. 5C ) is removed to form a groove 442 communicating with the groove 438 and defining a second conductive portion 116 . The groove 442 exposes the lower surface 132 of the package body 106 . The adjacent first conductive portion 114 and the second conductive portion 116 constitute the conductive element 108 , and the conductive elements 108 separated from each other are electrically insulated from each other by the package body 106 . In one embodiment, the method of removing the conductive layer 436 may include forming a patterned photoresist layer (not shown) on the lower surface 444 of the conductive layer 436 (FIG. The exposed lower surface 444 of the resist layer removes the conductive layer 436 inwardly, and then removes the patterned photoresist layer. In another embodiment, the method for removing the conductive layer 436 may include forming a patterned photoresist layer (not shown) on the lower surface 444 of the conductive layer 436, and then performing an electroplating process to expose the patterned photoresist layer. Form a metal plating layer (not shown) on the lower surface 444 of the lower surface 444, then remove the patterned photoresist layer, and use the metal plating layer as an etching mask, perform an etching step to remove the conductive layer 436 from the lower surface 444 inwardly, wherein the metal Plating layer can be nickel, gold and other materials.

Referring to FIG. 5E , a plurality of solder bumps 110 are disposed, which are only in contact with the second conductive portion 116 . In other words, the solder bump 110 does not contact the package body 106 .

6A to 6D illustrate a method of manufacturing a semiconductor package structure according to an embodiment. Before the steps shown in FIG. 6A , the steps shown in FIG. 5A can be performed, which will not be repeated here.

Referring to FIG. 6A , a chip 204 with conductive pillars 234 on its active surface 230 is provided, and the conductive pillars 234 of the chip 204 are physically and electrically connected to the first conductive portion 114 by using the electrical connector 112 as a solder unit.

Referring to FIG. 6B , the package 106 is used to cover the chip 204 , the conductive posts 234 and the electrical connectors 112 , and fill the groove 438 between the first conductive parts 114 .

Referring to FIG. 6C , a lower part of the conductive layer 436 ( FIG. 6B ) is removed to form a groove 442 communicating with the groove 438 and define the second conductive portion 116 . The adjacent first conductive portion 114 and the second conductive portion 116 constitute the conductive element 108 .

Referring to FIG. 6D , a plurality of solder bumps 110 are disposed, which are only in contact with the second conductive portion 116 of the conductive element 108 . In other words, the solder bump 110 does not contact the package body 106 .

7A to 7B illustrate a method of manufacturing a semiconductor package structure according to an embodiment. Before the step shown in FIG. 7A , the steps shown in FIGS. 6A to 6B may be performed, and details are not repeated here.

Referring to FIG. 7A , a lower portion of the conductive layer 436 ( FIG. 6B ) is removed, and the remaining upper portion forms the first conductive portion 114 of the conductive element 108A.

Referring to FIG. 7B , the solder bump 110 is disposed on the exposed lower surface 348 of the conductive element 108A (or the first conductive portion 114 ).

8A to 8E illustrate a method of manufacturing a semiconductor package structure according to an embodiment.

Referring to FIG. 8A , a conductive layer 436 is provided. An upper portion of the conductive layer 436 is removed to form the groove 538 and the groove 366 to define the first conductive portion 114 and the first seating portion 352 .

Referring to FIG. 8B , the chip 304 can be attached to the bottom of the groove 366 via an adhesive layer (not shown). The wire bonding technology is used to physically and electrically connect the chip 304 , the first conductive portion 114 , and the first seat portion 352 by the electrical connection member 312 which is a wire.

Referring to FIG. 8C , the package 106 is used to cover the chip 304 , the electrical connector 312 , the first conductive portion 114 , and the first seat portion 352 .

Referring to FIG. 8D , a lower portion of the conductive layer 436 ( FIG. 8C ) is removed to form a groove 542 communicating with the groove 538 , and to define the second conductive portion 116 and the second seating portion 354 . The adjacent first conductive portion 114 and the second conductive portion 116 constitute the conductive element 108 . The adjacent first seat portion 352 and the second seat portion 354 constitute the chip seat 350 .

Referring to FIG. 8E , a plurality of solder bumps 110 are disposed, which are only in contact with the second conductive portion 116 of the conductive element 108 . In other words, the solder bump 110 does not contact the package body 106 .

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (10)

1. A semiconductor packaging structure, characterized in that, comprising: a plurality of mutually separated conductive elements, each comprising a first conductive portion and a second conductive portion adjacent to each other; a chip electrically connected to the conductive elements; a package covering the chip and the first conductive parts of the conductive elements; and Several solder bumps are only in contact with the second conductive parts of the conductive elements. 2. The semiconductor package structure according to claim 1, further comprising a plurality of electrical connectors, wherein the chip is connected to the first conductive parts of the conductive elements through the electrical connectors. 3. The semiconductor package structure according to claim 1, wherein the second conductive portions of the conductive elements protrude from a lower surface of the package. 4. The semiconductor package structure according to claim 1, wherein a width of the junction between the first conductive portion and the second conductive portion is larger than a width of an upper surface of the first conductive portion, and larger than the width of the first conductive portion. 2. The width of the lower surface of the conductive part. 5. The semiconductor package structure according to claim 1, wherein the width of the conductive element is gradually from an upper surface of the first conductive portion to a junction between the first conductive portion and the second conductive portion become larger, and gradually become smaller towards the lower surface of the second conductive part. 6. The semiconductor package structure according to claim 1, wherein the second conductive portion has a lower surface and one side surface adjacent to the lower surface, and the solder bump is only connected to the lower surface of the second conductive portion in contact with the side surface. 7. The semiconductor package structure according to claim 1, wherein the electrical connectors comprise wires or solder. 8. A semiconductor packaging structure, characterized in that it comprises: a plurality of mutually separated conductive elements, each including a first conductive portion; several solder units; A chip has a plurality of conductive pillars disposed on an active surface thereof, wherein the solder units are physically and electrically connected to the conductive pillars and the first conductive parts of the conductive elements; a package covering the chip, the solder units and the first conductive parts of the conductive elements; and A plurality of solder bumps are physically and electrically connected to the conductive elements. 9. The semiconductor package structure according to claim 8, wherein each of the conductive elements further comprises a second conductive portion adjacent to the first conductive portion, and the solder bumps are only in contact with the conductive elements. The second conductive portion is in contact. 10. A method for manufacturing a semiconductor package structure, comprising: removing an upper portion of a conductive layer to define a first conductive portion of each of the plurality of conductive elements; physically and electrically connecting a chip with the first conductive parts by using a plurality of electrical connectors; encapsulating the chip, the electrical connectors, and the first conductive parts with a package; removing a lower portion of the conductive layer to define a second conductive portion of each of the conductive elements; and A plurality of solder bumps are configured, and the solder bumps are only in contact with the second conductive parts.