CN104391425A - Method for manufacturing small-gap planar electrode - Google Patents
Method for manufacturing small-gap planar electrode Download PDFInfo
- Publication number
- CN104391425A CN104391425A CN201410557759.XA CN201410557759A CN104391425A CN 104391425 A CN104391425 A CN 104391425A CN 201410557759 A CN201410557759 A CN 201410557759A CN 104391425 A CN104391425 A CN 104391425A
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- China
- Prior art keywords
- layout
- published
- gap
- lithography
- marker graphic
- Prior art date
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Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000001459 lithography Methods 0.000 claims description 36
- 239000003550 marker Substances 0.000 claims description 22
- 238000001259 photo etching Methods 0.000 abstract description 15
- 238000002360 preparation method Methods 0.000 abstract description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Micromachines (AREA)
Abstract
The invention discloses a layout design method for realizing a small-gap planar electrode, which comprises the following steps: designing a first version photoetching layout graph and a marking graph; designing a second version photoetching layout graph and a marking graph; and adjusting the distance between the first plate photoetching layout graph and the second plate photoetching layout graph to form a series of gaps with different sizes. By utilizing the invention, through the optimized design of the photoetching layout, the small-size gap structure which breaks through the photoetching alignment precision can be realized, the photoetching alignment precision is improved to a great extent, the invention has great practical significance for the preparation of the plane small-size gap structure, and the problem of low precision in photoetching alignment is solved.
Description
Technical field
The present invention relates to nano electron device and technical field of nano-processing, particularly relate to a kind of method for making of small―gap suture plane electrode.
Background technology
Semiconductor and greatly developing of microelectronic industry promote the continuous progress of micro-nano technology technique always.Nowadays, the technology such as mobile interchange, cloud computing and large data proposes revolutionary challenge again to micro-nano technology technology.Need prepare have super-high density, high response speed device to satisfy the demands.In micro-nano technology technique, photoetching is the Main Means graphically forming micro-nano structure, and its technological process is simply controlled, can large area realize and advantage of lower cost.But, be limited to the principle of photolithography patterning and the factor of equipment itself, though be ordinary optical photoetching also or the higher beamwriter lithography of precision all exists certain lithographic accuracy and alignment precision, make the distance realized between two domain shapes by photoetching alignment can not lower than a certain numerical value.In micro-nano structure, realize the aligning of two parts figure frequently by alignment, realize the less gap structure of a size with this.Such as two parts figure metal material that deposit is different respectively, forms the two terminal device with planar structure.But the realization breaking through the small size plane two-end structure of alignment precision is very difficult.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of layout design method realizing small―gap suture plane electrode, to solve the problem that in photoetching alignment, precision is not high.
(2) technical scheme
For achieving the above object, the invention provides a kind of layout design method realizing small―gap suture plane electrode, comprising: design first published lithography layout figure and marker graphic; Design second edition lithography layout figure and marker graphic; And the spacing of adjustment first published lithography layout figure and second edition lithography layout figure, form a series of gap varied in size.
In such scheme, in the step of described design first published lithography layout figure and marker graphic, described first published lithography layout for forming closely spaced a part of figure, described in be labeled as cross alignment mark, be evenly distributed on domain, and have coarse alignment mark and thin alignment mark divide.Described first published lithography layout figure and described marker graphic belong to same layer.
In such scheme, in the step of described design second edition lithography layout figure and marker graphic, described second edition lithography layout figure is for forming closely spaced other a part of figure, and described marker graphic has identical position and size with marker graphic in first published.Described second edition lithography layout figure and described marker graphic belong to same layer.
In such scheme, in the step of the spacing of described adjustment first published lithography layout figure and second edition lithography layout figure, progressively expand gap from two editions graphs coincide, until form comparatively wide arc gap, design a series of gap size.
(3) beneficial effect
As can be seen from technique scheme, the present invention has beneficial effect:
1, the present invention is utilized, by the optimal design of lithography layout, the small size gap structure breaking through lithography alignment accuracy can be realized, improve the alignment accuracy of photoetching to a great extent, to the preparation of plane small size gap structure, there is very large realistic meaning, solve the problem that in photoetching alignment, precision is not high.
2, utilize the present invention, provide a kind of new approaches promoting lithography alignment accuracy, prepare small scale structures to utilizing micro-nano technology technique and provide a kind of effective method.
Accompanying drawing explanation
Fig. 1 is the layout design method process flow diagram realizing small―gap suture plane electrode provided by the invention.
The effect schematic diagram that Fig. 2 is the domain according to method design shown in Fig. 1.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the layout design method process flow diagram realizing small―gap suture planar structure, specifically comprises:
Step 1: design first published lithography layout figure and marker graphic;
First in layout design software, select the color that this one deck of first published is used, define the size of whole domain, the layout of cross alignment mark is designed within the scope of suitable domain, in order to reduce the difficulty of second edition alignment and ensure higher alignment precision, need to design two groups of different alignment marks of size, be evenly distributed on whole domain.First published lithography layout for formed closely spaced a part of figure, be labeled as cross alignment mark, be evenly distributed on domain, and have coarse alignment mark and thin alignment mark divide.First published lithography layout figure and marker graphic belong to same layer.
Step 2: design second edition lithography layout figure and marker graphic;
First the color different from first published is selected to distinguish different layers in layout design software, the position corresponding with first published figure is drawn second edition graphic structure, the mark of the second edition need with first published be marked at position same in domain, same size also overlaps completely.Second edition lithography layout figure is for forming closely spaced other a part of figure, and marker graphic has identical position and size with marker graphic in first published.Second edition lithography layout figure and marker graphic belong to same layer.
Step 3: the spacing of adjustment first published lithography layout figure and second edition lithography layout figure, forms a series of gap varied in size;
Namely relative position by adjusting first published and second edition figure in layout design software can realize the change of the spacing of two domain shapes.This step progressively expands gap from two editions graphs coincide, until form comparatively wide arc gap, designs a series of gap size.Two editions spacing after adjustment are a series of value, overlap onto two domain shapes have certain gap and progressively change from two domain shapes.
Embodiment
The present embodiment selects ordinary optical photoetching process to realize having the two ends electric resistance changing storer of planar structure.First published electrode material is platinum, and second edition electrode material is silver, to it is desirable to prepare between electrode size at the device architecture of 100 ran.
First the figure designing first published platinum electrode is the wide rectangle structure of 2 millimeters long 10 microns.The mark of first published is divided into two groups, and the first group echo is large scale cross, and the length of cross lines is 100 microns, and wide is 10 microns.Be distributed in the middle of domain and four corners up and down; Second group echo is small size cross, long 20 microns of cross lines, wide 3 microns.
Then the figure designing second edition silver electrode be 50 microns square square below have the cutting-edge structure of 10 microns long 3 microns wide.The rectangular figure of each platinum of first published has 13 identical silver electrode figures with only corresponding, forms a series of small―gap suture structure.
The spacing of figure between finally adjusting two editions, the relative position that is by adjusting first published platinum electrode figure and second edition silver electrode figure realizes the device architecture of different gap.Here it may be noted that, two domain shapes of left end first device are adjusted to overlap, the height of lap is 600 nanometers, reduce the stack height of the device two domain shape on right side successively, the amplitude of each reduction is 100 nanometers, and the distance between two domain shapes of the 7th device so is from left to right zero.Continuing to adjust successively the distance of two domain shapes to the right, increase by 100 nanometers successively, be two editions pattern pitch is 600 nanometers to the 13rd device.Utilize this domain to make mask and carry out optical lithography, the plane two terminal device of electrode gap at 100 ran can be prepared.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. realize a layout design method for small―gap suture plane electrode, it is characterized in that, comprising:
Design first published lithography layout figure and marker graphic;
Design second edition lithography layout figure and marker graphic; And
The spacing of adjustment first published lithography layout figure and second edition lithography layout figure, forms a series of gap varied in size.
2. the layout design method realizing small―gap suture plane electrode according to claim 1, it is characterized in that, in the step of described design first published lithography layout figure and marker graphic, described first published lithography layout is for forming closely spaced a part of figure, describedly be labeled as cross alignment mark, be evenly distributed on domain, and have coarse alignment mark and thin alignment mark divide.
3. the layout design method realizing small―gap suture plane electrode according to claim 2, is characterized in that, described first published lithography layout figure and described marker graphic belong to same layer.
4. the layout design method realizing small―gap suture plane electrode according to claim 1, it is characterized in that, in the step of described design second edition lithography layout figure and marker graphic, described second edition lithography layout figure is for forming closely spaced other a part of figure, and described marker graphic has identical position and size with marker graphic in first published.
5. the layout design method realizing small―gap suture plane electrode according to claim 4, is characterized in that, described second edition lithography layout figure and described marker graphic belong to same layer.
6. the layout design method realizing small―gap suture plane electrode according to claim 1, it is characterized in that, in the step of the spacing of described adjustment first published lithography layout figure and second edition lithography layout figure, progressively gap is expanded from two editions graphs coincide, until form comparatively wide arc gap, design a series of gap size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410557759.XA CN104391425B (en) | 2014-10-20 | 2014-10-20 | Method for manufacturing small-gap planar electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410557759.XA CN104391425B (en) | 2014-10-20 | 2014-10-20 | Method for manufacturing small-gap planar electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104391425A true CN104391425A (en) | 2015-03-04 |
| CN104391425B CN104391425B (en) | 2019-01-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410557759.XA Active CN104391425B (en) | 2014-10-20 | 2014-10-20 | Method for manufacturing small-gap planar electrode |
Country Status (1)
| Country | Link |
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| CN (1) | CN104391425B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1513012A2 (en) * | 2003-09-05 | 2005-03-09 | ASML MaskTools B.V. | Method and apparatus for performing model based placement of phase-balanced scattering bars for sub-wavelength optical lithography |
| CN101656225A (en) * | 2008-08-22 | 2010-02-24 | 台湾积体电路制造股份有限公司 | Hybrid multi-layer photo-mask set and manufacturing method thereof |
| CN101957556A (en) * | 2009-07-16 | 2011-01-26 | 中芯国际集成电路制造(上海)有限公司 | Mask picture modification method, mask manufacturing method and optical proximity correction method |
| CN102122113A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| US20120210279A1 (en) * | 2011-02-15 | 2012-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Decomposition and marking of semiconductor device design layout in double patterning lithography |
-
2014
- 2014-10-20 CN CN201410557759.XA patent/CN104391425B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1513012A2 (en) * | 2003-09-05 | 2005-03-09 | ASML MaskTools B.V. | Method and apparatus for performing model based placement of phase-balanced scattering bars for sub-wavelength optical lithography |
| CN101656225A (en) * | 2008-08-22 | 2010-02-24 | 台湾积体电路制造股份有限公司 | Hybrid multi-layer photo-mask set and manufacturing method thereof |
| CN101957556A (en) * | 2009-07-16 | 2011-01-26 | 中芯国际集成电路制造(上海)有限公司 | Mask picture modification method, mask manufacturing method and optical proximity correction method |
| CN102122113A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| US20120210279A1 (en) * | 2011-02-15 | 2012-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Decomposition and marking of semiconductor device design layout in double patterning lithography |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104391425B (en) | 2019-01-22 |
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