CN104347621A - Electrostatic discharge protection method of chip with multiple power systems and multiple package types - Google Patents

Abstract

The invention discloses an electrostatic discharge protection method of a chip with multiple power systems and multiple package types. According to the method, in addition to using a common ground wire path in the chip, a ground potential in a seal ring is utilized, and a ground wire of each power system is connected, so that the electrostatic discharge current is released through two parallel paths, and thus the condition of damage caused by excessive potential of a circuit in the chip due to overlarge parasitic resistance on a discharge path is avoided. According to the method, the ESD (Electronic Static Discharge) performance of the chip is enhanced without increasing the area of the chip.

Description

The chip electro-static discharge guard method of a kind of many power supplys system, many packing forms

Technical field

The present invention proposes the chip electro-static discharge guard method of a kind of many power supplys system, many packing forms.This invention is applicable to the chip design field of many power supplys system, many packing forms, is particularly useful for IO and shares same earthy chip design.

Background technology

Along with integrated circuit fabrication process level enters deep sub-micron era, MOS (Metal-oxide-semicondutor) transistor in integrated circuit all adopts shallow doped structure LDD (Lightly Doped Drain); Silicide process is covered on MOS transistor diffusion region; Polycrystalline compounds technique can reduce the series resistance of gate polycrystalline; MOS transistor thickness of grid oxide layer is more and more thinner, and channel length is more and more less.These improve the integrated level that all improve chip and the arithmetic speed improving chip, reduce chip power-consumption, but design for the static discharge of deep submicron integrated circuit, but bring very large drawback, cause the reliability decrease of chip product.

ESD refers to that a certain amount of electric charge transfers to the process of (as chip) another object from an object (as human body).At present the anti-ESD harm of integrated circuit (IC) chip is required to be all body's static electricity preventing to be main, and establishes manikin (HBM, Human Body Model), HBM be set up in ESD model the earliest with one of topmost model.The human body that what he described is occurs when a people with electrostatic catches the pin of tactile integrated circuit (IC) chip is to chip pin electric discharge phenomena.Therefore, ESD usually the input of integrated circuit, export IO and power supply, I/O circuit inside formed.This process can cause chip in a short period of time by a very large electric current, and the chip failure of more than 35% is caused by ESD.

The purpose of design of esd protection circuit will avoid operating circuit become esd discharge path and damaged exactly; ensure the ESD occurred at any chip pin; there is applicable low impedance path that ESD circuit is introduced power supply or ground wire, by another one pin, ESD electric current is bled off.

For the chip of more complicated, there is more IO number usually.The interface of different application, because power level is different, needs the different electrical power IO used, forms many power supplys system chip.IO supply voltage scope as specified in ISO7816 standard is 1.62 ~ 5.5V, GPIO (general purpose I/O) supply voltage scope is that in 2.7 ~ 5.5V, USB2.0 specification, regulation USBPHY supply voltage scope is 3.0V ~ 3.6V etc.

Many packing forms refer to, for a chips, can encapsulate out different pins according to different application.The input and output IO of such as ISO7816 will carry out card packing forms, and GPIO will carry out QFP64 (flat-four-side 64 pin) packing forms etc.Usually, the input and output IO of ISO7816, GPIO can be multiplexed with, that is, the input and output IO of ISO7816 should meet the encapsulation order that ISO7816 specifies, also will meet encapsulation order during GPIO application, therefore, between each pin of same power domain, also not close is adjacent, there is larger spacing.Due to the existence of IO spacing, on the ESD path between IO, spurious impedance increases, and ESD design difficulty increases.

In this case, each type pins is still needed to have higher ESD level to meet chip performance requirement.As ESD (HBM) the level > 6KV of 7816IO; ESD (HBM) the level > 4KV of USBPHYIO; ESD (HBM) the level > 2KV of GPIO.

Chip ESD design in, consider between each power supply system of chip by one " " be linked together, the ESD electric current of each pin of chip all can be discharged by this ground paths.Therefore the ground paths of full chip is the breach of many power supplys system, the design of many packing forms chip esd protection.

Common design is at chip internal, widens the metal line-width of ground paths, reduces the spurious impedance between chip any two points, realizes effective esd discharge path.But this method can cause the increase of chip area.More importantly, owing to guiding ESD ground paths into chip internal, chip internal substrate electric potential may be caused too high, may cause having internal components to damage when esd discharge.

The present invention is exactly except the normal ground paths of chip internal, also utilize in sealring " " current potential, the ground wire of each power supply system is communicated with get up in chip periphery, reduces the spurious impedance between chip any two points, realize effective esd discharge path.

Chip Sealring is to prevent chip to be subject to mechanical damage when cutting, and a circle " divider wall " of design, be the guard ring between chip and scribe line.If be used as the esd discharge path of chip, both strengthened the ESD performance of chip, do not increased chip area again, to chip without any functional loss of energy.Metal width on usual sealring is several microns to tens microns, has all metal levels of metal1 ~ topmetal simultaneously, with chip internal ground line parallel, highly beneficial to earth potential dead resistance between reduction chip any two points.

Summary of the invention

What the present invention proposed is a kind of effective solution, can improve the ESD performance of many power supplys system, many packing forms chip with less chip area.

The invention provides a kind of static discharge new architecture, comprise the method for attachment between chip ground IO and sealring, the method for designing etc. of sealring.

Wherein, the method for attachment between the ground wire of chip I/O and sealring comprises, and one is that chip ground IO draws metal wire from bonding PAD, and skip floor is to metal1 ~ topmetal, is connected with the metal1 ~ topmetal of sealring; Two is that chip power IO and input and output are drawn from bonding PAD both sides by the ground wire I/O cell, and skip floor is to metal1 ~ topmetal, is connected with the metal1 ~ topmetal of sealring.

The method for designing of sealring, ensured that sealring is injected by metal1 ~ topmetal, P+ and forms, and be closed into ring, around chip one week.In Sealring, metal1 ~ topmetal is connected by the via of each layer.By contact below metal wire in sealring, be communicated with psub, ensure that the earth potential of metal wire is identical with chip earth potential.At chip internal, the earth potential of each power supply system is still communicated with by metal, as ESD ground paths together with the wide metal in sealring.

The method utilizes metal1 ~ topmetal multilayer width metal lines in sealring, as the ESD ground paths of many power supplys system chip, strengthens the esd discharge ability of chip.By the I/O cell of each power supply system (comprise input IO, export IO, two-way IO, power supply IO, IO) in ground wire, be connected on the metal wire of sealring by metal1 ~ topmetal.Be communicated with by the via of each layer between metal in sealring, to ensure, between each layer, there is discharge path.

Accompanying drawing explanation

Fig. 1 the invention process case, esd discharge (IO1 beats positive electricity to IO2) equivalent discharge path between the IO pin of chip two power supply systems.

Fig. 2 the invention process case, chip ground wire ESD track layout schematic diagram.In this figure, only illustrate all kinds IO with the method for attachment of sealring, and chip, IO and sealring position relationship, IO number and IO particular location in chip are not described.

Embodiment

As shown in Figure 1, the ESD electric current of IO1 pin flows to VDD1 by ESD clamp1, chip internal GND is flowed to by ESD clamp3, flow to sealringGND simultaneously, chip internal GND and sealring GND forms alternate path, arrive the GND node of IO2, by ESD clamp5, IO2 pin is discharged.

As shown in Figure 2, take area as the chip of 4mm*4mm be example, chip internal ground wire is metal2, and width is 40um, and is closed into ring in the chips; The outer sealring ground wire of chip is metal1 ~ metal4, and width is 10um.Denote in figure, black line is chip active graphical frame; Tiltedly be scribed ss chip outer ring sealring; Grid line is the annular ground wire of chip internal and the ground wire that is connected with sealring.Line between each IO and sealring according to the number of metal of IO domain or the actual permission of chip layout and metal width, can carry out line.

If IO1 and IO2 is placed on chip diagonal angle just, only consider that the dead resistance introduced by ground wire metal wire is, R _in≈ (4000+4000)/(2*40) * 0.08=8ohm; And the dead resistance that sealring ground wire is introduced is R _sR≈ (4000+4000)/(2*3*10) * 0.08//(4000+4000)/(2*10) * 0.04=6ohm, the equivalent parasitic resistance of chip internal ground line parallel sealring ground wire is R _{in parallel}≈ 8//6=3.5ohm.Wherein 0.08 for removing top wire square resistance; 0.04 is top wire square resistance.

During ESD voltage tester to 4KV (esd discharge current peak is 2.67A), the dead resistance pressure drop of inner ground wire is only had to be, V _in=2.67A*8=21.36V.This voltage is far longer than device withstand voltage level (being assumed to be 10V), and chip I 0 or internal components may be caused to damage; The dead resistance pressure drop of chip internal ground line parallel sealring ground wire is, V _{in parallel}=2.67A*3.5=9.35V.Voltage is less than device withstand voltage 10V, can protect IC internal components.

For this case, adopt the present invention, good protection is served to the withstand voltage internal components for 10V.

Claims (2)

1. chip many power supplys system, the chip electro-static discharge guard method of many packing forms, it is characterized in that, the method to utilize in sealring first layer metal to the multilayer width metal lines of top-level metallic, as the ESD ground paths of many power supplys system chip, strengthen the esd discharge ability of chip, specific as follows: chip ground IO draws metal wire from pressure welding point bonding PAD, or chip power IO and input and output are drawn from bonding PAD both sides by the ground wire I/O cell, and skip floor is to first layer metal to top-level metallic, be connected to top-level metallic with the first layer metal of sealring, ensure that sealring is injected by first layer metal form to top-level metallic, P type hole, and be closed into ring, around chip one week, in Sealring, first layer metal is connected by the through hole of each layer to top-level metallic, contact hole is passed through below metal wire in sealring, be communicated with P type substrate, ensure that the earth potential of metal wire is identical with chip earth potential, at chip internal, the earth potential of each power supply system is still communicated with by metal, as ESD ground paths together with the width metal lines in sealring.

2. the method for claim 1, it is characterized in that the method to utilize in sealring first layer metal to top-level metallic multilayer width metal lines, as the ESD ground paths of many power supplys system chip, strengthen the esd discharge ability of chip, by the ground wire in the I/O cell of each power supply system, be connected on the multilayer width metal lines of sealring by first layer metal to top-level metallic, be communicated with by the through hole of each layer between multilayer width metal lines in sealring, to ensure, between each layer, there is discharge path.