CN104330775A - Attenuation control method of digital STC attenuation circuit - Google Patents

Abstract

The invention relates to an attenuation control method of a digital STC attenuation circuit, and a digital processing mode is used to realize the change of bias voltage with time. The voltage corresponding to different attenuation amounts is stored by using the memory unit of a memory, a voltage value is a 12-number binary number, and the voltage value (which is the attenuation amount) of each memory unit of the memory is determined according to an index requirement. Since the voltage value is a digital quantity, the voltage value is converted into a corresponding analog quantity through D/A conversion and then is converted into the corresponding voltage through a current/voltage conversion circuit to control an electrically controlled attenuator. The method has the advantages of small curve error, high precision and no burr.

Description

A kind of adjustable attenuation method of digital STC attenuator circuit

Technical field

The present invention relates to modern radar reception technique field, specifically a kind of adjustable attenuation method of Precision digital STC attenuator circuit.

Background technology

In radar real work, be inevitably subject to noise jamming stronger in short range.Such as, the radar on naval vessel can run into the noise jamming of reflectance of sea wave, and ground radar can run into the noise jamming of the clutter reflections such as jungle.Now, if the gain of receiver is high, then the aim in short distance in noise jamming will make the saturation of receiver.If the gain of receiver adjust too low, although process goal nonoverload in noise jamming, receiver sensitivity is greatly diminished, thus affects the detection of far field target.In order to solve this contradiction, adopt Sensitivity Time gain control circuit STC (Sensitive Time Control).Sensitivity Time gain control circuit is also called near area gain and controls or temporal gain control, and its implication is exactly the sensitivity decrease making receiver closely time, saturated to prevent short range clutter from making receiver occur; Receiver is made to keep original gain and sensitivity at a distance, to ensure the acquisition of Small object and to distinguish.

At present, the method that two kinds produce STC curve is mainly contained.

Method 1: use the electric discharge of RC circuit to obtain control voltage, produce a voltage waveform matched with the Changing Pattern of STC waveform.The STC curve that the method generates is observed continuously smooth on oscillograph, does not have burr, but underaction.

Method 2: in modern radar, STC has often come with numerical-control attenuator and programmable chip, and control signal can determine to have high precision according to the clutter environment of surrounding, control the advantages such as flexible, but the method easily produces burr.

Summary of the invention

The technical matters solved

In order to avoid the deficiencies in the prior art part, the present invention proposes a kind of adjustable attenuation method of digital STC attenuator circuit.

Technical scheme

An adjustable attenuation method for digital STC attenuator circuit, described digital STC attenuator circuit comprises FPGA, DAC converter, amplifier modulate circuit, electrically controlled attenuator, amplifier, frequency mixer and wave filter, it is characterized in that step is as follows:

Step 1: receiver protection pulse and system clock two signals are inputed to FPGA;

Step 2:FPGA is according to radar signal decays amount and the relational expression of time

$D=-40\lg \frac{t}{t_0}$

12 binary codes corresponding to radar signal decays amount are saved as .MIF file, calls in the LPM_ROM of FPGA; Under receiver protection pulse action, to system clock counting, count value as address, to LPM_ROM addressing; Wherein t ₀for decaying release time;

Step 3:DAC converter becomes the controlled quentity controlled variable electric current of simulation one group of 12 bit code conversion that LPM_ROM exports, and the relation of its output current and binary code is as follows:

IOUTA＝(DACCODE/4096)×32×V _REFIO/R _SET

IOUTB＝(4095-DACCODE)/4096×32×V _REFIO/R _SET

Wherein IOUTA is the anode of output current, and IOUTB is the negative terminal of output current, V _rEFIOthe reference voltage of DAC converter, R _sETit is the full inclined output current regulating resistance of DAC converter;

Step 4: amplifier modulate circuit exports to electrically controlled attenuator after the controlled quentity controlled variable current conversion of output is become voltage;

Step 5: electrically controlled attenuator is according to the magnitude of voltage of input, and the signal to signal source is decayed according to the magnitude of voltage of electrically controlled attenuator and the relation table of pad value;

Step 6: the signal after decay is input to oscillograph after amplifying, carrying out mixing and filtering with local oscillation signal.

Described electrically controlled attenuator adopts the HMC346MS8G of Hittite company.

Described DAC converter adopts the AD9762 of AD company.

Beneficial effect

The adjustable attenuation method of a kind of digital STC attenuator circuit that the present invention proposes, have employed digital processing mode and realizes bias voltage over time.The memory-aided internal storage location of profit stores voltage corresponding to differential declines amount, and magnitude of voltage is 12 bit codes, and the magnitude of voltage (both damping capacity) of each internal storage location of storer is determined by index request.Because magnitude of voltage is digital quantity, therefore make it be converted to corresponding analog quantity through D/A conversion, then convert corresponding voltage to through current/voltage translation circuit and go to control electrically controlled attenuator.Advantage is that curve error is little, precision is high, impulse-free robustness.

Accompanying drawing explanation

Fig. 1 damping capacity variation diagram

Fig. 2 the present invention realizes block diagram

Fig. 3 voltage controlled attenuator circuit

Embodiment

Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:

According to the rule that short range noise jamming intensity distance (time) changes, corresponding STC damping capacity is set.Reach a conclusion according to radar equation: the biquadratic of echo strength and distance is inversely proportional to, STC damping capacity is set on this basis.For different positions, the far and near height of its surrounding terrain atural object is had nothing in common with each other, so the zero attenuation distance of STC should be able to adjust easily and flexibly.

Certain model radar STC designing requirement is as follows:

Working frequency range: 8GHz ~ 12GHz;

STC controlling depth: >=30dB;

STC curve returns to normal gain by 1/R4;

The beginning is opened from receiver protection pulse falling edge.

Combine above content, the expression formula of damping capacity is:

D＝40log(L/L0)

Wherein: D is damping capacity (dB), L0 is zero attenuation distance.

The span of independent variable L: 889m≤L≤5000m, (as L=889m, D=-30dB; As L=5000m, D=0dB).

The change curve of damping capacity D as shown in Figure 1.

Utilize the relation of radar horizon and time and the relation of operating distance and radar signal decays amount, the relation extrapolating radar signal decays amount and time is:

$D=-40\lg \frac{t}{t_0}$

Wherein t ₀for decaying release time;

Electrically controlled attenuator changes its damping capacity by its bias voltage, but fixing bias voltage can only realize quantitative decay, and can not meet technical requirement, therefore controls the damping capacity of electrically controlled attenuator with the bias voltage of change.

Based on above-mentioned design concept, the present invention adopts the D/A converter AD9762 design of field programmable logic device FPGA and AD company of the U.S. to produce and controls electric current, again through amplifier modulate circuit, produce STC control voltage, the HMC346MS8G of Hittite company of the U.S. selected by electrically controlled attenuator.Use amplify and mixing, filter circuit design auxiliary test unit, STC circuit is tested.

HMC346MS8G is high performance-cost ratio, the absorbability broadband voltage controlled attenuator VCA of Hittite Microwave Corporation, and the reference attenuator utilizing its inside to carry and an external arithmetic amplifier just can by the effective control of control voltage realization to voltage controlled attenuator.Its principal feature: the broadband attenuation characteristic with DC ~ 14GHz; There is low phase shift and attenuation ratio; There is the comparatively high attenuation dynamic range of 30dB; There is good wideband impedance match characteristic; Control mode is simple.

This VCA needs V1 and V2 bis-tunnel control voltage just can meet complementary relationship, and when namely their control planning is V1 increase, V2 reduces, but they all need negative supply.The major function of I is for VCA provides drive current.Control to be reduced to a road and realize good broadband attenuation characteristic, requiring to keep input, export the characteristic impedance being 50 Ω.Utilize the external arithmetic amplifier shown in Fig. 3 to realize the virtual impedance coupling of broadband attenuator in design for this reason.Chip adopts principal and subordinate's attenuating structure of T-shaped topology, in master fader, adopt the resistance between the collector and emitter connecting FET to be 50 Ω, and from attenuator, be 500 Ω, the object of its 10:1 is the impedance operator allowing external impedance translation circuit simultaneously to regulate principal and subordinate to decay.External impedance translation circuit can be utilized like this by regulating V2 voltage continuously to maintain the characteristic impedance from attenuator 500 Ω, and due to the impedance relationship of principal and subordinate 10:1, therefore, the RF input characteristic impedance of main decay remains 50 Ω.

Due to the normal need of work negative bias of this VCA, therefore add a diode in the design.Such operational amplifier exports diode current flow when overturning by forward, by current feedback to operational amplifier negative input, operational amplifier is exported and reduces thus avoid operational amplifier to occur forward bias.Due to the employing of diode, the potential-divider network of opamp input terminal is vital, and here, the forward Input voltage terminal 3.92k Ω of operational amplifier and the resistor of 500 Ω carry out dividing potential drop to obtain input voltage.Such as: operational amplifier forward input voltage is-1.7V, the forward voltage due to diode is about 0.6V, so will make diode current flow when operational amplifier exports for during-1.1V, if this is the case, attenuator will not reach maximum attenuation value.In order to ensure the 30dB Regime during recession scope of VCA, must ensure that V1 is between 0V and-3V, V2 is between-2.5V and-0.6V.In addition, it should be noted that VCA when high band can by stray inductance impact and make decay Quality Down, and if RF signal there is potential direct current signal, then must RF input end adopt every straight process.

Realize precise hard_drawn tuhes, the problem that first will solve is STC damping capacity and controls the corresponding relation of electric current and control the corresponding relation of data in electric current and LPM_ROM storer.In LPM_ROM storer, data by C language programming realization, can revise adjustment to the data in LPM_ROM repeatedly, make STC damping capacity Step wise approximation and finally reach requirement.In order to make decay continuity, need 30dB (maximum attenuation amount) to be divided into 100 unit, each attenuation gradient is 0.3dB.D/A converter is the controlled quentity controlled variable (as voltage, electric current etc.) one group of 12 bit code conversion that LPM_ROM exports being become simulation, and the major parameter of D/A converter is precision and speed.In principle, as long as figure place is abundant, precision is just higher.The design have selected the AD9762 of AD company, figure place 12.

In the design process, utilize the S parameter that Hittile company provides, carried out matched design in conjunction with ADS software for circuit, under 50 Ω input and output characteristic impedances, its transmission line live width is 23.046mil, and sheet material specific inductive capacity is 3.48, and thickness of slab is 0.254mm.According to method for designing and the requirement of above introduction, devise an X-band broadband voltage controlled attenuator, and debug side circuit, test result is consistent with designing requirement.

As shown in Figure 2, concrete steps of the present invention are as follows:

Step 1: receiver protection pulse and system clock two signals are inputed to FPGA;

Step 2:FPGA is according to radar signal decays amount and the relational expression of time

$D=-40\lg \frac{t}{t_0}$

12 binary codes corresponding to radar signal decays amount are saved as .MIF file, calls in the LPM_ROM of FPGA; Under receiver protection pulse action, to system clock counting, count value as address, to LPM_ROM addressing; Wherein t ₀for decaying release time;

Step 3:DAC converter becomes the controlled quentity controlled variable electric current of simulation one group of 12 bit code conversion that LPM_ROM exports, and the relation of its output current and binary code is as follows:

IOUTA＝(DACCODE/4096)×32×V _REFIO/R _SET

IOUTB＝(4095-DACCODE)/4096×32×V _REFIO/R _SET

Wherein IOUTA is the anode of output current, and IOUTB is the negative terminal of output current, V _rEFIOthe reference voltage of DAC converter, R _sETit is the full inclined output current regulating resistance of DAC converter;

Step 4: amplifier modulate circuit exports to electrically controlled attenuator after the controlled quentity controlled variable current conversion of output is become voltage;

Step 5: electrically controlled attenuator is according to the magnitude of voltage of input, and the signal to signal source is decayed according to the magnitude of voltage of electrically controlled attenuator and the relation table of pad value;

Step 6: the signal after decay is input to oscillograph after amplifying, carrying out mixing and filtering with local oscillation signal.

Claims (3)

1. an adjustable attenuation method for digital STC attenuator circuit, described digital STC attenuator circuit comprises FPGA, DAC converter, amplifier modulate circuit, electrically controlled attenuator, amplifier, frequency mixer and wave filter, it is characterized in that step is as follows:

Step 1: receiver protection pulse and system clock two signals are inputed to FPGA;

Step 2:FPGA is according to radar signal decays amount and the relational expression of time

$D=-40\lg \frac{t}{t_0}$

12 binary codes corresponding to radar signal decays amount are saved as .MIF file, calls in the LPM_ROM of FPGA; Under receiver protection pulse action, to system clock counting, count value as address, to LPM_ROM addressing; Wherein t ₀for decaying release time;

Step 3:DAC converter becomes the controlled quentity controlled variable electric current of simulation one group of 12 bit code conversion that LPM_ROM exports, and the relation of its output current and binary code is as follows:

IOUTA＝(DACCODE/4096)×32×V _REFIO/R _SET

IOUTB＝(4095-DACCODE)/4096×32×V _REFIO/R _SET

Wherein IOUTA is the anode of output current, and IOUTB is the negative terminal of output current, V _rEFIOthe reference voltage of DAC converter, R _sETit is the full inclined output current regulating resistance of DAC converter;

Step 4: amplifier modulate circuit exports to electrically controlled attenuator after the controlled quentity controlled variable current conversion of output is become voltage;

Step 5: electrically controlled attenuator is according to the magnitude of voltage of input, and the signal to signal source is decayed according to the magnitude of voltage of electrically controlled attenuator and the relation table of pad value;

Step 6: the signal after decay is input to oscillograph after amplifying, carrying out mixing and filtering with local oscillation signal.

2. the adjustable attenuation method of digital STC attenuator circuit according to claim 1, its feature adopts the HMC346MS8G of Hittite company at described electrically controlled attenuator.

3. the adjustable attenuation method of digital STC attenuator circuit according to claim 1, its feature adopts the AD9762 of AD company at described DAC converter.