CN104241281A

CN104241281A - Integrated circuit and manufacturing method thereof

Info

Publication number: CN104241281A
Application number: CN201310243253.7A
Authority: CN
Inventors: 黄河; 克里夫·德劳利
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; China Core Integrated Circuit Ningbo Co Ltd
Priority date: 2013-06-18
Filing date: 2013-06-18
Publication date: 2014-12-24
Anticipated expiration: 2033-06-18
Also published as: CN104241281B

Abstract

The invention provides an integrated circuit and a manufacturing method thereof, and relates to the technical field of semiconductors. According to the integrated circuit, a first set of transistors with different side walls, a second set of transistors with different side walls, a third set of transistors with different side walls, an integrated passive device, MEMS devices and other components are integrated to one chip through the wafer processing flow, and compared with an existing radio frequency front-end module manufactured through the system integration packaging technology, the integrated circuit is higher in signal to noise ratio, lower in power consumption, smaller in device size and lower in cost. The manufacturing method of the integrated circuit is used for manufacturing the integrated circuit, and besides the advantages of the manufactured integrated circuit, the packaging complexity and manufacturing cost of a final radio frequency front-end module can be lowered.

Description

A kind of integrated circuit and manufacture method thereof

Technical field

The present invention relates to technical field of semiconductors, in particular to a kind of integrated circuit and manufacture method thereof.

Background technology

In technical field of semiconductors, RF front-end module (Radio Frequency Frond-EndModule is called for short RF FEM) is the key component in Wireless Telecom Equipment (such as mobile phone, panel computer etc.).In the prior art, RF front-end module (RF FEM) is realized by system in package (SiP) by multiple different chip usually.Generally speaking, RF front-end module (RF FEM) generally includes the different chips such as power amplifier core (Power amplifier core), power amplifier controller (PA controller), tuner (Tuners), radio-frequency (RF) switch (RFswitch), filter (Filters), duplexer (Duplexer) and comprises other chips of envelope detected (envelope tracking) chip.Wherein, power amplifier core adopts GaAs (GaAs) chip or high voltage (HV) and power (POWER) CMOS (Complementary Metal Oxide Semiconductor) (CMOS) chip usually; Power amplifier controller adopts CMOS chip usually, tuner adopts radio-frequency (RF) CMOS chip usually, radio-frequency (RF) switch adopts silicon-on-insulator mos field effect transistor (SOI MOS) usually, filter adopts radio frequency integrated passive devices (RF IPD) usually, duplexer adopts MEMS (micro electro mechanical system) (MEMS) usually, and other chips (as envelope detected chip) adopt CMOS chip usually.

But in the prior art, RF front-end module (RF FEM) is owing to being obtained through system in package (SiP) by multiple different chip, and the interconnection of each chip chamber in system in package, often adopts terminal conjunction method (Wire bonding) to realize.Therefore, existing RF front-end module (RF FEM) has the shortcomings such as module size is large, signal to noise ratio (snr) is low, power consumption is large.In addition, manufacture the method (that is, system-in-a-package method) of RF front-end module and often have that process complexity is high, high in cost of production shortcoming.

Therefore, in order to solve the problem, the present invention proposes a kind of new integrated circuit and manufacture method thereof.

Summary of the invention

For the deficiencies in the prior art, the invention provides a kind of integrated circuit and manufacture method thereof, realized the part or all of function of RF front-end module of the prior art (RF FEM) by one chip.

The embodiment of the present invention one provides a kind of integrated circuit, a kind of integrated circuit, it is characterized in that, comprise: first group transistor in the first Semiconductor substrate, the first area laying respectively at the first surface of described first Semiconductor substrate, second area and the 3rd region, the second group transistor and the 3rd group transistor and the first body dielectric layer be positioned on the second surface of described first Semiconductor substrate, wherein

By being positioned at first group of shallow trench isolation of described first Semiconductor substrate from isolated between each transistor in described first group transistor of described first area, wherein said first group of shallow trench isolation is the first distance from the side of the described second surface near described first Semiconductor substrate apart from the distance of the described first surface of described first Semiconductor substrate;

Being isolated by the first group of deep trench isolation being positioned at described first Semiconductor substrate between each transistor in described second group transistor of described second area, the distance of wherein said first group of deep trench isolation near the side of the described second surface of described first Semiconductor substrate apart from the described first surface of described first Semiconductor substrate is second distance;

By being positioned at second group of shallow trench isolation of the first Semiconductor substrate from isolated between each transistor in described 3rd group transistor in described 3rd region, wherein said second group of shallow trench isolation is described first distance from the side of the described second surface near described first Semiconductor substrate apart from the distance of the described first surface of described first Semiconductor substrate;

Wherein, described second distance is greater than described first distance, and described second distance is less than or equal to the thickness of described first Semiconductor substrate.

Wherein, described first group transistor is low voltage mos transistor, and described second group transistor is high-voltage MOS transistor.Further, described second group transistor is laterally diffused MOS transistor.

Wherein, described 3rd group transistor is complete depletion type MOS transistor.

Wherein, described first body dielectric layer also comprises and is positioned at the 4th region of described first Semiconductor substrate and the part in the 5th region, wherein, the part in described first body dielectric layer the 4th region and the 5th region that are positioned at described first Semiconductor substrate runs through described first Semiconductor substrate.

Wherein, described integrated circuit also comprises the four-range silicon through hole being positioned at described first Semiconductor substrate, and described silicon through hole runs through the four-range part that described first body dielectric layer is positioned at described first Semiconductor substrate.

Wherein, described integrated circuit also comprises and is positioned at the integrated passive devices that described first body dielectric layer is positioned at the top of the part in the 5th region of described first Semiconductor substrate.

Wherein, described integrated passive devices comprises electric capacity and/or inductance.

Wherein, described integrated circuit also comprises and is arranged at MEMS (micro electro mechanical system) (MEMS) device that described first body dielectric layer is positioned at the top of the four-range part of described first Semiconductor substrate and/or the part in the 5th region.

Wherein, described integrated circuit also comprises and is positioned at described first group transistor, described second group transistor and described 3rd group transistor MEMS (micro electro mechanical system) (MEMS) device at least above or below one of them.

Wherein, described integrated circuit also comprise be positioned at described first Semiconductor substrate first surface on the second Semiconductor substrate as carrier substrate, further, described integrated circuit also comprises MEMS (micro electro mechanical system) (MEMS) device be arranged in described second Semiconductor substrate.

The embodiment of the present invention two provides a kind of manufacture method of integrated circuit, and described method comprises:

Step S101: the first Semiconductor substrate is provided, formed respectively in the first area of described first Semiconductor substrate and the 3rd region first group of shallow trench isolation from second group of shallow trench isolation from, first group of deep trench isolation is formed at the second area of described first Semiconductor substrate, wherein, described first group of shallow trench isolation is the first distance from the side of the second surface relative with described first surface near described first Semiconductor substrate apart from the distance of the described first surface of described first Semiconductor substrate, described second group of shallow trench isolation is described first distance from the side of the described second surface near described first Semiconductor substrate apart from the distance of the described first surface of described first Semiconductor substrate, the distance of described first group of deep trench isolation near the side of the described second surface of described first Semiconductor substrate apart from the described first surface of described first Semiconductor substrate is second distance, described second distance is greater than described first distance,

Step S102: in the first area of described first Semiconductor substrate, second area and the 3rd region form the first group transistor, the second group transistor and the 3rd group transistor respectively, wherein, described first group transistor, the second group transistor and the 3rd group transistor are all positioned at the first surface side of described first Semiconductor substrate;

Step S103: form the first body dielectric layer on the second surface of described first Semiconductor substrate, described first body dielectric layer is positioned at the first area of described first Semiconductor substrate, second area is identical with the distance of described first surface with the part in the 3rd region.

Wherein, between described step S102 and described step S103, also step S1023 is comprised:

Carry out back-end process technique and form metal interconnect structure with the described first surface in described first Semiconductor substrate.

Wherein, also comprise the steps: between described step S1023 and described step S103

Step S10231: engage the second Semiconductor substrate as carrier substrate at the described first surface of described first Semiconductor substrate;

Step S10232: carrying out reduction processing to make the second surface of the first Semiconductor substrate after reduction processing to the described second surface of described first Semiconductor substrate is the 3rd distance apart from the distance of the first surface of described first Semiconductor substrate, and described 3rd distance is more than or equal to described second distance.

Wherein, in described step S101, the described first group of shallow trench isolation of formation from, described second group of shallow trench isolation from described first group of deep trench isolation before, the distance formed in described first Semiconductor substrate apart from the described first surface of described first Semiconductor substrate is the thinning stop-layer of described 3rd distance; In described step S10232, described reduction processing stops on described thinning stop-layer.

Wherein, the step forming described thinning stop-layer comprises: carry out non-Si ion implantation from the described second surface of described first Semiconductor substrate to described first Semiconductor substrate and form non-silicon sheath with the second depth location in described first Semiconductor substrate, and wherein said non-silicon ion comprises oxonium ion, carbon ion, Nitrogen ion or at least both combination among them.

Wherein, also comprise after the step of described formation non-silicon sheath, described first Semiconductor substrate is carried out to the step of high-temperature process.

Wherein, in described step S103, described first body dielectric layer also comprises and is positioned at the 4th region of described Semiconductor substrate and the part in the 5th region, and described step S103 comprises:

Step S1031: etch described first Semiconductor substrate, to form the first groove of described first Semiconductor substrate run through through reduction processing in the 4th region of described first Semiconductor substrate and the 5th region;

Step S1032: filled dielectric material in described first groove also carries out planarization, to form the first body dielectric layer being positioned at described first area, second area, the 3rd region, the 4th region and the 5th region.

Wherein, after described step S103, also step S104 is comprised:

Form silicon through hole in the 4th region of described first Semiconductor substrate, described silicon through hole runs through the four-range part that described first body dielectric layer is positioned at described first Semiconductor substrate.

Wherein, after described step S104, also step S105 is comprised:

Integrated passive devices is formed above the part being positioned at the 5th region of described first Semiconductor substrate at described first body dielectric layer.

Wherein, after described step S103, also step S104 ' is comprised:

Be positioned at above the four-range part of described first Semiconductor substrate and/or the part in the 5th region at described first body dielectric layer and form MEMS (micro electro mechanical system) (MEMS) device.

Wherein, after described step S103, also step S104 ' ' is comprised:

MEMS (micro electro mechanical system) (MEMS) device is formed above described first group transistor, described second group transistor and described 3rd group transistor at least one of them.

Wherein, in described step S10231, in described second Semiconductor substrate, be formed with MEMS (micro electro mechanical system) (MEMS) device.

Integrated circuit of the present invention, compared with the RF front-end module (RF FEM) passed through in prior art made by system Integration in Package, has higher signal to noise ratio (snr), lower power consumption, less device size and lower cost.The manufacture method of integrated circuit of the present invention, can reduce encapsulation complexity and manufacturing cost, and the integrated circuit manufactured by the method, compared with RF front-end module of the prior art, has the advantages such as signal to noise ratio is high, low in energy consumption, device size is little.

Accompanying drawing explanation

Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.

In accompanying drawing:

Figure 1A is a kind of schematic cross sectional views of the structure of a kind of integrated circuit of the embodiment of the present invention one;

Figure 1B is the another kind of schematic cross sectional views of the structure of a kind of integrated circuit of the embodiment of the present invention one;

Fig. 2 A to 2J is the schematic cross sectional views of the figure that the correlation step of the manufacture method of a kind of integrated circuit of the embodiment of the present invention two is formed;

Fig. 3 is a kind of indicative flowchart of the manufacture method of a kind of integrated circuit of the embodiment of the present invention two;

Fig. 4 is the another kind of indicative flowchart of the manufacture method of a kind of integrated circuit of the embodiment of the present invention two.

Embodiment

In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.

Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.

Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.

Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.

The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.

Here with reference to the cross-sectional view as the schematic diagram of desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, it is expected to the change from shown shape because such as manufacturing technology and/or tolerance cause.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to such as manufacturing the form variations caused.Such as, the injection region being shown as rectangle has round or bending features and/or implantation concentration gradient usually at its edge, instead of the binary from injection region to non-injection regions changes.Equally, by inject formed disposal area this disposal area and injection can be caused to carry out time process surface between district some inject.Therefore, the district shown in figure is in fact schematic, and their shape is not intended the true form in the district of display device and is not intended to limit scope of the present invention.

In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain integrated circuit and the manufacture method thereof of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.

Embodiment one

Below, the structure of the integrated circuit that the embodiment of the present invention proposes is described with reference to Figure 1A and Figure 1B.Wherein, Figure 1A is a kind of schematic cross sectional views of the structure of a kind of integrated circuit of the embodiment of the present invention, and Figure 1B is the another kind of schematic cross sectional views of the structure of a kind of integrated circuit of the embodiment of the present invention one.

The present embodiment provides a kind of integrated circuit, and it can as the RF front-end module of the communication equipments such as mobile phone (RF FEM).As shown in Figure 1A, the integrated circuit of the present embodiment comprises: the first Semiconductor substrate 100, be positioned at the first body dielectric layer 1001 in the first Semiconductor substrate 100 and be positioned at the first Semiconductor substrate 100 first area the first group transistor 1102, be positioned at the second group transistor 1202 of the second area of the first Semiconductor substrate 100 and be positioned at the 3rd group transistor 1302 in the 3rd region of the first Semiconductor substrate 100.Wherein, the first group transistor 1102 is core MOS transistor (Core MOS), is generally low voltage mos transistor, and the second group transistor 1202 is high-voltage MOS transistor (HV MOS), and the 3rd group transistor 1302 is complete depletion type MOS transistor (FD MOS).Further, the second group transistor is ldmos transistor (that is, laterally diffused MOS transistor).In the present embodiment, the first group transistor 1102, second group transistor 1202 and the 3rd group transistor 1302 include multiple transistor, concise and to the point in order to what represent, and every group transistor schematically show only one in figure ia.Wherein, the 3rd group transistor 1302 can be silicon-on-insulator (SOI) transistor.

In the present embodiment, by being positioned at the first area of the first Semiconductor substrate 100 and first group of shallow trench isolation with the first depth H 1 isolated from (STI) 1101 between each transistor in first group transistor 1102, the part that bottom is positioned at described first area by the first body dielectric layer 1001 isolated; Be positioned at the second area of the first Semiconductor substrate 100 between each transistor in second group transistor 1202 and have first group of deep trench isolation (DTI) 1201 of the second depth H 2 isolate, the part that bottom is positioned at described second area by described first body dielectric layer 1001 isolated; Be positioned at the 3rd region of the first Semiconductor substrate 100 between each transistor in 3rd group transistor 1302 and second group of shallow trench isolation with the first depth H 1 from (STI) 1301 isolate, the part that bottom is positioned at described 3rd region by described first body dielectric layer 1001 isolated.In the present embodiment, the second depth H 2 is greater than the thickness that the first depth H 1, second depth H 2 is less than or equal to the first Semiconductor substrate 100.Further, the second surface that described first body dielectric layer 1001 is positioned at the part of first area, the part of second area and the part in the 3rd region are all positioned at the first Semiconductor substrate 100.Wherein, first group of shallow trench isolation can be considered as the isolated side wall (abbreviation sidewall) of each group transistor from (STI) 1101, first group of deep trench isolation (DTI) 1201 and second group of shallow trench isolation from (STI) 1301.First body dielectric layer 1001 can be considered as the bottom of each group transistor.That is, the first group transistor, the second group transistor, the 3rd group transistor have employed different lateral and bottom insulation.

In the present embodiment, the first surface (" front ") of the first Semiconductor substrate 100, refers to that the first Semiconductor substrate 100 is formed with the surface of transistor; Second surface (" back side or " reverse side "), then refer to another surface relative with " first surface " of the first Semiconductor substrate 100.And, in the present embodiment, " degree of depth " is exactly " distance " on ordinary meaning, the computational methods of " degree of depth " with the first surface of the first Semiconductor substrate 100 for reference, " certain one deck has the first depth H 1(or the second depth H 2) " refer to that the distance of the first surface of this layer of distance first Semiconductor substrate 100 is H1(or H2), specifically can see the sign of Figure 1A to H1 and H2, other situations are by that analogy.Specifically, in the present embodiment, first group of shallow trench isolation is " the first distance " H1 from the distance of 1101 first surfaces near the side of the second surface of the first Semiconductor substrate 100 apart from the first Semiconductor substrate 100; The distance of the first surface of first group of deep trench isolation 1201 near the side of the second surface of the first Semiconductor substrate 100 apart from the first Semiconductor substrate 100 is " second distance " H2; Second group of shallow trench isolation is also " the first distance " H1 from the distance of the first surface of (STI) 1301 near the side of the second surface of the first Semiconductor substrate 100 apart from the first Semiconductor substrate 100.

In the integrated circuit of the present embodiment, as shown in Figure 1A, the thickness of the Semiconductor substrate of the first group transistor 1102 region is identical with the thickness of the Semiconductor substrate of the second group transistor 1202 region, but the degree of depth of the first group of shallow trench isolation being arranged in the side of the different transistor of the first group transistor 1202 from 1101 is less than first group of deep trench isolation 1201 of the side being arranged in the different transistor of the second group transistor 1202.The thickness of the Semiconductor substrate of the 3rd group transistor 1302 region is less than the thickness of the thickness of the Semiconductor substrate of the first group transistor 1102 region and the Semiconductor substrate of the second group transistor 1202 region, and the second group of shallow trench isolation being arranged in the 3rd group transistor 1302 different crystal pipe side is identical from the degree of depth of 1101 with first group of shallow trench isolation from the degree of depth of 1301.

Exemplarily, the integrated circuit of the present embodiment also comprises the 4th group transistor 1402 in the 6th region being positioned at the first Semiconductor substrate 100, by being positioned at the 6th region of the first Semiconductor substrate 100 and the 3rd group of shallow trench isolation with first degree of depth isolated from (STI) 1401 between each transistor in 4th group transistor 1402, the part that bottom is positioned at the 6th region by the first body dielectric layer 1001 isolated, and the part that wherein the first body dielectric layer 1001 is positioned at the 6th region has the second depth H 2.Wherein, the structure of the 4th group transistor 1402 is identical with the first group transistor 1102, also for as core transistor device.In this example, because the structure of the 4th group transistor 1402 is identical with the first group transistor 1102, therefore, the 6th region can be considered as a part for first area.In the present embodiment, the top of the 4th group transistor 1402 can also be provided with MEMS (micro electro mechanical system) (MEMS) device 14031, particularly, MEMS (micro electro mechanical system) (MEMS) device 14031 can be arranged at the second body dielectric layer 1002 be positioned at above the first body dielectric layer 1001, as shown in Figure 1A.

The integrated circuit of the present embodiment further comprises the silicon through hole 1605 being positioned at the four-range silicon through hole (TSV) 1505 of the first Semiconductor substrate 100 and the 5th region of the first Semiconductor substrate 100, and silicon through hole 1505 and silicon through hole 1605 run through the first body dielectric layer 1001 and be arranged in the 4th region of the first Semiconductor substrate 100 and the part 1504 in the 5th region.Wherein, the part 1504 in the 4th region and the 5th region that the first body dielectric layer 1001 is positioned at the first Semiconductor substrate 100 runs through the first Semiconductor substrate 100, further, the upper and lower surface that the first body dielectric layer 1001 is positioned at the 4th region of the first Semiconductor substrate 100 and the part 1504 in the 5th region is in same level with the first surface (front) of the first Semiconductor substrate 100 and second surface (back side) respectively.In the present embodiment, the effect of silicon through hole 1505 and silicon through hole 1605 is that connection bit is in the device of the first Semiconductor substrate 100 first surface (front) and second surface (back side).Wherein, silicon through hole 1505 and silicon through hole 1605 can be all one or more, in order to represent concise and to the point, illustrate only a silicon through hole 1505 and a silicon through hole 1605 in Figure 1A.It should be explained that, the first body dielectric layer 1001 of the present embodiment comprise the 3rd region being positioned at the first Semiconductor substrate 100 part 1304, be positioned at the 4th region of the first Semiconductor substrate 100 and the part 1504 in the 5th region and be positioned at the part 1100 in other regions of the first Semiconductor substrate 100, as shown in Figure 1A.Further, 1100,1304 and 1504 is generally as a whole, and in Figure 1A, subregion illustrates just for convenience of description and explanation.

The integrated circuit of the present embodiment further comprises the integrated passive devices (IPD) in the 5th region being positioned at the first Semiconductor substrate 100, and this integrated passive devices comprises electric capacity 16061 and inductance 16062.In the present embodiment, integrated passive devices is positioned at the top that the first body dielectric layer 1001 is positioned at the part in the 5th region of the first Semiconductor substrate 100, as shown in Figure 1A.Wherein, electric capacity 16061 and inductance 16062 can be all one or more, in order to represent concise and to the point, illustrate only an inductance and an electric capacity in Figure 1A.In the present embodiment, integrated passive devices also can only comprise electric capacity or inductance, and for the quantity of electric capacity or inductance, the present embodiment does not limit.In the present embodiment, electric capacity 16061 is connected with the miscellaneous part of the first Semiconductor substrate 100 first surface (also claiming front or upper surface) by silicon through hole 1605, and when integrated passive devices does not comprise electric capacity 16061, silicon through hole 1605 can be omitted.

The integrated circuit of the present embodiment generally also comprise be positioned at the first Semiconductor substrate 100 first surface on the second Semiconductor substrate 103 as carrier substrate, second Semiconductor substrate 103 is generally bonded by adhesive layer 102 and the metal intermetallic dielectric layer or other retes being positioned at the first Semiconductor substrate 100 first surface, as shown in Figure 1A.Wherein, described second Semiconductor substrate 103 can as a part for the encapsulation of this integrated circuit.Certainly, the integrated circuit of the present embodiment also can not comprise the second Semiconductor substrate 103.

In the present embodiment, this integrated circuit also comprises back segment metal interconnect structure, pad structure (as pad 1507, pad 16071 and pad 16072 and be connected pad 1506 etc.) and the structure such as interlayer dielectric layer, metal intermetallic dielectric layer, as shown in Figure 1A.

In the present embodiment, this integrated circuit is except integrated first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and the assembly such as integrated passive devices and MEMS, all right other various assemblies integrated, do not limit at this.

Figure 1B shows the another kind of schematic cross sectional views of the structure of the integrated circuit of the embodiment of the present invention.The difference of the structure of the integrated circuit shown in the structure of this integrated circuit and Figure 1A is, MEMS (micro electro mechanical system) (MEMS) device 14032 included by this integrated circuit is arranged in the second Semiconductor substrate 103 as carrier substrate, as shown in Figure 1B.In embodiments of the present invention, MEMS (micro electro mechanical system) (MEMS) device is except can being arranged on the position shown in Figure 1A and Figure 1B, the position of other any appropriate can also be arranged at, such as: MEMS can be arranged in the dielectric layer (such as adhesive layer 102) between metal interconnect structure on the first surface of the first body Semiconductor substrate 100 and the second Semiconductor substrate 103, is arranged in other body dielectric layers (being generally interlayer dielectric layer or metal intermetallic dielectric layer) above the second body dielectric layer 1002.In fact, in the integrated circuit of the present embodiment, except the transistors such as formation first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 rete and formed metal interconnect structure (namely, metal interconnection layer) rete outside on other rete (being generally interlayer dielectric layer or metal intermetallic dielectric layer) or within all can MEMS be set, such as, MEMS can be positioned at described first group transistor, described second group transistor and described 3rd group transistor at least above or below one of them.Further, MEMS can be arranged at the regional comprising first area, second area, the 3rd region, the 4th region, the 5th region and the 6th region of the first Semiconductor substrate 100.About the annexation of miscellaneous part and the concrete manufacture method etc. of MEMS in the concrete structure of MEMS, MEMS and integrated circuit, those skilled in the art can select with reference to prior art according to actual needs, repeats no more herein.

The integrated circuit of the present embodiment, owing to being integrated with the first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and the assembly such as integrated passive devices and MEMS, therefore may be used for realizing RF front-end module (RFFEM) function.Wherein, first group transistor 1102 may be used for the function realizing power amplifier controller, second group transistor 1202 may be used for the function realizing power amplifier core, 3rd group transistor 1302 may be used for the function realizing radio-frequency (RF) switch, 4th group transistor 1402 may be used for the function realizing tuner, MEMS may be used for the function realizing duplexer, and integrated passive devices (such as electric capacity 16061 and inductance 16062) may be used for the function realizing filter.

The integrated circuit of the present embodiment, due between each group transistors such as the first group transistor 1102 by shallow trench isolation from or deep trench isolation (shallow trench isolation from or deep trench isolation can be considered as the sidewall of transistor) and the first body dielectric layer 1001 isolate, there is good noise isolation effect, the noise jamming between the different part in this integrated circuit can be avoided, make whole integrated circuit have higher signal to noise ratio (snr) on the whole.And RF front-end module of the prior art (RF FEM) is realized by system in package by multiple chip, the cabling of different chip chamber can cause the generation of noise, and often signal to noise ratio is lower.

In addition, the integrated circuit of the present embodiment obviously has less device size and lower power consumption and lower cost than by multiple chip by the RF front-end module that system in package realizes.Further, because the integrated circuit of the present embodiment to realize the function of RF front-end module by one chip form, the functions such as the many base band of multimode more comprehensively communication function can therefore be realized with comparalive ease.

In brief, integrated circuit of the present invention, first group transistor of different lateral and bottom insulation, the second group transistor, the 3rd group transistor and the assembly such as integrated passive devices and MEMS will be adopted, be integrated on one chip by wafer work flow, compared with the RF front-end module (RF FEM) passed through in prior art made by system Integration in Package, there is higher signal to noise ratio, lower power consumption, less device size and lower cost.

Embodiment two

Below, the detailed step of a manufacture method illustrative methods of the integrated circuit that the embodiment of the present invention proposes is described with reference to Fig. 2 A-Fig. 2 J and Fig. 3, Fig. 4.Wherein, Fig. 2 A to 2J is the schematic cross sectional views of the figure of the correlation step formation of the manufacture method of a kind of integrated circuit of the embodiment of the present invention; Fig. 3 is a kind of indicative flowchart of the manufacture method of a kind of integrated circuit of the embodiment of the present invention; Fig. 4 is the another kind of indicative flowchart of the manufacture method of a kind of integrated circuit of the embodiment of the present invention.

The manufacture method of the integrated circuit of the embodiment of the present invention, for the manufacture of the integrated circuit described in embodiment one, specifically comprises the steps:

Steps A 1: provide the first Semiconductor substrate 100, forms the thinning stop-layer 101 being parallel to the first Semiconductor substrate 100 surface in the first Semiconductor substrate 100.Wherein, thinning stop-layer 101 has depth H 2 in the first Semiconductor substrate 100.The figure formed, as shown in Figure 2 A.

In the present embodiment, the first surface (or " front ") of the first Semiconductor substrate 100, refers to that the first Semiconductor substrate 100 is formed with the surface of transistor (such as the first group transistor 1202); Second surface (" back side or " reverse side ") then refers to another surface relative with " first surface " of the first Semiconductor substrate 100.And, in the present embodiment, " degree of depth " is exactly " distance " on ordinary meaning, the computational methods of " degree of depth " with the first surface of the first Semiconductor substrate 100 for reference, " certain one deck has the second depth H 2 " refers to that the distance of the first surface of this layer of distance first Semiconductor substrate 100 is H2, specifically can see the sign of Fig. 2 A to H2, other situations (the such as degree of depth is the situation of H1) are by that analogy.

In the present embodiment, exemplary, the first Semiconductor substrate 100 comprises six regions such as first area, second area, the 3rd region, the 4th region, the 5th region and the 6th region, as shown in Figure 2 A.In fact, the first Semiconductor substrate 100 also can comprise and be less than six regions or the situation more than six regions.Regional is generally used for forming different devices, and certainly, certain two or more region wherein also can form identical device, does not limit at this.

In the present embodiment, the first Semiconductor substrate 100 generally adopts body silicon (bulk Si).Thinning stop-layer 101 and the horizontal separator of island 1300 all can adopt oxide (silica) or other suitable materials.Exemplary, thinning stop-layer 101 and the horizontal separator 1300 of island are silica.

Wherein, the method forming thinning stop-layer 101 can comprise: carry out non-Si ion implantation from the described second surface of the first Semiconductor substrate 100 to the first Semiconductor substrate 100 and form non-silicon sheath with the second depth H 2 position in the first Semiconductor substrate 100.Wherein, namely this non-silicon sheath can be used as thinning stop-layer 101.Wherein, described non-silicon ion comprises oxonium ion, carbon ion, Nitrogen ion or at least both combination among them.

Further, the step of described first Semiconductor substrate being carried out to high-temperature process can also be comprised after the step of described formation non-silicon sheath.

In the present embodiment, the effect of thinning stop-layer 101 be mainly as follow-up reduction processing carried out to the first Semiconductor substrate 100 time stop-layer.In the present embodiment, the processing step forming thinning stop-layer 101 can be omitted according to actual conditions.

Steps A 2: form shallow trench isolation from (STI) and deep trench isolation (DTI) in the first Semiconductor substrate 100.

Particularly, there is first group of shallow trench isolation of the first depth H 1 from 1101 in the formation of the first area of the first Semiconductor substrate 100, first group of deep trench isolation 1201 with the second depth H 2 is formed at the second area of the first Semiconductor substrate 100, there is second group of shallow trench isolation of the first depth H 1 from 1301 in the 3rd region formation of the first Semiconductor substrate 100, there is the 3rd group of shallow trench isolation of the first depth H 1 from 1401 in the 6th region formation of the first Semiconductor substrate 100, as shown in Figure 2 B.

Wherein, H2 is greater than H1.In the present embodiment, can first be formed first group of shallow trench isolation from 1101, second group of shallow trench isolation from 1301 and the 3rd group of shallow trench isolation from 1401, then form first group of deep trench isolation 1201.

In the present embodiment, first group of shallow trench isolation from 1101 near the side of the second surface of the first Semiconductor substrate 100 apart from the distance of the first surface of the first Semiconductor substrate 100 be " the first distance " H1(namely, first group of shallow trench isolation has the first depth H 1 from 1101); First group of deep trench isolation 1201 near the side of the second surface of the first Semiconductor substrate 100 apart from the distance of the first surface of the first Semiconductor substrate 100 be " second distance " H2(namely, first group of deep trench isolation 1201 has the second depth H 2); Second group of shallow trench isolation from (STI) 1301 near the side of the second surface of the first Semiconductor substrate 100 apart from the distance of the first surface of the first Semiconductor substrate 100 be also " the first distance " H1(namely, second group of shallow trench isolation has the first depth H 1 from 1301).Thinning stop-layer 101 is " second distance " H2 apart from the distance of the first surface of the first Semiconductor substrate 100.

In addition, in the present embodiment, the degree of depth of first group of deep trench isolation 1201 in the first Semiconductor substrate 100 formed also can be less than the degree of depth of thinning stop-layer 101 in the first Semiconductor substrate 100, but still need be greater than first group of shallow trench isolation from 1101, second group of shallow trench isolation from 1301 and the 3rd group of shallow trench isolation from 1401 degree of depth in the first Semiconductor substrate 100.Now the degree of depth of thinning stop-layer can be referred to as the 3rd degree of depth or the 3rd distance, and the 3rd degree of depth is greater than H2.

Steps A 3: in the first area of the first Semiconductor substrate 100, second area, the 3rd region and the 6th region form the first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 respectively, as shown in Figure 2 C.Wherein, the first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 are all positioned at the first surface side of the first Semiconductor substrate 100, as shown in Figure 2 C.

In the present embodiment, first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 include multiple transistor, concise and to the point in order to what represent, in Fig. 2 C and relevant drawings, every group transistor schematically show only a transistor.Further, in the present embodiment, do not limit the sequencing of formation first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402, those skilled in the art can select according to actual needs.

Wherein, first group transistor 1102 is core MOS transistor (Core MOS), be generally low voltage mos transistor, second group transistor 1202 is high-voltage MOS transistor (HVMOS), 3rd group transistor 1302 is complete depletion type MOS transistor (FD MOS), and the 4th group transistor 1402 is also core MOS transistor (Core MOS).Further, the second group transistor is ldmos transistor (that is, laterally diffused MOS transistor).Because the structure of the 4th group transistor 1402 is identical with the first group transistor 1102, therefore, the 6th region can be considered as a part for first area.In the present embodiment, comprise the step forming MEMS (micro electro mechanical system) (MEMS) device if follow-up, MEMS can be formed separately and do not formed above the first group transistor 1102 above the 4th group transistor 1402.

Wherein, be positioned at the first area of the first Semiconductor substrate 100 between each transistor in the first group transistor 1102 and first group of shallow trench isolation with the first depth H 1 from (STI) 1101 isolate; Be positioned at the second area of the first Semiconductor substrate 100 between each transistor in second group transistor 1202 and have first group of deep trench isolation (DTI) 1201 of the second depth H 2 isolate; Be positioned at the 3rd region of the first Semiconductor substrate 100 between each transistor in 3rd group transistor 1302 and second group of shallow trench isolation with the first depth H 1 from (STI) 1301 isolate; Be positioned at the 6th region of the first Semiconductor substrate 100 between each transistor in 4th group transistor 1402 and the 3rd group of shallow trench isolation with the first depth H 1 from (STI) 1401 isolate.

Steps A 4: carry out back-end process (BEOL) technique to form metal interconnect structure in the front of the first Semiconductor substrate 100, as shown in Figure 2 D.

Particularly, by back-end process (BEOL) technique of semiconductor device, in the first area of the first Semiconductor substrate 100, second area, the 3rd region, the 6th region, the 4th region and the 5th region form the first metal interconnect structure 1103, second metal interconnect structure 1203, the 3rd metal interconnect structure 1303, the 4th metal interconnect structure 1403, the 5th metal interconnect structure 1503 and the 6th metal interconnect structure 1603 respectively, as shown in Figure 2 D.Form the method for metal interconnect structure, various method of the prior art can be adopted.When forming metal interconnect structure, also need form the rete such as interlayer dielectric layer, metal level in the first Semiconductor substrate 100, repeating no more herein.

Steps A 5: engage the second Semiconductor substrate 103 be used for as carrier substrate (carrier substrate) at the first surface of the first Semiconductor substrate 100.Exemplarily, the second Semiconductor substrate 103 is bonded by adhesive layer 102 and the metal intermetallic dielectric layer being positioned at the first Semiconductor substrate 100 first surface, as shown in Figure 2 E.

Wherein, the material of adhesive layer 102 can be oxide skin(coating) or other suitable materials.Second Semiconductor substrate 103 can be various Semiconductor substrate, its role is to for carrying and supports the first Semiconductor substrate 100.Wherein, the second Semiconductor substrate 103 can be removed in subsequent technique, also can be retained.As retained, the second Semiconductor substrate 103 can as a part for the encapsulation of integrated circuit in subsequent encapsulating process.Using being retained as a part for the encapsulation of integrated circuit as the second Semiconductor substrate 103 of carrier substrate, material can being saved, reduce costs.

Steps A 6: reduction processing to the second depth H 2 is carried out to the second surface of the first Semiconductor substrate 100, as shown in Figure 2 F.

Wherein, second surface is the surface relative with first surface; Reduction processing to the second depth H 2 refers to that the thickness of the first Semiconductor substrate 100 after by reduction processing is identical with the second depth H 2.When being formed with thinning stop-layer 101 in the first Semiconductor substrate 100, preferably make reduction process stop on thinning stop-layer 101, that is, the part that the first Semiconductor substrate 100 is positioned on thinning stop-layer 101 is completely removed, as shown in Figure 2 F.

Steps A 7: form the first body dielectric layer 1001 in the first Semiconductor substrate 100, as shown in Figure 2 G.

Wherein, the first body dielectric layer 1001 comprises the part 1504 in the 4th region that is positioned at the first Semiconductor substrate 100 and the 5th region and is positioned at the part 1100 in other regions of the first Semiconductor substrate 100, as shown in Figure 2 G.1100 and 1504 is generally as a whole, and in Fig. 2 G, subregion illustrates just for convenience of description and explanation.

Wherein, the first body dielectric layer 1001 can be silica or other suitable materials; Preferably, the first body dielectric layer 1001 is silica.

In the present embodiment, the upper and lower surface that the first body dielectric layer is positioned at the part 1504 in the 4th region and the 5th region is in same level with the first surface (front) of the first Semiconductor substrate 100 through reduction processing and second surface (reverse side) respectively.

Exemplary, steps A 7 generally comprises following steps:

Steps A 701: etch the first Semiconductor substrate 100, forms the first groove of the first Semiconductor substrate 100 run through through reduction processing in the 4th region and the 5th region;

Steps A 702: filled dielectric material in the first groove also carries out planarization, to form the first body dielectric layer 1001.Wherein, dielectric material can be oxide.

Wherein, carry out planarization, specifically refer to, after filled dielectric material, planarization is carried out to the second surface of the first Semiconductor substrate 100.After planarization, the second surface of the first Semiconductor substrate 100 all cover by the first body dielectric layer 1001, as shown in Figure 2 G.Carrying out the technique of planarization, can be chemico-mechanical polishing (CMP) or additive method.

Steps A 8: formed and run through silicon through hole 1505 and the silicon through hole 1605 that the first body dielectric layer 1001 is positioned at the part 1504 in the 4th region and the 5th region, as illustrated in figure 2h.

Wherein, the effect of silicon through hole 1505 and silicon through hole 1605 is that connection bit is in the device of the first Semiconductor substrate 100 first surface and second surface.In the present embodiment, silicon through hole 1505 and silicon through hole 1605 can be all one or more, concise and to the point in order to what represent, and Fig. 2 H and follow-up other figures only show a silicon through hole 1505 and a silicon through hole 1605.

Steps A 9: form integrated passive devices (IPD) above the part being positioned at the 5th region at the first body dielectric layer 1001.Wherein, integrated passive devices comprises electric capacity and/or inductance element.

Exemplary, form electric capacity 16061 and inductance 16062 above the part being positioned at the 5th region as shown in figure 2i at the first body dielectric layer 1001, wherein, electric capacity 16061 is capacity plate antenna, comprises the top electrode and bottom electrode that are formed by metal level.Exemplary, electric capacity 16061 and inductance 16062 are formed at the second body dielectric layer 1002 be arranged in above the first body dielectric layer 1001.Wherein, electric capacity 16061 and inductance 16062 can be all one or more, in order to represent concise and to the point, illustrate only an inductance and an electric capacity in Fig. 2 I and relevant drawings.In the present embodiment, integrated passive devices also can only comprise electric capacity or inductance, and for the quantity of electric capacity or inductance, the present embodiment does not limit.In the present embodiment, electric capacity 16061 is connected with the miscellaneous part of the first Semiconductor substrate 100 first surface by silicon through hole 1605, and when integrated passive devices does not comprise electric capacity 16061, silicon through hole 1605 can be omitted.In this step, while formation integrated passive devices, the connection pad 1506 be positioned at above silicon through hole 1505 can also be formed.

Steps A 10: form the pad structure for connecting silicon through hole and integrated passive devices.

Exemplary, as shown in fig. 2j, form pad structure 1507,16071 and 16072, wherein, pad structure 1507 is for guiding the outside of integrated circuit into by silicon through hole 1505, pad structure 16071 is for guiding the outside of integrated circuit into by electric capacity 16061, pad structure 16072 is for guiding the outside of integrated circuit into by inductance 16062.

So far, complete the introduction of the correlation step of the manufacture method of the integrated circuit of the present embodiment, the follow-up manufacture that can be completed final integrated circuit by the step such as scribing, encapsulation, is repeated no more herein.

In the present embodiment, between steps A 7 and A10, the step (being denoted as steps A 8 ') that the first body dielectric layer 1001 is positioned at top formation MEMS (micro electro mechanical system) (MEMS) device of the four-range part of the first Semiconductor substrate 100 and/or the part in the 5th region can also be included in, exemplary, after steps A 8 before steps A 9, the MEMS 14031 forming the second body dielectric layer 1002 and be positioned at wherein, as shown in Fig. 2 I and 2J.Further, between steps A 7 and A10, the first group transistor 1102, second group transistor 1202 and the 3rd group transistor 1302 can also be included in and at least one of them top form the step (be denoted as steps A 8 ' ') of MEMS (micro electro mechanical system) (MEMS) device.Wherein, steps A 8 ' and steps A 8 ' ' can synchronous with steps A 8, can and steps A 9 is synchronous, can between steps A 8 and steps A 9, steps A 9 can be positioned at after, steps A 8 can also be positioned at before, the present embodiment does not limit this.In addition, in steps A 5, in the second Semiconductor substrate 103 provided, MEMS (micro electro mechanical system) (MEMS) device can also be formed with.Further, in steps A 5, can also in the dielectric layer (such as interlayer dielectric layer or metal intermetallic dielectric layer) first on metal interconnect structure or on form MEMS, the second Semiconductor substrate 103 of rejoining.In the present embodiment, after the transistors such as formation first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302 and the 4th group transistor 1402 and metal interconnect structure, on each interlayer dielectric layer or metal intermetallic dielectric layer or within all can form MEMS, such as, MEMS can be positioned at described first group transistor, described second group transistor and described 3rd group transistor at least above or below one of them.Further, the MEMS of formation can be positioned at the regional comprising first area, second area, the 3rd region, the 4th region, the 5th region and the 6th region of the first Semiconductor substrate 100.About the annexation of miscellaneous part and the concrete manufacture method etc. of MEMS in the concrete structure of MEMS, MEMS and integrated circuit, those skilled in the art can select with reference to prior art according to actual needs, repeats no more herein.

In addition, the manufacture method of the integrated circuit of the present embodiment, except comprising the step of formation first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and the assembly such as integrated passive devices and MEMS, the step forming other various assemblies can also be comprised, do not limit at this.

The integrated circuit obtained according to the manufacture method of the integrated circuit of the present embodiment, be integrated with the first group transistor 1102, second group transistor 1202, the 3rd group transistor 1302, the 4th group transistor 1402 and the assembly such as integrated passive devices and MEMS, may be used for realizing RF front-end module (RF FEM) function.

The manufacture method of the integrated circuit of the present embodiment, due to define shallow trench isolation from or deep trench isolation and the first body dielectric layer etc., can isolate between each assemblies such as the first group transistor 1102, thus can avoid the noise jamming between the different assembly in this integrated circuit, make whole integrated circuit have higher signal to noise ratio (snr) on the whole.And RF front-end module of the prior art (RF FEM) is realized by system in package by multiple chip, the cabling of different chip chamber can cause the generation of noise, and often signal to noise ratio is lower.

In addition, the integrated circuit that the manufacture method of the integrated circuit of the present embodiment is obtained, obviously has less device size and lower power consumption than by multiple chip by the RF front-end module that system in package realizes.And realize RF front-end module relative to the mode by system in package in prior art, the manufacture method of the integrated circuit of the present embodiment, owing to adopting the form of one chip to realize, the complexity of encapsulation will significantly be reduced, and thus manufacturing cost also can be reduced.

Generally, the manufacture method of the present embodiment integrated circuit, can reduce complexity and the manufacturing cost of encapsulation, and, integrated circuit obtained by the method, compared with RF front-end module of the prior art, has the advantages such as signal to noise ratio is high, low in energy consumption, device size is little.

Fig. 3 shows a kind of indicative flowchart of the manufacture method of a kind of integrated circuit that the embodiment of the present invention proposes, for schematically illustrating the typical process of this manufacture method.Specifically comprise:

Step S101: the first Semiconductor substrate is provided, formed respectively in the first area of described first Semiconductor substrate and the 3rd region the first group of shallow trench isolation with described first degree of depth from second group of shallow trench isolation from, first group of deep trench isolation with second degree of depth is formed at the second area of described first Semiconductor substrate, wherein, described second degree of depth is greater than described first degree of depth;

Fig. 4 shows the another kind of indicative flowchart of the manufacture method of a kind of integrated circuit that the embodiment of the present invention proposes, for relatively illustrating a kind of typical process of this manufacture method in detail.Specifically comprise:

Step S103: form the first body dielectric layer on the second surface of described first Semiconductor substrate;

Step S104: form silicon through hole in the 4th region of described first Semiconductor substrate, described silicon through hole runs through the four-range part that described first body dielectric layer is positioned at described first Semiconductor substrate;

Step S105: form integrated passive devices above the part being positioned at the 5th region of described first Semiconductor substrate at described first body dielectric layer.

The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims

1. an integrated circuit, it is characterized in that, comprise: first group transistor in the first Semiconductor substrate, the first area laying respectively at the first surface of described first Semiconductor substrate, second area and the 3rd region, the second group transistor and the 3rd group transistor and the first body dielectric layer be positioned on the second surface of described first Semiconductor substrate, wherein

2. integrated circuit as claimed in claim 1, it is characterized in that, described first group transistor is low voltage mos transistor, and described second group transistor is high-voltage MOS transistor.

3. integrated circuit as claimed in claim 1, it is characterized in that, described 3rd group transistor is complete depletion type MOS transistor.

4. integrated circuit as claimed in claim 2, it is characterized in that, described second group transistor is laterally diffused MOS transistor.

5. integrated circuit as claimed in claim 1, it is characterized in that, described first body dielectric layer also comprises and is positioned at the 4th region of described first Semiconductor substrate and the part in the 5th region, wherein, the part in described first body dielectric layer the 4th region and the 5th region that are positioned at described first Semiconductor substrate runs through described first Semiconductor substrate.

6. integrated circuit as claimed in claim 5, it is characterized in that, described integrated circuit also comprises the four-range silicon through hole being positioned at described first Semiconductor substrate, and described silicon through hole runs through the four-range part that described first body dielectric layer is positioned at described first Semiconductor substrate.

7. integrated circuit as claimed in claim 5, is characterized in that, described integrated circuit also comprises and is positioned at the integrated passive devices that described first body dielectric layer is positioned at the top of the part in the 5th region of described first Semiconductor substrate.

8. integrated circuit as claimed in claim 7, it is characterized in that, described integrated passive devices comprises electric capacity and/or inductance.

9. the integrated circuit as described in any one of claim 5 to 8, it is characterized in that, described integrated circuit also comprises and is arranged at MEMS (micro electro mechanical system) (MEMS) device that described first body dielectric layer is positioned at the top of the four-range part of described first Semiconductor substrate and/or the part in the 5th region.

10. the integrated circuit as described in any one of claim 1 to 8, it is characterized in that, described integrated circuit also comprises and is positioned at described first group transistor, described second group transistor and described 3rd group transistor MEMS (micro electro mechanical system) (MEMS) device at least above or below one of them.

11. integrated circuits as described in any one of claim 1 to 8, it is characterized in that, described integrated circuit also comprise be positioned at described first Semiconductor substrate first surface on the second Semiconductor substrate as carrier substrate, further, described integrated circuit also comprises MEMS (micro electro mechanical system) (MEMS) device be arranged in described second Semiconductor substrate.

The manufacture method of 12. 1 kinds of integrated circuits, is characterized in that, described method comprises:

The manufacture method of 13. integrated circuits as claimed in claim 12, it is characterized in that, described first group transistor is low voltage mos transistor, and described second group transistor is high-voltage MOS transistor.

The manufacture method of 14. integrated circuits as claimed in claim 12, is characterized in that, described 3rd group transistor is complete depletion type MOS transistor.

The manufacture method of 15. integrated circuits as claimed in claim 13, it is characterized in that, described second group transistor is laterally diffused MOS transistor.

The manufacture method of 16. integrated circuits as claimed in claim 12, is characterized in that, between described step S102 and described step S103, also comprise step S1023:

The manufacture method of 17. integrated circuits as claimed in claim 16, is characterized in that, also comprise the steps: between described step S1023 and described step S103

The manufacture method of 18. integrated circuits as claimed in claim 17, is characterized in that,

In described step S101, the described first group of shallow trench isolation of formation from, described second group of shallow trench isolation from described first group of deep trench isolation before, the distance formed in described first Semiconductor substrate apart from the described first surface of described first Semiconductor substrate is the thinning stop-layer of described 3rd distance;

In described step S10232, described reduction processing stops on described thinning stop-layer.

The manufacture method of 19. integrated circuits as claimed in claim 18, it is characterized in that, the step forming described thinning stop-layer comprises: carry out non-Si ion implantation from the described second surface of described first Semiconductor substrate to described first Semiconductor substrate and form non-silicon sheath with the second depth location in described first Semiconductor substrate, and wherein said non-silicon ion comprises oxonium ion, carbon ion, Nitrogen ion or at least both combination among them.

The manufacture method of 20. integrated circuits as claimed in claim 19, is characterized in that, also comprises, described first Semiconductor substrate is carried out to the step of high-temperature process after the step of described formation non-silicon sheath.

The manufacture method of 21. integrated circuits as claimed in claim 12, is characterized in that,

In described step S103, described first body dielectric layer also comprises and is positioned at the 4th region of described Semiconductor substrate and the part in the 5th region, and described step S103 comprises:

The manufacture method of 22. integrated circuits as claimed in claim 21, is characterized in that, after described step S103, also comprise step S104:

The manufacture method of 23. integrated circuits as claimed in claim 22, is characterized in that, after described step S104, also comprise step S105:

The manufacture method of 24. integrated circuits as claimed in claim 23, it is characterized in that, described integrated passive devices comprises electric capacity and/or inductance.

The manufacture method of 25. integrated circuits as claimed in claim 22, is characterized in that, after described step S103, also comprise step S104 ':

The manufacture method of 26. integrated circuits as described in any one of claim 12 to 21, is characterized in that, after described step S103, also comprise step S104 ' ':

The manufacture method of 27. integrated circuits as claimed in claim 17, is characterized in that, in described step S10231, is formed with MEMS (micro electro mechanical system) (MEMS) device in described second Semiconductor substrate.