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CN104218832A - Single-phase five-level topology and inverter - Google Patents

Single-phase five-level topology and inverter Download PDF

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Publication number
CN104218832A
CN104218832A CN201310211740.5A CN201310211740A CN104218832A CN 104218832 A CN104218832 A CN 104218832A CN 201310211740 A CN201310211740 A CN 201310211740A CN 104218832 A CN104218832 A CN 104218832A
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China
Prior art keywords
switching tube
phase
tube
switching
switch
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Granted
Application number
CN201310211740.5A
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Chinese (zh)
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CN104218832B (en
Inventor
邹海晏
陶磊
张建
王艾
胡勇
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Sungrow Power Supply Co Ltd
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Sungrow Power Supply Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a single-phase five-level topology and an inverter. The single-phase five-level topology comprises a first capacitor, a three-level bridge arm module and four switching tubes, wherein the four switching tubes refer to a first switching tube, a fifth switching tube, a sixth switching tube and an eighth switching tube respectively; each switching tube is reversely connected in parallel with a diode; the three-level bridge arm module comprises two switching tubes and a double-switch unit; the first end of a third switching tube is connected with a first node, and the second end of the third switching tube is connected with a neutral point N through the double-switch unit; and the first end of a fourth switching tube is connected with N through the double-switch unit, and the second end of the fourth switching tube is connected with a second node. Five level states are output, the current harmonic content of a system is reduced, the filter inductance is reduced, the voltage level is raised, the common-mode voltage is restrained, and the running efficiency is increased. Balanced control of capacitor voltage under full power and full modulation can be realized without adding an additional hardware circuit, and the phase output voltage of the system is prevented from degrading from five levels to three levels.

Description

Single-phase five-level topology and inverter
Technical Field
The invention relates to the technical field of power electronics, in particular to a single-phase five-level topology and an inverter.
Background
In the new energy fields of solar power generation, wind power generation and the like, the multilevel inverter is increasingly emphasized due to the characteristics of high output power, low device switching frequency, high system equivalent switching frequency, small output harmonic, fast dynamic response, wide transmission frequency band, good electromagnetic compatibility and the like. Many of the multilevel circuits currently under study are diode clamped multilevel circuits. The diode-embedded three-level circuit is successfully applied to the fields of photovoltaic inverters and fan converters.
However, diode-clamped four-level and above inverter uses a plurality of capacitors connected in series across the dc side. Each switching tube in the inverter is connected with a corresponding capacitor through a power diode in sequence, unequal power output from the capacitors causes unequal voltages on the capacitors, namely the problem of capacitor voltage imbalance occurs, so that the phenomenon that a higher level is degraded to a lower level, for example, the degradation from a five level to a three level is easy to occur.
In the prior art, an additional hardware circuit needs to be added or the voltage utilization rate of the inverter needs to be sacrificed to realize the balance of the capacitor voltage.
Therefore, how to provide a five-level inverter topology capable of keeping the capacitor voltage balance without adding additional hardware circuits or sacrificing the inverter voltage utilization rate is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a single-phase five-level topology and an inverter, which can keep the capacitor voltage balanced without additionally increasing a hardware circuit or sacrificing the voltage utilization rate of the inverter.
The invention provides a single-phase five-level topology, comprising: the circuit comprises a first capacitor, a three-level bridge arm module and four switching tubes, wherein the four switching tubes are respectively a first switching tube, a fifth switching tube, a sixth switching tube and an eighth switching tube; each switching tube is reversely connected with a diode in parallel;
the first end of the first switch tube is connected with the anode of a direct-current power supply, and the second end of the first switch tube is connected with the first node;
a second end of the eighth switching tube is connected with a negative electrode of the direct-current power supply, and a first end of the eighth switching tube is connected with the second node; two ends of the first capacitor are respectively connected with a first node and a second node;
a first end of the fifth switching tube is connected with the first node, and a second end of the fifth switching tube is connected with the output end of the inverter;
a first end of the sixth switching tube is connected with the output end of the inverter, and a second end of the sixth switching tube is connected with the second node;
the three-level bridge arm module comprises two switching tubes and a double-switching unit, wherein the two switching tubes are respectively a third switching tube and a fourth switching tube;
the first end of the third switching tube is connected with the first node, and the second end of the third switching tube is connected with a neutral point N through the double switching units; the first end of the fourth switch tube is connected with the N through the double switch units, and the second end of the fourth switch tube is connected with the second node.
Preferably, the dual-switch unit comprises a second switch tube, a seventh switch tube, a first diode and a second diode; the double-switch unit is provided with three nodes which are connected with the outside, namely a third node, a fourth node and the N;
the anode of the first diode is connected with the N, and the cathode of the first diode is connected with the third node;
a first end of the seventh switching tube is connected with the third node, and a second end of the third switching tube is connected with the third node;
the anode of the second diode is connected with a fourth node, and the cathode of the second diode is connected with the N;
the first end of the second switch tube is connected with the second end of the seventh switch tube, the second end of the second switch tube is connected with the fourth node, and the first end of the fourth switch tube is connected with the fourth node.
Preferably, the dual switching unit includes a second switching tube and a seventh switching tube; the second switching tube and the seventh switching tube are connected with a diode in parallel in a reverse direction;
the first end of the second switching tube is connected with the second end of a third switching tube, and the second end of the third switching tube is connected with the first end of the fourth switching tube;
the first end of the seventh switch tube is connected with the N, and the second end of the seventh switch tube is connected with the second end of the second switch tube.
Preferably, the dual-switch unit comprises a second switch tube, a first diode, a second diode, a third diode and a fourth diode;
the anode of the first diode is connected with the N, and the cathode of the third diode is connected with the N;
the cathode of the first diode is connected with the cathode of the second diode, the anode of the second diode is connected with the second end of the third switching tube, and the second end of the third switching tube is connected with the first end of the fourth switching tube;
the anode of the third diode is connected with the anode of the fourth diode, and the cathode of the fourth diode is connected with the anode of the second diode;
the first end of the second switch tube is connected with the cathode of the first diode, and the second end of the second switch tube is connected with the anode of the third diode.
Preferably, the first and second electrodes are formed of a metal,
the driving signal logics of the first switching tube and the second switching tube are opposite;
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the driving signal logics of the seventh switching tube and the eighth switching tube are opposite.
Preferably, the first and second electrodes are formed of a metal,
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the logic phase of the driving signal of the first switching tube and the eighth switching tube is opposite to the logic phase of the driving signal of the second switching tube.
Preferably, the eight working modes corresponding to the single-phase five-level inverter are respectively:
a first mode of operation: the first switch tube, the fourth switch tube, the fifth switch tube and the seventh switch tube are switched on, and the other switch tubes are all switched off;
the second working mode is as follows: the second switching tube, the fourth switching tube, the fifth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
the third working mode is as follows: the first switch tube, the fourth switch tube, the sixth switch tube and the seventh switch tube are all switched on, and the other switch tubes are all switched off;
the fourth working mode: the second switching tube, the fourth switching tube, the sixth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a fifth working mode: the second switching tube, the third switching tube, the fifth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a sixth working mode: the second switching tube, the third switching tube, the sixth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a seventh working mode: the second switching tube, the third switching tube, the fifth switching tube and the eighth switching tube are all switched on, and the other switching tubes are all switched off;
the eighth working mode: the second switch tube, the third switch tube, the sixth switch tube and the eighth switch tube are all switched on, and the rest switch tubes are all switched off.
Preferably, a second capacitor and a third capacitor are further included;
two ends of the second capacitor are respectively connected with the positive electrode of the direct current power supply and the N;
and two ends of the third capacitor are respectively connected with the negative electrode of the direct current power supply and the N.
The embodiment of the invention also provides a five-level inverter, which comprises three single-phase five-level topologies, namely a first single-phase five-level topology, a second single-phase five-level topology and a third single-phase five-level topology; the capacitor further comprises a second capacitor and a third capacitor;
the first ends of the first switching tubes in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are connected together and are connected with the positive end of the direct-current power supply;
second ends of eighth switching tubes in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are connected together and are connected with a negative end of direct-current voltage;
the N in the three-level bridge arm modules in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are all connected with the common end of the second capacitor and the common end of the third capacitor;
and the output ends of the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are respectively used as three alternating current output ends of the five-level inverter.
The embodiment of the invention also provides a multi-phase five-level inverter, which comprises a plurality of single-phase five-level topologies; the capacitor further comprises a second capacitor and a third capacitor;
the first ends of the first switching tubes in each single-phase five-level topology are connected together and are connected with the positive end of the direct-current power supply;
the second ends of the eighth switching tubes in each single-phase five-level topology are connected together and are connected with the negative end of the direct-current voltage;
the N in the three-level bridge arm module in each single-phase five-level topology is connected with the common end of the second capacitor and the common end of the third capacitor;
and the output end of each single-phase five-level topology is respectively used as the alternating current output end of the five-level inverter, and each alternating current output end is mounted with a load.
Compared with the prior art, the invention has the following advantages:
the single-phase five-level topology and the inverter provided by the embodiment of the invention can output five level states, thereby reducing the current harmonic content of the system, reducing the filter inductance of the system, improving the voltage level of the system, suppressing the common-mode voltage of the system, improving the operating efficiency of the system and reducing the hardware cost of the system. And the balance control of the capacitor voltage under full power and full modulation can be realized by selecting the conduction sequence of the switching tubes without adding an additional hardware circuit, so that the phase output voltage of the system is prevented from being degenerated from five levels to three levels.
Drawings
FIG. 1 is a schematic diagram of a single-phase five-level topology according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a second embodiment of a single-phase five-level topology provided by the present invention;
FIG. 3 is a third schematic diagram of an embodiment of a single-phase five-level topology provided by the present invention;
FIG. 4 is a diagram of a single-phase five-level topology according to an embodiment of the present invention;
fig. 5a is a schematic view of the first mode of operation of fig. 2;
FIG. 5b is a schematic view of the second mode of operation of FIG. 2;
fig. 5c is a schematic view of the third mode of operation of fig. 2;
FIG. 5d is a schematic view of the fourth mode of operation of FIG. 2;
fig. 5e is a schematic view of the fifth mode of operation of fig. 2;
fig. 5f is a schematic view of a sixth mode of operation of fig. 2;
fig. 5g is a schematic view of the seventh mode of operation of fig. 2;
fig. 5h is a schematic view of an eighth mode of operation of fig. 2;
FIG. 6 is an equivalent schematic diagram of the single-phase five-level inverter shown in FIG. 2 according to the present invention;
FIG. 7 is an equivalent schematic diagram of a three-phase five-level inverter provided by the invention;
fig. 8 is an equivalent schematic diagram of the multiphase five-level inverter provided by the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, the figure is a schematic diagram of an embodiment of a single-phase five-level topology provided by the present invention.
It should be noted that fig. 1 is a schematic diagram of a single-phase half-bridge five-level topology.
The single-phase five-level topology provided by the embodiment comprises: the three-level bridge arm circuit comprises a first capacitor C1, a three-level bridge arm module and four switching tubes, wherein the four switching tubes are a first switching tube T1, a fifth switching tube T5, a sixth switching tube T6 and an eighth switching tube T8 respectively; each switching tube is reversely connected with a diode in parallel;
a first end of the first switch tube T1 is connected to the positive electrode + E of the dc power supply, and a second end of the first switch tube T1 is connected to the first node a;
a second terminal of the eighth switch transistor T8 is connected to the negative electrode-E of the dc power supply, and a first terminal of the eighth switch transistor T8 is connected to the second node B; two ends of the first capacitor C1 are respectively connected with a first node a and a second node B;
a first end of the fifth switching tube T5 is connected to the first node a, and a second end of the fifth switching tube T5 is connected to the output O of the inverter;
a first end of the sixth switching tube T6 is connected to the output O of the inverter, and a second end of the sixth switching tube T6 is connected to the second node B;
the three-level bridge arm module comprises two switching tubes and a double-switching unit 100, wherein the two switching tubes are respectively a third switching tube T3 and a fourth switching tube T4;
a first end of the third switching tube T3 is connected to the first node a, and a second end of the third switching tube is connected to a neutral point N through the double switching units; the first end of the fourth switch tube T4 is connected through the double switch units are connected with the N, and the second end of the fourth switch tube T4 is connected with the second node B.
The single-phase five-level topology provided by the embodiment can output five level states, so that the current harmonic content of the system is reduced, the filter inductance of the system is reduced, the voltage level of the system is improved, the common-mode voltage of the system is suppressed, the operating efficiency of the system is improved, and the hardware cost of the system is reduced. And the balance control of the capacitor voltage under full power and full modulation can be realized by selecting the conduction sequence of the switching tubes without adding an additional hardware circuit, so that the phase output voltage of the system is prevented from being degenerated from five levels to three levels.
The following describes a specific implementation of the dual switch unit in detail with reference to the accompanying drawings.
Referring to fig. 2, the figure is a schematic diagram of a single-phase five-level topology according to a second embodiment of the present invention.
In the single-phase five-level topology provided by the present embodiment, the dual-switch unit includes a second switch transistor T2, a seventh switch transistor T7, a first diode D1, and a second diode D2;
in this embodiment, the dual switch unit has three nodes connected to the outside, which are a third node C, a fourth node D, and a neutral point N;
the anode of the first diode D1 is connected with the N, and the cathode of the first diode D1 is connected with the third node C;
a first end of the seventh switching tube T7 is connected to the third node C, and a second end of the third switching tube T3 is connected to the third node C;
the anode of the second diode D2 is connected to the fourth node D, and the cathode of the second diode D2 is connected to the N;
a first terminal of the second switch transistor T2 is connected to a second terminal of a seventh switch transistor T7, a second terminal of the second switch transistor T2 is connected to the fourth node D, and a first terminal of the fourth switch transistor T4 is connected to the fourth node D.
Referring to fig. 3, the figure is a third schematic diagram of an embodiment of a single-phase five-level topology provided by the present invention.
In the single-phase five-level topology provided by this embodiment, the dual-switch unit 100 includes a second switch transistor T and a seventh switch transistor T7; the second switch tube T2 and the seventh switch tube T7 are connected in parallel with a diode in an opposite direction;
a first end of the second switching tube T2 is connected to a second end of a third switching tube T3, and a second end of the third switching tube T3 is connected to a first end of the fourth switching tube T4;
a first terminal of the seventh switch transistor T7 is connected to the N, and a second terminal of the seventh switch transistor T7 is connected to the second terminal of the second switch transistor T2.
Referring to fig. 4, the figure is a four-schematic diagram of an embodiment of a single-phase five-level topology provided by the present invention.
In the single-phase five-level topology provided by the embodiment, the two-switch unit includes a second switch transistor T2, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4; (ii) a
The anode of the first diode D1 is connected with the N, and the cathode of the third diode D3 is connected with the N;
a cathode of the first diode D1 is connected to a cathode of the second diode D2, an anode of the second diode D2 is connected to a second terminal of the third switching tube T3, and a second terminal of the third switching tube T3 is connected to a first terminal of the fourth switching tube T4;
the anode of the third diode D3 is connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is connected to the anode of the second diode D2;
a first terminal of the second switch tube T2 is connected to the cathode of the first diode D1, and a second terminal of the second switch tube T2 is connected to the anode of the third diode D3.
The above are three implementation manners of a single-phase five-level circuit provided by the embodiment of the present invention, and the specific operation mode of the single-phase five-level circuit is described below by taking the implementation manner shown in fig. 2 as an example.
The switching tube is an IGBT tube, an MOS tube, an IGCT tube, an IEGT tube, or the like;
it is understood that the diode connected in anti-parallel with the switching tube is a separate diode or a diode packaged with the switching tube. Before the inverter operates in the implementation shown in fig. 2, the first capacitor C1 (in fig. 2) in the single-phase five-level inverter should be charged to a magnitude of one fourth of the total dc power supply voltage.
It should be noted that the driving signals of the switching tubes in the above embodiments shown in fig. 2 and fig. 3 of the present invention are completely the same, specifically as follows:
the driving signal logics of the first switching tube and the second switching tube are opposite;
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the driving signal logics of the seventh switching tube and the eighth switching tube are opposite.
The above-mentioned driving signals have opposite logics, which means that when the driving signal of the first switching tube is at a high level, the driving signal of the second switching tube is at a low level, that is, the switching states of the first switching tube and the second switching tube are complementary.
The driving signals of each switching tube in the embodiment shown in fig. 4 of the present invention are specifically as follows:
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the logic phase of the driving signal of the first switching tube and the eighth switching tube is opposite to the logic phase of the driving signal of the second switching tube.
Referring to fig. 5a, a schematic view of the first mode of operation of fig. 2 is shown.
A first mode of operation: the first switch tube T1, the fourth switch tube T4, the fifth switch tube T5 and the seventh switch tube T7 are switched on, and the other switch tubes are all switched off;
in the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is C2 → T1 → T5 → L → Vac.
Reference is made to fig. 5b, which is a schematic view of the second mode of operation of fig. 2.
The second working mode is as follows: the second switch tube T2, the fourth switch tube T4, the fifth switch tube T5 and the seventh switch tube T7 are all turned on, and the other switch tubes are all turned off;
in the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is D1 → T7 → T2 → T4 → C1 → T5 → L → Vac or D2 → T4 → C1 → T5 → L → Vac.
Reference is made to fig. 5c, which is a schematic illustration of the third mode of operation of fig. 2.
The third working mode is as follows: the first switch tube T1, the fourth switch tube T4, the sixth switch tube T6 and the seventh switch tube T7 are all turned on, and the other switch tubes are all turned off;
in the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is C2 → T1 → C1 → T6 → L → Vac.
Reference is made to fig. 5d, which is a schematic illustration of the fourth mode of operation of fig. 2.
The fourth working mode: the second switch tube T2, the fourth switch tube T4, the sixth switch tube T6 and the seventh switch tube T7 are all turned on, and the other switch tubes are all turned off;
in the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is D1 → T7 → T2 → T4 → T6 → L → Vac or D2 → T4 → T6 → L → Vac.
Reference is made to fig. 5e, which is a schematic illustration of the fifth mode of operation of fig. 2.
A fifth working mode: the second switch tube T2, the third switch tube T3, the fifth switch tube T5 and the seventh switch tube T7 are all turned on, and the other switch tubes are all turned off;
the non-conducting paths are shown in the figure with a light solid line and the conducting paths with a dark solid line. The current path is D1 → T3 → T5 → L → Vac or D2 → T2 → T7 → T3 → T5 → L → Vac.
Reference is made to fig. 5f, which is a schematic illustration of the sixth mode of operation of fig. 2.
A sixth working mode: the second switch tube T2, the third switch tube T3, the sixth switch tube T6 and the seventh switch tube T7 are all turned on, and the other switch tubes are all turned off;
the non-conducting paths are shown in the figure with a light solid line and the conducting paths with a dark solid line. The current path is D1 → T3 → C1 → T6 → L → Vac or D2 → T2 → T7 → T3 → C1 → T6 → L → Vac.
Reference is made to fig. 5g, which is a schematic illustration of the seventh mode of operation of fig. 2.
A seventh working mode: the second switch tube T2, the third switch tube T3, the fifth switch tube T5 and the eighth switch tube T8 are all turned on, and the other switch tubes are all turned off;
in the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is C3 → T8 → C1 → T5 → L → Vac.
Reference is made to fig. 5h, which is a schematic illustration of the eighth operating mode of fig. 2.
The eighth working mode: the second switch tube T2, the third switch tube T3, the sixth switch tube T6 and the eighth switch tube T8 are all turned on, and the other switch tubes are all turned off.
In the figure, the non-conductive paths are shown by light solid lines, and the conductive paths are shown by dark solid lines. The current path is C3 → T8 → T6 → L → Vac.
In order to make those skilled in the art better understand the above eight working modes, the following description is given in conjunction with table 1.
Since T1, T3, T5 and T7 are logically opposite to the driving pulse signals of T2, T4, T6 and T8 respectively. For example, when T1 is turned on, T2 is turned off with certainty, that is, when the drive signal of T1 is high, the drive signal of T2 is low with certainty.
For convenience of description, T1, T3, T5 and T7 are exemplified below.
TABLE 1
T1 T3 T5 T7 VO iN iC1 On-off state
1 0 1 1 +E io 0 V0
0 0 1 1 +E/2 io -io V1
1 0 0 1 +E/2 io io V2
0 0 0 1 0 io 0 V3
0 1 1 1 0 io 0 V4
0 1 0 1 -E/2 io io V5
0 1 1 0 -E/2 io -io V6
0 1 0 0 -E io 0 V7
As can be seen from Table 1, the current flowing to the midpoint N is always ioSince the output current is a sine wave and the total current flowing to the midpoint in one cycle is 0, the voltages of C2 and C3 can be maintained in balance in one sine wave cycle.
When the output voltage is + E/2, two states V1 and V2 can be selected, and the current flowing to the capacitor C1 in the two states is opposite in direction, so that the voltage of the capacitor C1 can be balanced by flexibly selecting two switch states V1 and V2; similarly, when the output voltage is-E/2, two switch states of V5 and V6 can be flexibly selected to balance the voltage of the capacitor C1.
Referring to fig. 6, the figure is an equivalent schematic diagram of the single-phase five-level topology shown in fig. 2 provided by the present invention;
wherein,
the topology unit 402 is an equivalent schematic of the single-phase five-level topology 401.
Referring to fig. 7, the figure is an equivalent schematic diagram of a three-phase five-level inverter provided by the present invention.
The three-phase five-level inverter provided by the embodiment comprises: a first single-phase five-level topology (first topology unit) 504, a second single-phase five-level topology (second topology unit) 505, and a third single-phase five-level topology (third topology unit) 506; a second capacitor C2 and a third capacitor C3;
first ends of first switching tubes in the first single-phase five-level topology 504, the second single-phase five-level topology 505 and the third single-phase five-level topology 506 are connected together and are connected with the positive end of the direct-current power supply 501;
the second ends of the eighth switching tubes in the first single-phase five-level topology 504, the second single-phase five-level topology 505 and the third single-phase five-level topology 506 are connected together and are all connected with the negative end of the direct-current power supply 501;
the N in the three-level bridge arm modules in the first single-phase five-level topology 504, the second single-phase five-level topology 505 and the third single-phase five-level topology 506 are all connected with the common end of a second capacitor C2 and a third capacitor C3;
the output terminals O of the first single-phase five-level topology 504, the second single-phase five-level topology 505 and the third single-phase five-level topology 506 are respectively used as three alternating current output terminals of the five-level inverter.
The output end of the first single-phase five-level topology 504 is connected to one end of a first alternating current power supply 510 through a first inductor 507;
the output end of the second single-phase five-level topology 505 is connected to one end of the second ac power supply 511 through the second inductor 508;
the output terminal of the third single-phase five-level topology 506 is connected to one terminal of a third ac power supply 512 through a third inductor 509;
the other end of the first ac power source 510, the other end of the second ac power source 511, and the other end of the third ac power source 512 are connected together.
The amplitudes of the first alternating current power supply 510, the second alternating current power supply 511 and the third alternating current power supply 512 are equal, and the phase angles are sequentially different by 120 degrees.
Before the inverter provided in fig. 7 operates, the first capacitor C1 (in fig. 2) in each single-phase five-level inverter should be charged to a magnitude of one-fourth of the total dc power supply 501 voltage.
It should be noted that, based on the single-phase five-level topology provided in the above embodiments, embodiments of the present invention further provide a multi-phase five-level inverter, which is described in detail below with reference to the accompanying drawings.
Referring to fig. 8, a schematic diagram of a multi-phase five-level inverter according to the present invention is shown.
The multiphase five-level inverter provided by the embodiment comprises a plurality of single-phase five-level topologies;
the first ends of the first switching tubes in each single-phase five-level topology are connected together and are connected with the positive end of the direct-current power supply;
the second ends of the eighth switching tubes in each single-phase five-level topology are connected together and are connected with the negative end of the direct-current voltage;
the N in the three-level bridge arm module in each single-phase five-level topology is connected with the common end of the second capacitor and the common end of the third capacitor;
and the output end of each single-phase five-level topology is respectively used as the alternating current output end of the five-level inverter, and each alternating current output end is mounted with a load.
The symbols of the load in the figure are drawn as resistors, and it is understood that the load may be a motor, a 6-phase motor, or a 12-phase motor. For example, when the load is a 6-phase motor, the five-level inverter is six-phase.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (10)

1. A single-phase five-level topology, comprising: the circuit comprises a first capacitor, a three-level bridge arm module and four switching tubes, wherein the four switching tubes are respectively a first switching tube, a fifth switching tube, a sixth switching tube and an eighth switching tube; each switching tube is reversely connected with a diode in parallel;
the first end of the first switch tube is connected with the anode of a direct-current power supply, and the second end of the first switch tube is connected with the first node;
a second end of the eighth switching tube is connected with a negative electrode of the direct-current power supply, and a first end of the eighth switching tube is connected with the second node; two ends of the first capacitor are respectively connected with a first node and a second node;
a first end of the fifth switching tube is connected with the first node, and a second end of the fifth switching tube is connected with the output end of the inverter;
a first end of the sixth switching tube is connected with the output end of the inverter, and a second end of the sixth switching tube is connected with the second node;
the three-level bridge arm module comprises two switching tubes and a double-switching unit, wherein the two switching tubes are respectively a third switching tube and a fourth switching tube;
the first end of the third switching tube is connected with the first node, and the second end of the third switching tube is connected with a neutral point N through the double switching units; the first end of the fourth switch tube is connected with the N through the double switch units, and the second end of the fourth switch tube is connected with the second node.
2. The single-phase five-level topology according to claim 1, wherein the two-switch unit comprises a second switch tube, a seventh switch tube, a first diode and a second diode; the double-switch unit is provided with three nodes which are connected with the outside, namely a third node, a fourth node and the N;
the anode of the first diode is connected with the N, and the cathode of the first diode is connected with the third node;
a first end of the seventh switching tube is connected with the third node, and a second end of the third switching tube is connected with the third node;
the anode of the second diode is connected with a fourth node, and the cathode of the second diode is connected with the N;
the first end of the second switch tube is connected with the second end of the seventh switch tube, the second end of the second switch tube is connected with the fourth node, and the first end of the fourth switch tube is connected with the fourth node.
3. The single-phase five-level topology according to claim 1, wherein the dual switching unit comprises a second switching tube and a seventh switching tube; the second switching tube and the seventh switching tube are connected with a diode in parallel in a reverse direction;
the first end of the second switching tube is connected with the second end of a third switching tube, and the second end of the third switching tube is connected with the first end of the fourth switching tube;
the first end of the seventh switch tube is connected with the N, and the second end of the seventh switch tube is connected with the second end of the second switch tube.
4. The single-phase five-level topology according to claim 1, wherein the two-switch unit comprises a second switch tube, a first diode, a second diode, a third diode and a fourth diode;
the anode of the first diode is connected with the N, and the cathode of the third diode is connected with the N;
the cathode of the first diode is connected with the cathode of the second diode, the anode of the second diode is connected with the second end of the third switching tube, and the second end of the third switching tube is connected with the first end of the fourth switching tube;
the anode of the third diode is connected with the anode of the fourth diode, and the cathode of the fourth diode is connected with the anode of the second diode;
the first end of the second switch tube is connected with the cathode of the first diode, and the second end of the second switch tube is connected with the anode of the third diode.
5. The single-phase five-level topology according to claim 2 or 3,
the driving signal logics of the first switching tube and the second switching tube are opposite;
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the driving signal logics of the seventh switching tube and the eighth switching tube are opposite.
6. The single-phase five-level topology of claim 4,
the driving signal logics of the third switching tube and the fourth switching tube are opposite;
the driving signal logics of the fifth switching tube and the sixth switching tube are opposite;
the logic phase of the driving signal of the first switching tube and the eighth switching tube is opposite to the logic phase of the driving signal of the second switching tube.
7. The single-phase five-level topology according to claim 2 or 3, wherein the eight operating modes of the single-phase five-level inverter are:
a first mode of operation: the first switch tube, the fourth switch tube, the fifth switch tube and the seventh switch tube are switched on, and the other switch tubes are all switched off;
the second working mode is as follows: the second switching tube, the fourth switching tube, the fifth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
the third working mode is as follows: the first switch tube, the fourth switch tube, the sixth switch tube and the seventh switch tube are all switched on, and the other switch tubes are all switched off;
the fourth working mode: the second switching tube, the fourth switching tube, the sixth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a fifth working mode: the second switching tube, the third switching tube, the fifth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a sixth working mode: the second switching tube, the third switching tube, the sixth switching tube and the seventh switching tube are all switched on, and the other switching tubes are all switched off;
a seventh working mode: the second switching tube, the third switching tube, the fifth switching tube and the eighth switching tube are all switched on, and the other switching tubes are all switched off;
the eighth working mode: the second switch tube, the third switch tube, the sixth switch tube and the eighth switch tube are all switched on, and the rest switch tubes are all switched off.
8. The single-phase five-level topology of claim 1, further comprising a second capacitor and a third capacitor;
two ends of the second capacitor are respectively connected with the positive electrode of the direct current power supply and the N;
and two ends of the third capacitor are respectively connected with the negative electrode of the direct current power supply and the N.
9. A five-level inverter comprising three single-phase five-level topologies according to any one of claims 1 to 7, a first single-phase five-level topology, a second single-phase five-level topology and a third single-phase five-level topology, respectively; the capacitor further comprises a second capacitor and a third capacitor;
the first ends of the first switching tubes in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are connected together and are connected with the positive end of the direct-current power supply;
second ends of eighth switching tubes in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are connected together and are connected with a negative end of direct-current voltage;
the N in the three-level bridge arm modules in the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are all connected with the common end of the second capacitor and the common end of the third capacitor;
and the output ends of the first single-phase five-level topology, the second single-phase five-level topology and the third single-phase five-level topology are respectively used as three alternating current output ends of the five-level inverter.
10. A multiphase five level inverter comprising a plurality of single phase five level topologies as claimed in any one of claims 1-7; the capacitor further comprises a second capacitor and a third capacitor;
the first ends of the first switching tubes in each single-phase five-level topology are connected together and are connected with the positive end of the direct-current power supply;
the second ends of the eighth switching tubes in each single-phase five-level topology are connected together and are connected with the negative end of the direct-current voltage;
the N in the three-level bridge arm module in each single-phase five-level topology is connected with the common end of the second capacitor and the common end of the third capacitor;
and the output end of each single-phase five-level topology is respectively used as the alternating current output end of the five-level inverter, and each alternating current output end is mounted with a load.
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