CN104135292A - Mixed mode time interleaved digital-to-analog converter for radio-frequency applications - Google Patents

Abstract

Disclosed are systems, devices and methods related to mixed mode time interleaved digital-to-analog converters (DACs). In some embodiments, such DACs can be utilized for radio-frequency (RF) applications. In some embodiments, a DAC for RF applications can include a first circuit configured to receive a digital signal and perform a first operation to yield an increased bandwidth of the DAC. The DAC can further include a second circuit configured to perform a second operation on the digital signal to yield an analog signal representative of the digital signal. The second circuit can be further configured to reduce or remove an image within the increased bandwidth.

Description

Mixed mode time interleaving digital to analog converter for radio frequency applications

The cross reference of related application

The name that the application requires to submit on May 2nd, 2013 is called the provisional application No.61/818 of the U.S. of " for the mixed mode time interleaving digital to analog converter of radio frequency applications ", 788 priority, and it discloses clear and definite integral body by reference and is herein incorporated.

Technical field

The disclosure generally relates to a kind of digital to analog converter (DAC) for radio frequency (RF) application.

Background technology

In many digital radio devices and system, generally with number format deal with data, and be converted into the analog format for transmitting.This conversion is carried out by digital to analog converter (DAC) conventionally.

DAC is converted to digital information the analog representation of this information with the step of separating.During this transfer process, may manifest many effects; And at least some in this effect may reduce utilizes the equipment of DAC and the performance of system.

Summary of the invention

In some implementation, the disclosure relates to a kind of digital to analog converter (DAC), and it comprises the first circuit, is configured to receiving digital signals and carries out the first bandwidth that operates to produce the increase of described DAC.Described DAC further comprises second circuit, is configured to that described digital signal is carried out to second and operates to produce the analog signal that represents described digital signal.Described second circuit is further configured to and in the bandwidth of described increase, reduces or removal of images (image).

In certain embodiments, described the first circuit can comprise up-sampling circuit, is configured to digital signal described in coefficient n up-sampling, and wherein quantity n is real number, for example 2.Described the first circuit may further include finite impulse response (FIR) (FIR) filter, is configured to receive the digital signal of described up-sampling, and generates the digital signal of filtered up-sampling.

In certain embodiments, described the first circuit may further include the hybrid circuit of communicating by letter with described second circuit.Described hybrid circuit can be configured to carry out mixed mode operations.In certain embodiments, described second circuit can comprise time interleaving DAC (TIDAC) circuit of communicating by letter with described hybrid circuit.Described TIDAC circuit can comprise a plurality of samplings and maintenance (S/H) circuit.Each S/H circuit can be configured to receive the digital signal of described up-sampling the analog signal after T.G Grammar.Described TIDAC circuit can comprise the clock with described a plurality of S/H circuit communications.Described clock can be configured to provide staggered clock signal to described a plurality of S/H circuit.Described TIDAC circuit may further include delay circuit, and being configured to provides delay at least one in described staggered clock signal.

In certain embodiments, can in analog domain, carry out described mixed mode operations.Described hybrid circuit can comprise and each multiplier circuit of communicating by letter in described S/H circuit.Each multiplier circuit can be configured to receive analog signal and the mix clock signal described conversion from its corresponding S/H circuit.Analog signal and described mix clock signal that each multiplier circuit can be further configured to based on after described conversion generate product signal.Described the first circuit may further include and each summing circuit of communicating by letter in described a plurality of multiplier circuits.Described summing circuit can be configured to receive described product signal from its corresponding multiplier circuit, and is that described DAC generates analog output signal.

In certain embodiments, can in numeric field, carry out described mixed mode operations.Described hybrid circuit can comprise with described a plurality of S/H circuit in each the multiplier circuit of input communication.Described multiplier circuit can be configured to receive digital signal and the mix clock signal of described up-sampling.Digital signal and described mix clock signal that described multiplier circuit can be further configured to based on described up-sampling are described a plurality of S/H circuit evolving product signal.Described the first circuit may further include with described a plurality of S/H circuit in each the switching circuit of output communication.Described switching circuit can be configured to from described a plurality of S/H circuit each receive analog signal and the clock signal after described conversion.Described switching circuit can be further configured to as described DAC circuit evolving analog output signal.The clock signal providing to described switching circuit can be from providing the clock of the TIDAC of described staggered clock signal to provide to described a plurality of S/H circuit.

In certain embodiments, described analog signal can comprise radio frequency (RF) signal.Described image can comprise spurious emissions crest.

In certain embodiments, the bandwidth of described increase can have the effective frequency range wider than sinc response function.The bandwidth of described increase can have than the wider effective frequency range of the response of only being obtained by mixed mode operations.

According to many implementations, the disclosure relates to a kind of for digital signal being converted to the method for radio frequency (RF) signal.Described method comprises and receives described digital signal and carry out the first bandwidth that operates to produce the increase of RF signal.Described method further comprises that described digital signal is carried out to second operates to produce described RF signal.Described the second operation further reduces or removal of images in the bandwidth of described increase.

In certain embodiments, described the first operation can comprise numerical data described in up-sampling.Described the first operation may further include carries out filtering to the numerical data of described up-sampling.

In certain embodiments, described operation may further include married operation.Can in numeric field or analog domain, carry out described married operation.Described the second operation can comprise carries out a plurality of time interleaving digital-to-analogue conversions (TIDAC) operation to the numerical data of described up-sampling.Described the second operation may further include the output that merges described TIDAC operation, or selects in the output of described TIDAC operation.

In many instructions, the disclosure relates to a kind of baseband subsystems, comprises the processor that is configured to generating digital signal and the digital to analog converter (DAC) that is configured to described digital signal to be converted to radio frequency (RF) signal.Described DAC comprises the first circuit, is configured to receive described digital signal and carries out the first bandwidth that operates to produce the increase of described DAC.Described DAC further comprises second circuit, is configured to that described digital signal is carried out to second and operates to produce the RF signal that represents described digital signal.Described the second operation is further configured in the bandwidth of described increase and reduces or removal of images.

According to some implementation, the disclosure relates to a kind of wireless system, comprises the baseband subsystems that is configured to processing digital signal.Described baseband subsystems has digital to analog converter (DAC), comprises and is configured to receive described digital signal and carries out the first the first circuit of bandwidth that operates to produce the increase of described DAC.Described DAC further comprises second circuit, is configured to that described digital signal is carried out to second and operates to produce radio frequency (RF) signal that represents described digital signal.Described second circuit is further configured in the bandwidth of described increase and reduces or removal of images.Described wireless system further comprises the RF subsystem of communicating by letter with described baseband subsystems.Described RF subsystem configures is for receiving described RF signal and generating the RF signal after amplifying.Described wireless system further comprises the antenna with described RF subsystem communication.The transmission of the RF signal of described antenna configuration after for ease of described amplification.

In certain embodiments, can in infrastructure base station, realize described wireless system.Can in the portable radio machine of for example mobile phone, realize described wireless system.

For summarizing object of the present disclosure, this paper describes some aspect of the present invention, advantage and novel features.Be appreciated that any specific embodiment according to the present invention can realize all these advantages.Therefore, can implement or realize the present invention in the mode of the realization as teaching herein or an advantage of optimization or one group of advantage, and needn't be as other advantage that realizes of instruction herein or suggestion.

Accompanying drawing explanation

Fig. 1 describes to have the digital to analog converter (DAC) of one or more features as herein described.

Fig. 2 illustrates in certain embodiments, can in wireless system, realize the DAC of Fig. 1.

Fig. 3 A illustrates conventional DAC configuration.

Fig. 3 B illustrates the example of up-sampling configuration.

Fig. 3 C illustrates the example of time interleaving DAC (TIDAC) configuration.

Fig. 4 A illustrates has sample frequency F _sand pitch frequency (tone frequency) F _tonethe example response of conventional DAC.

Fig. 4 B illustrates the example DAC operational circumstances that may occur relatively large spurious emissions crest.

Fig. 5 A illustrates and the making zero (RZ) and mix the example of (MIX) sampling configuration of normal sampling configuration comparison.

Fig. 5 B illustrates the example of estimating for the power spectral density of the sampling configuration of Fig. 5 A.

Fig. 6 A illustrates example normal mode operational circumstances, wherein (7/8) F _spitch frequency F _tonebe created in the spurious emissions (image) of the relative high-amplitude of about 0.3GHz, wherein F _sfor 2.4GHz.

Fig. 6 B illustrates example hybrid pattern operational circumstances, wherein F _toneand F _sidentical with Fig. 6 A, it produces the pitch frequency F raising _toneamplitude, but wherein spurious emissions (image) amplitude can keep enough height to affect bandwidth of operation.

Fig. 7 A illustrates with the F identical with Fig. 6 A _toneand F _sthe input spectrum of the TIDAC system of operation.

Fig. 7 B illustrates the output spectrum of the TIDAC system of Fig. 7 A, wherein from 0.3GHz, has substantially eliminated image.

Fig. 8 illustrates example DAC configuration, and it can be implemented as provides the output spectrum with improved tone power and the image that reduces or substantially eliminate.

Fig. 9 A illustrates the F with 2.4GHz _sf with 0.3GHz _tonethe example of the output spectrum that the DAC of Fig. 8 of operation produces, wherein substantially not or reduced the first image.

Fig. 9 B illustrates the F with 2.4GHz _sf with 2.1GHz _toneanother example of the output spectrum that the DAC of Fig. 8 of operation produces, wherein substantially not or reduced the first image yet.

Figure 10 illustrates another kind of example DAC configuration, and it can be implemented as provides the desired characteristics that is similar to Fig. 8 and 9.

Figure 11 illustrates the process of carrying out DAC operation as herein described that can be implemented as.

Figure 12 illustrates the process of the example more specifically of the process that can be Figure 11 in the context of the DAC of Fig. 8 system.

Figure 13 illustrates the process of the example more specifically of the process that can be Figure 11 in the context of the DAC of Figure 10 system.

Figure 14 describes the example of radio frequency (RF) system, and it has the one or more DAC that realize in wireless device as herein described.

Figure 15 describes the example of RF system, and it has the one or more DAC that realize in the wireless system of for example base station as herein described.

Embodiment

Title provided in this article, if any, just for convenient, and not necessarily can affect scope of the present invention or the implication of asking for protection.

Herein disclosed is various systems, circuit, equipment and the method for the digital-to-analogue conversion that relates to the signal of applying for radio frequency (RF).Although be described in the context of RF application, be appreciated that one or more feature of the present disclosure can also be for relating to other application of digital-to-analogue conversion.

When the signal of number format is synthesized to RF form, may there is the problem of the limit bandwidth of digital to analog converter (DAC).In some cases, this limit bandwidth can comprise due to Nyquist bandwidth F _sthe limit of the band in response to DAC (band limited) frequency, wherein F of/2 _srepresent sample frequency.This frequency band limits can produce the effect of the dynamic range that reduces RF system.This frequency band limits can also cause with for F _sfrequency domain in the difficult problem that is associated of signal replication, it is approaching F _sduring/2 operation, produce the spurious emissions that approaches the signal being sent out.

Fig. 1 schematic representation has the DAC100 of one or more features as herein described.These features can be conducive to solve some or all problems that DAC above-mentioned and for RF application is associated.As Fig. 1 describes, DAC100 can be configured to receiving digital signals and generate the RF signal that represents described digital signal.To the example of DAC100 be described in further detail herein.

Fig. 2 describes wherein can realize the wireless system of the DAC100 with one or more features of the present disclosure.In certain embodiments, can in baseband subsystems 102, realize DAC100, digital signal is converted to corresponding analog signal.This analog signal can offer transmitter 110, and it is configured to generate the RF signal after (for example,, by power amplifier (PA) 112) amplification for transmitting.In certain embodiments, can in RF subsystem 104, realize transmitter 110 and PA112.

Fig. 2 further illustrates and the RF signal after the amplification from PA112 can be offered to antenna 108 by front end system 106.In certain embodiments, front end system 106 can be configured to be convenient to receive (Rx) (not shown) and transmission (Tx) operation.

In certain embodiments, can in relating to base station, wireless device or any RF system that digital signal is converted to analog signal, realize the wireless system of Fig. 2.In addition,, although be described in the example context as a part for baseband subsystems 102 at DAC100, be appreciated that and can also in the RF of other type framework, realize one or more feature of the present disclosure.

Fig. 3 A illustrates the conventional DAC configuration 120 that wherein digital signal 122 that is depicted as " Data_in " is offered to sampling and keep (S/H) circuit 124.Can configure in a known way and operate S/H circuit 124 to produce simulation output.

As common, understand, common the had response characteristic of above-mentioned conventional DAC configuration is or is similar to sync function, wherein sinc (x)=sin (x)/x.Conventionally also will appreciate that when DAC is with frequency F _ssampling is to generate pitch frequency F _tonetime, can generated frequency F _iMthe spurious emissions at place.F _iMcan be expressed as F _iM=F _s-F _tone, and this spurious emissions is normally undesired.These spurious emissions are in this article also referred to as image.

Fig. 4 A illustrates the sample frequency F with 2.4GHz _soperate and generate the pitch frequency F of 0.1GHz _tonethe example response of the conventional DAC of (crest 160) (for example, the example of Fig. 3 A).As shown in the figure, at the frequency (F of about 2.3GHz (2.4-0.1) _iM) locate to occur spurious emissions (image) crest.In this concrete example, F _toneand F _iMobviously separate, and because the response of sinc function significantly reduces spurious emissions amplitude.Therefore, can relatively easily eliminate relatively little spurious emissions crest 162.

Yet, consider another sample situation as shown in Figure 4 B, wherein F _s=2.4GHz, and F _tone1.5GHz (crest 166).As shown in the figure, at about 0.9GHz (2.4-1.5) F _iMthere is relatively large spurious emissions (image) crest 164 in place.

Based on above-mentioned example, note along with F _toneincrease, tone power reduces, thereby reduces dynamic range.In addition, work as F _tonebecome and approach F _s/ 2 o'clock, unexpected ground F _iMbecome and approach F _tone.Frequency F _s/ 2 are called Nyquist frequency sometimes.Conventionally understand the effect of this frequency and relevant for example aliasing (aliasing).

Above-mentioned effect with reference to figure 4A and 4B description can solve in many ways.For example, signal equalization can maintain or improve the dynamic range of DAC system, to compensate roll-off (roll-off) of DAC response.Can also utilize the technology of the data of for example resampling or up-sampling arrival.In the context of up-sampling, can utilize many operator schemes.The pattern that makes zero and mixed mode are the example of this operator scheme.

Fig. 3 B schematic representation up-sampling configuration 130, wherein up-sampling assembly 134 up-samplings are depicted as the digital signal 132 of " Data_in ".If carry out up-sampling with coefficient n, the efficiently sampling frequency occurring from up-sampling assembly 134 can be nF _s.The data of up-sampling are illustrated as offering sampling and keep (S/H) circuit 136.Can configure in a known way and operate described S/H circuit 136 to generate simulation output.

Fig. 5 A and 5B illustrate above-mentioned the making zero (RZ) of comparing with conventional (normally) DAC operation and mix the example of (MIX) pattern operation (for example, the up-sampling for Fig. 3 B configures).In Fig. 5 A, describe that representative is normal, the sampling period of RZ and MIX pattern.Fig. 5 B illustrates for the power spectral density of model identical and estimates.

In Fig. 5 B, MIX pattern is illustrated as producing the widest bandwidth expansion in three kinds of example arrangement, and with arrow, indicates the crest location of MIX mode response.At the frequency place corresponding to this crest, even if utilized equilibrium, utilize the power of normal response (" O ") of zero hold sampling also in the abrupt slope in sinc response.In the situation that RZ samples, power falls to approximately-8dBFS, and it can seriously reduce noise spectrum and the spectral mask performance of DAC, thereby described response cannot be applied for the low noise spectral density (NSD) being for example associated with infrastructure base station.

MIX pattern has the widest bandwidth expansion in three examples, and its bandwidth also can be limited to spurious emissions (image).With reference to figure 6A and 6B, this effect is shown.Fig. 6 A illustrates normal mode operational circumstances, wherein desirable pitch frequency F _tonefor (7/8) F _s, F _sfor 2.4GHz.Therefore, F _tonebe about 2.1GHz, and the spurious emissions (image) of relative high-amplitude (based on sinc response) is shown in the F of about 0.3GHz _iMplace generates.

In Fig. 6 B, there is same tone and sample frequency (F _s=2.4GHz, F _tone=(7/8) F _s=2.1GHz) MIX pattern operation is illustrated as producing the pitch frequency F raising _toneamplitude (for example, about 13dB raises), and at the F of about 0.3GHz _iMplace reduces the amplitude of image.Yet it is enough high to affect bandwidth of operation that spurious emissions amplitude (image) can keep.

In some applications, can reduce for example frequency spectrum duplicate (replica) of spurious emissions (image) by for example technology of time interleaving DAC (TIDAC) framework.Conventionally, TIDAC configuration can comprise parallel connection (parallel) combination of a plurality of DAC passages, and the output of these passages can be sued for peace to produce total system output.

Fig. 3 C illustrates the example TIDAC configuration 140 with two DAC passages.First passage is shown as including and receives the first sampling of data input (Data_in) 142 and keep (S/H) assembly 148.Similarly, second channel is shown as including the 2nd S/H assembly 150 that also receives data input (Data_in) 142.The one S/H assembly 148 is illustrated as by coming the clock signal of self-clock 144 to operate, and the 2nd S/H assembly 150 is illustrated as delay (for example, half period) the version operation by carrying out the clock signal of self-clock 144.In this example, described delay is illustrated as being introduced by assembly 146.

Fig. 3 C further illustrate can in summing circuit 152, merge described the first and second S/H assemblies 148,150 output to produce simulation output.This TIDAC configuration can be eliminated the image that spurious emissions produces effectively.For example, Fig. 7 A illustrates the F with 2.1GHz _tone(crest 170) (F wherein _s=2.4GHz) input spectrum of the TIDAC system of operation.Fig. 7 B illustrates the F that comprises 2.1GHz place _tonethe output spectrum of crest 172, and substantially eliminated the first image near 0.3GHz or its.When, noting because sinc roll-offs effectively during removal of images from described output spectrum, the power output of tone crest 172 has reduced about 12dB from input power.

In some implementation, DAC system can be configured to comprise with for example, for (raising output sound adjusting power, thereby expand available bandwidth) one or more features of being associated of technology, and with for reducing or substantially eliminating one or more features that the technology of undesired image is associated.For example, the one or more features with being associated with reference to figure 3B, 5, the 6 MIX pattern configurations of describing and the one or more features that are associated with the TIDAC configuration of describing with reference to figure 3C, 7 can be combined.Although be described in the context of this example, will appreciate that and can in other combination, realize one or more feature of the present disclosure.

Fig. 8 illustrates to may be embodied as to provide for example has improved tone power and minimizing or the example DAC configuration 100 of the desired characteristics of the output spectrum of the image of elimination substantially.DAC configuration 100 can comprise up-sampling circuit 204 (for example, with coefficient 2 up-samplings), and its input by path 202 receiving digital signals 200 is to produce the data of up-sampling.Can this data be offered to filter 208 (for example, finite impulse response (FIR) (FIR) filter) to produce up-sampling and filtered data in outgoing route 210 by path 206.

Up-sampling and filtered data are illustrated as offering a S/H circuit 214 by path 210,212.Similarly, up-sampling and filtered data are regarded as also by path 210,216, offering the 2nd S/H circuit 218.Can in TIDAC pattern, operate the first and second S/H circuit 214,218.For example, the clock signal of passing through path 222 and 224 that the one S/H circuit 214 is illustrated as origin self-clock 220 operates, and the 2nd S/H circuit 218 is illustrated as delay (for example, half period) the version operation of the clock signal of passing through path 222,226 and 230 of origin self-clock 220.In this example, described delay is illustrated as being introduced by assembly 228.

In the example arrangement 100 of Fig. 8, can in analog domain, carry out married operation.For example, can be used for the mixed mode clock signal of self-clock 250 is multiplied by each in the simulation output of the first and second S/H circuit 214,218.More specifically, from the simulation of a S/H circuit 214, export and be illustrated as offering the first multiplier circuit 260 by path 240, and come the mixed mode clock signal of self-clock 250 to be illustrated as offering the first multiplier circuit 260 by path 252 and 254.The first multiplier circuit 260 is illustrated as exporting product signal to path 262.Similarly, from the simulation of the 2nd S/H circuit 218, export and be illustrated as offering the second multiplier circuit 264 by path 242, and come the mixed mode clock signal of self-clock 250 to be illustrated as offering the second multiplier circuit 264 by path 252 and 256.The second multiplier circuit 264 is illustrated as exporting product signal to path 266.

As shown in Fig. 8 is further, the output signal of the first and second multiplier circuits 260,264 is illustrated as being merged by summing circuit 270.Summing circuit 270 be illustrated as producing can be as the output of DAC100 output signal to path 272.

The DAC that configures in the above described manner and operate can produce desirable function, comprises and increases bandwidth and at least in the bandwidth of described increase, reduce or basic removal of images.For example, Fig. 9 A and 9B illustrate the F with 2.4GHz _s, be respectively the F of 0.3GHz (crest 280 of Fig. 9 A) and 2.1GHz (crest 282 of Fig. 9 B) _tonethe output spectrum that the DAC100 of Fig. 8 of operation produces.Can find out in each frequency spectrum, substantially not or reduced the first image.More specifically, the F that substantially there is no 2.1GHz (2.4-0.3) in the frequency spectrum of Fig. 9 A _iMfirst image at place; In the frequency spectrum of Fig. 9 B, substantially there is no the F of 0.3GHz (2.4-2.1) _iMfirst image at place.In addition, the power output of the 0.3GHz tone of roughly the same (for example, being greater than approximately-50dB) (crest 280) and 2.1GHz (crest 282) tone illustrates improved bandwidth.

Figure 10 illustrates another example DAC configuration 100, and it can be implemented as provides and desired characteristics like feature class with reference to described in figure 8 and 9.In the example of Figure 10, can carry out married operation at numeric field.

DAC configuration 100 can comprise up-sampling circuit 204 (for example, with coefficient 2 up-samplings), and its input by path 202 receiving digital signals 200 is to produce the data of up-sampling.Can this data be offered to filter 208 (for example, finite impulse response (FIR) (FIR) filter) to produce up-sampling and the filtered data in outgoing route 210 by path 206.

In the example arrangement 100 of Figure 10, can in numeric field, carry out married operation.For example, can be used for the mixed mode clock signal of self-clock 290 is multiplied by numerical data (path 210).More specifically, the clock signal in the up-sampling in path 210 and filtered data and path 292 is illustrated as offering multiplier circuit 294.Multiplier circuit 294 is illustrated as exporting product signal to path 296.

Hybrid digital data from multiplier circuit 294 are illustrated as offering a S/H circuit 214 by path 296 and 298.Similarly, hybrid digital data are illustrated as offering the 2nd S/H circuit 218 by path 296 and 300.Can in TIDAC pattern, operate the first and second S/H circuit 214,218.For example, the clock signal of passing through path 222,224,302 that the one S/H circuit 214 is illustrated as origin self-clock 220 operates, and the 2nd S/H circuit 218 is illustrated as delay (for example, half period) the version operation of the clock signal of passing through path 222,226,230 of origin self-clock 220.In this example, described delay is illustrated as being introduced by assembly 228.

In the example depicted in fig. 10, the simulation of the first and second S/H circuit 214,218 output is illustrated as by path 310 and 312, offering switching circuit 314 respectively.Described switching circuit 314 is illustrated as also by path 222,224 and 304 receptions, coming the staggered clock signal of self-clock 220.Can also operate described switching circuit 314 to switch the output in (in path 316) between two channels interleaveds that are associated with the first and second S/H circuit 214,218.

In certain embodiments, switching circuit 314 can be implemented as the very switch of high frequency.In certain embodiments, can realize this switch to produce high linear properties.

Figure 11 illustrates process 330, and it can be implemented as carries out the DAC operation with one or more features as herein described.In frame 332, can receiving digital data.In frame 334, can carry out DAC operative combination to increase bandwidth of operation and reduce or eliminate the image in this bandwidth to described numerical data.

In the context of the example DAC of Fig. 8 and 10 system, Figure 12 and 13 illustrates respectively process 340 and 360, and it can be implemented as the example more specifically of the process 330 of Figure 11.In the frame 342 of the instantiation procedure 340 of Figure 12, can receiving digital data.In frame 344, can up-sampling described in numerical data.In frame 346, can carry out filtering to the data of described up-sampling.In frame 348, can carry out a plurality of time interleaving samplings and keep operation.In frame 350, can carry out married operation for each simulation output of described time interleaving S/H operation.In frame 352, can merge described hybrid analog-digital simulation and export to produce simulation output.

In the frame 362 of the instantiation procedure 360 of Figure 13, can receiving digital data.In frame 364, can up-sampling described in numerical data.In frame 366, can carry out filtering to the data of described up-sampling.In frame 368, can carry out married operation to described up-sampling and filtered numerical data.In frame 370, can carry out a plurality of time interleaving samplings and keep operation described hybrid digital data.In frame 372, can carry out switching manipulation to select the output of S/H operation to produce simulation output.

As described herein, can in wireless system and/or equipment, realize one or more feature as herein described.For example, infrastructure base station can comprise the wireless system with one or more features as herein described.

In some implementation, the DAC system with one or more features as herein described can be included in the RF equipment of wireless device for example.Can be with one or more modular form, or with its certain combination, in described wireless device, directly realize this equipment and/or circuit.In certain embodiments, this wireless device can comprise handheld wireless device, wireless flat computer of such as cell phone, smart phone, tool, being with or without telephony feature etc.

Figure 14 describes to have the exemplary wireless device 400 of one or more favorable characteristics as herein described.In the context of DAC100 with one or more features as herein described, sort circuit or equipment can be parts for baseband subsystems 410 for example.

In exemplary wireless device 400, transceiver 414 is illustrated as with baseband subsystems 410 mutual, and inter alia, it is configured to provide the conversion between the RF signal that is suitable for user's data and/or voice signal and is suitable for transceiver 414.In order to transmit, transceiver 414 can provide the RF signal not amplifying to produce the RF signal after amplifying to power amplifier 416.RF signal after described amplification can be offered to antenna 424 by for example switch 422 (via duplexer 420).Transceiver 414 can also be configured to process the signal receiving.The signal of these receptions can be sent to one or more LNA (not shown) from antenna 424 by duplexer 420.Transceiver 414 is also illustrated as being connected to power management component 406, and it is configured to management for the power of the operation of wireless device 400.

Baseband subsystems 410 is illustrated as being connected to user interface 402 so that offer user and receive various inputs and the output of voice and/or data from it.Baseband subsystems 410 can also be connected to memory 404, and it is configured to store data and/or instruction so that the operation of wireless device and/or provide information storage for user.

Many other wireless device configuration can be utilized one or more feature as herein described.For example, wireless device needs not be multiband equipment.In another example, wireless device can comprise the extra antenna of diversity antenna for example and the extra connection features of Wi-Fi, bluetooth and GPS for example.

In some implementation, the DAC system with one or more features as herein described can be included in the wireless system of the wireless system being for example associated with infrastructure base station.Figure 15 schematic representation has the example wireless system 500 of one or more favorable characteristics as herein described.In upper and lower zhang of DAC100 with one or more features as herein described, sort circuit or equipment can be parts for Digital Subsystem 502 for example.Digital Subsystem 502 can be configured to provide the one or more functions that are associated with baseband subsystems.Digital Subsystem 502 can also comprise processor 504, and it is configured to control and/or be convenient to the various functions of Digital Subsystem 502.

In example wireless system 500, the transceiver 512 of RF subsystem 510 is illustrated as with Digital Subsystem 502 mutual.Inter alia, Digital Subsystem 502 can be configured to provide the conversion between the RF signal that is suitable for user's data and/or voice signal and is suitable for transceiver 512.In order to transmit, transceiver 512 provides the RF signal not amplifying can to power amplifier 514, to produce the RF signal after amplification.Can the signal of the RF after described amplification be provided to antenna 522 by for example front end (FE) system 520.Transceiver 512 can also be configured to process the signal receiving.Can the signal receiving from antenna 520 be sent to low noise amplifier (LNA) 516 by front end system 520.Many other assemblies can be included in wireless system 500 so that its operation.

Digital signal is being converted in the context of analog rf signal, is this paper describes various examples.As common, understand, RF subsystem can be first by this for the analog of transmitting, be intermediate frequency (IF) signal, be then treated to RF signal.Therefore, will appreciate that RF signal that DAC as herein described generates can comprise having the frequency that is associated with any part of wireless device and/or system or the analog signal of frequency range (comprising frequency or frequency range with aforementioned IF and RF signal correction connection).

The disclosure has been described various features, wherein there is no a kind of benefit as herein described of being responsible for completely.Will appreciate that and can combine, revise or omit various feature as herein described, this it will be apparent to those skilled in the art that.Those combinations except specifically describing herein and combination and the sub-portfolio outside sub-portfolio it will be apparent to those skilled in the art that, and it is intended to form this disclosed part.In conjunction with each flow chart step and/or stage, the whole bag of tricks has been described herein.Will appreciate that in many cases, can merge some step and/or stage, thereby a plurality of steps shown in flow chart and/or stage can be implemented as to a step and/or stage.In addition, some step and/or stage can be split as to the extra sub-component of separately carrying out.In some instances, can rearrange the order in described step and/or stage, and can omit completely some step and/or stage.In addition, method as herein described is understood to open, makes to carry out the additional step and/or the stage that illustrate and describe herein.

Can use for example arbitrary combination of computer software, hardware, firmware or computer software, hardware and firmware advantageously to realize some aspect of system and method as herein described.Computer software can comprise the computer-executable code of for example, in computer-readable medium (, nonvolatile computer-readable medium) storage, carries out function as herein described when it is carried out.In certain embodiments, by one or more general-purpose computer processor object computer executable codes.Open according to this, it will be understood by those skilled in the art that the arbitrary feature or function that can realize with the software of carrying out on all-purpose computer can also realize with the various combination of hardware, software or firmware.For example, can use integrated circuit combination with hardware, to realize this module completely.Alternatively or in addition, can realize wholly or in part this feature or function with the special-purpose computer rather than the all-purpose computer that are designed to carry out specific function as herein described.

A plurality of distributive computing facilities can replace arbitrary computing equipment as herein described.In this distributed embodiment, the function of a computing equipment is distributed (for example, on network), thereby carries out some function in each in distributive computing facility.

Can reference equation, algorithm and/or flow process illustrate to describe some embodiment.Can realize these methods with the computer program instructions that can carry out on one or more computers.These methods can also be embodied as independent computer program, or the assembly of device or system.In this regard, can and/or comprise that by hardware, firmware the software of one or more computer program instructions of implementing in computer readable program code logic realizes each equation, algorithm, flow chart box or step and combination thereof.As will be appreciated, any these computer program instructions can be written into one or more computers, include but not limited to that all-purpose computer or special-purpose computer or other processing unit able to programme are to produce machine, the computer program instructions that makes to carry out on one or more computers or one or more other treatment facility able to programme is realized the function of appointment in described equation, algorithm and/or flow chart.Also will appreciate that frame and combination thereof in each equation, algorithm and/or flow process diagram can be realized by the hardware based computer system of special use, it carries out function or step or the combination of the appointment of specialized hardware and computer readable program code logic device.

In addition, the computer program instructions of for example realizing (for example can also be stored in to computer-readable memory in computer readable program code logic, nonvolatile computer-readable medium) in, it can guide one or more computers or other treatment facility able to programme to move with ad hoc fashion, and the instruction that makes to store in computer-readable memory realizes one or more functions of appointment in one or more frames of one or more flow charts.Computer program instructions can also be written into one or more computers or other programmable computation device so that the sequence of operations step of carrying out in described one or more computer or other programmable computation device produces computer implemented process, the instruction that makes to carry out on described computer or other processing unit able to programme is provided for realizing the step of appointed function in one or more frames of one or more equations, one or more algorithm and/or one or more flow charts.

Can be carried out and full automation some or all method as herein described and task by computer system.In some cases, described computer system for example can be included in network communication and interoperability, to carry out a plurality of different computers or the computing equipment (, physical server, work station, storage array etc.) of described function.Each this computing equipment generally includes processor (or a plurality of processor), program command or the module of in its execute store or other nonvolatile computer-readable recording medium or equipment, storing.Can implement described various functions disclosed herein with these program command, for example, although can alternatively realize some or all disclosed function in the application specific circuitry (, ASIC or FPGA) of computer system.In the situation that described computer system comprises a plurality of computing equipment, these equipment can but need not to be common cooperation.Can, by for example physical storage device of solid-state storage chip and/or disk is transformed to different conditions, for good and all store the result of described disclosed method and task.

Unless context is in addition requirement clearly, runs through whole specification and claim, word " comprise " and " comprise,, wait and should explain with the implication of inclusive, and the implication of nonexcludability or exhaustive; That is to say, with the implication of " including but not limited to ", explain.As normally used herein, word " couples " and refers to two or more elements that can directly connect or connect by one or more intermediary element.In addition, when using in this application, the word of word " herein ", " above ", " below " and the similar meaning should refer to the application's integral body, and not this Applicant's Abstract graph any specific part.When context allows, in embodiment above, use the word of odd number or plural number also can comprise respectively plural number or odd number.Word "or" when the list of mentioning two or more, this word covers the whole following explanation to this word: any item in list, the whole items in list and any combination of the item in list.Use exclusively word " exemplary " to refer to " serving as example, use-case or example " herein.Arbitrary implementation that will not be described as " exemplary " is herein interpreted as being better than or well other implementation.

The disclosure is not intended to be limited to implementation shown in this article.Implementation described in open to this is carried out various modifications, is very apparent for a person skilled in the art, and General Principle defined herein can be applied to other implementation, and can not depart from these disclosed spirit or scope.Instruction of the present invention provided herein can be applied to other method and system, and is not limited to above-mentioned method and system, and can combine the element of above-mentioned various embodiment and behavior so that more embodiment to be provided.Therefore, can realize novelty method and system as herein described with various other forms; In addition, can carry out various omissions, replacement and change to the form of methods described herein and system, and can not depart from spirit of the present disclosure.Appended claim and equivalent thereof are intended to contain these can fall into form or the variation in spirit and scope of the present disclosure.

Claims (20)

1. a digital to analog converter (DAC), comprising:

The first circuit, is configured to receiving digital signals and carries out the first bandwidth that operates to produce the increase of described DAC; And

Second circuit, is configured to that described digital signal is carried out to second and operates to produce the analog signal that represents described digital signal, and described second circuit is further configured in the bandwidth of described increase and reduces or removal of images.

2. described DAC as claimed in claim 1, wherein said the first circuit comprises up-sampling circuit, is configured to digital signal described in coefficient n up-sampling, quantity n is real number.

3. described DAC as claimed in claim 2, wherein said the first circuit further comprises the hybrid circuit of communicating by letter with described second circuit, described hybrid circuit is configured to carry out mixed mode operations.

4. described DAC as claimed in claim 3, wherein said second circuit comprises time interleaving DAC (TIDAC) circuit of communicating by letter with described hybrid circuit, described TIDAC circuit comprises a plurality of samplings and maintenance (S/H) circuit, and each S/H Circnit Layout is for receiving the digital signal of described up-sampling the analog signal after T.G Grammar.

5. described DAC as claimed in claim 4, wherein said TIDAC circuit comprises the clock with described a plurality of S/H circuit communications, described clock is configured to provide staggered clock signal to described a plurality of S/H circuit.

6. described DAC as claimed in claim 5, wherein said TIDAC circuit further comprises delay circuit, being configured to provides delay at least one in described staggered clock signal.

7. described DAC as claimed in claim 4 wherein carries out described mixed mode operations in analog domain.

8. described DAC as claimed in claim 7, wherein said hybrid circuit comprises and each multiplier circuit of communicating by letter in described a plurality of S/H circuit, each multiplier circuit is configured to receive analog signal and the mix clock signal described conversion from its corresponding S/H circuit, and analog signal and described mix clock signal that each multiplier circuit is further configured to based on after described conversion generate product signal.

9. described DAC as claimed in claim 8, wherein said the first circuit further comprises and each summing circuit of communicating by letter in described a plurality of multiplier circuits, and described summing circuit is configured to receive described product signal and generate analog output signal for described DAC from its corresponding multiplier circuit.

10. described DAC as claimed in claim 4 wherein carries out described mixed mode operations in numeric field.

11. as described in claim 10 DAC, wherein said hybrid circuit comprise with described a plurality of S/H circuit in each the multiplier circuit of input communication, described multiplier circuit is configured to receive digital signal and the mix clock signal of described up-sampling, and digital signal and described mix clock signal that described multiplier circuit is further configured to based on described up-sampling are described a plurality of S/H circuit evolving product signal.

12. as described in claim 11 DAC, wherein said the first circuit further comprise with described a plurality of S/H circuit in each the switching circuit of output communication, described switching circuit be configured to from described a plurality of S/H circuit each receive analog signal and the clock signal after described conversion, described switching circuit is further configured to described DAC circuit evolving analog output signal.

13. as described in claim 12 DAC, the described clock signal that wherein offers described switching circuit is from providing the clock of the described TIDAC of described staggered clock signal to provide to described a plurality of S/H circuit.

14. 1 kinds for being converted to digital signal the method for radio frequency (RF) signal, and described method comprises:

Receive described digital signal;

Carry out the first bandwidth that operates to produce the increase of described RF signal; And

Described digital signal is carried out to second and operate to produce described RF signal, described the second operation further reduces or removal of images in the bandwidth of described increase.

15. as described in claim 14 method, wherein said the first operation comprises numerical data described in up-sampling.

16. as described in claim 15 method, wherein said the first operation further comprises married operation.

17. as described in claim 16 method, wherein in numeric field or analog domain, carry out described married operation.

18. as described in claim 16 method, wherein said the second operation comprises carries out a plurality of time interleaving digital-to-analogue conversions (TIDAC) operations to the numerical data of described up-sampling.

19. as described in claim 19 method, wherein said the second operation further comprises the output that merges described TIDAC operation, or selects in the output of described TIDAC operation.

20. 1 kinds of baseband subsystems, comprising:

Processor, is configured to generating digital signal; And

Digital to analog converter (DAC), be configured to described digital signal to be converted to radio frequency (RF) signal, described DAC comprises the first circuit, be configured to receive described digital signal and carry out the first bandwidth that operates to produce the increase of described DAC, described DAC further comprises second circuit, be configured to that described digital signal is carried out to second and operate to produce the RF signal that represents described digital signal, described second circuit is further configured in the bandwidth of described increase and reduces or removal of images.