CN104135272B - Save the preemphasis LVDS drive circuits of power consumption - Google Patents
Save the preemphasis LVDS drive circuits of power consumption Download PDFInfo
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- CN104135272B CN104135272B CN201410377242.2A CN201410377242A CN104135272B CN 104135272 B CN104135272 B CN 104135272B CN 201410377242 A CN201410377242 A CN 201410377242A CN 104135272 B CN104135272 B CN 104135272B
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Abstract
The invention discloses a kind of preemphasis LVDS drive circuits for saving power consumption, including main tapping and preemphasis tap, main tapping to be converted to LVDS differential signals OUTP, OUTN by CMOS differential signals INP, INN；Preemphasis tap is then added on corresponding described LVDS differential signals OUTP, OUTN and exports according to INP, INN and the corresponding current signal of CMOS differential signals INP_1, INN_1 generation obtained behind a unit interval that is delayed by INP, INN.The present invention, by two couples of difference control signals INP, INN and INP_1, INN_1 control preemphasis taps, preemphasis tap is set to detect the high speed hopping edge of INP, INN, and it is in running order make it that preemphasis tap has electric current to pass through in a unit interval only after saltus step, and at other times without electric current by off position, same preemphasis effect is realized, but significantly reduces the power consumption of drive circuit, there is very high practical value.
Description
Technical field
Present invention design communication system signal treatment technology, and in particular to that saves power consumption has the function of the LVDS of preemphasis
Drive circuit.
Background technology
The transfer function of transmission medium has a low-pass characteristic, the transmission through long-distance, and the high fdrequency component of signal will be by
Greatly consume, and if circuit cannot support such high-frequency signal saltus step well again, along with output interface
There is larger load, it is easy to which the high level and low level current potential for having led to signal cannot reach well, so as to cause
The processing time of data cannot effectively control.With the raising of drive bandwidth, driven when the bit wide of each data is less than
During the position processing time of dynamic device, the value of previously sent signal will influence the waveform of present bit, and this interference is referred to as intersymbol and does
Disturb (ISI, inter-symbol interference).Intersymbol interference reduces the peak frequency that system can be run, and can be real
The preemphasis circuit of existing high frequency section amplification can accelerate the processing time of data, reduce intersymbol interference.
Have the drive circuit (driver) of preemphasis function basic structure and preemphasis principle it is as shown in Figure 1.In figure
Give two kinds of signal modulation modes：Non-return to zero code (NRZ, not return to zero) and level Four pulse amplitude modulation
(PAM4, four-level pulse amplitude modulation).In a communications system, transmitting procedure high frequency components
Decay can cause the loss of signal integrity, in order to obtain the consistent signal of amplitude in the range of bandwidth of interest in receiving terminal,
Preemphasis processing, the high fdrequency component of advance promotion signal, with compensation would generally be done to signal before signal transmission in transmitting terminal
Decay of the signal in transmitting procedure high frequency components.
The drive circuit for having preemphasis function includes main tapping (main tap) 10, preemphasis tap (pre-emphasis
Tap) 20 and time delay module 30.Fig. 2 gives a typical preemphasis circuit structure.
Main tapping 10 uses LVDS circuit structures, its effect is that CMOS differential signals INP, INN are converted to LVDS is poor
Sub-signal OUTP, OUTN：When INP is high level, INN is low level, PMOS tube M3 and NMOS tube M4 conductings, PMOS tube M2 and
NMOS tube M5 is turned off, and output LVDS differential voltages OUTP-OUTN is negative；When INP is low level, INN is high level, PMOS tube
M3 and NMOS tube M4 shut-offs, PMOS tube M2 and NMOS tube M5 conductings, output LVDS differential voltages OUTP-OUTN is just.
The circuit of preemphasis tap uses the circuit structure identical with main tapping, only difference is that current source current value
Size and the size of each switching tube have difference.The input of preemphasis tap is CMOS differential signals INP_1 and INN_1.
INP_1 and INN_1 is to be obtained by INP and INN by time delay module one unit interval (UI, unit interval) of delay
Arrive.Preemphasis tap injects not Tongfang according to CMOS differential input signal INP_1 and INN_1 to the output node of drive circuit
To electric current.Since the output of preemphasis tap with the output of main tapping is reversely to be connected, thus when INP_1 is high level,
When INN_1 is low level, preemphasis tap injects the electric current in OUTP to OUTN directions to drive circuit output node, and works as INP_
When 1 is low level, INN_1 is high level, electricity of the preemphasis tap to drive circuit output node injection OUTN to OUTP directions
Stream.
The waveform of preemphasis tap, main tapping and drive circuit output current is as shown in Figure 3.In drive circuit output level
After conversion in a back to back unit interval, output level has an overshoot, and which adds output signal
High fdrequency component, so as to play the effect of preemphasis.
However, traditional pre-add weight structure has the defects of wasting power consumption：A list after output signal carries out level conversion
In the time interval of position, the output current of preemphasis tap just and main tapping current direction same direction so that output is believed
Number produce one overshoot；At other times in interval, the output current of preemphasis tap and the current direction of main tapping are opposite
Direction, drive circuit output current subtract the output current of preemphasis tap for the output current of main tapping, there are current canceling,
Preemphasis tap has electric current to flow through and in running order all the time, causes the waste of power consumption.
The content of the invention
Problem to be solved by this invention is that preemphasis tap has electric current by running order so as to cause work(always
The problem of consumption wastes.
In order to solve the above-mentioned technical problem, the technical solution adopted in the present invention is to provide a kind of preemphasis for saving power consumption
LVDS drive circuits, including main tapping 10, preemphasis tap 20 and time delay module 30, the main tapping is by CMOS differential signals
INP, INN are converted to LVDS differential signals OUTP, OUTN；The preemphasis tap then postpones according to INP, INN and by INP, INN
CMOS differential signals INP_1, the INN_1 obtained behind one unit interval produces corresponding current signal and is added to accordingly
Exported on described LVDS differential signals OUTP, OUTN, so as to produce voltage overshoot, realize preemphasis.
In such scheme, the preemphasis tap 20 includes first, second PMOS switchable current sources 21,22, first,
2nd NMOS switchable current sources 23,24, the first, second PMOS switchable current sources 21,22 and first, second NMOS can
Switched current source 23,24 by input signal INP, INN control be switched on and off, first, second group of cmos switch 25,26 by
Input signal INP_1, INN_1 controls, and the electric current of the switchable current source is added to institute according to the on off state accordingly
State on output signal OUTP, OUTN.
In such scheme, the first PMOS switchable current sources 21 include capacitance C1, PMOS tube M7 and M16, NMOS
The source electrode of pipe M15, NMOS tube M15 and PMOS tube M16 connect bias voltage BIAS_UP, the drain electrode of NMOS tube M15 and PMOS tube M16
The grid of PMOS tube M7 is connect, the source electrode of PMOS tube M7 meets power vd D, the grid of a termination PMOS tube M7 of capacitance C1, capacitance C1
Another termination PMOS tube M16 grid；The 2nd PMOS switchable current sources 22 include capacitance C2, PMOS tube M8 and M18,
The source electrode of NMOS tube M17, NMOS tube M17 and PMOS tube M18 connect bias voltage BIAS_UP's, NMOS tube M17 and PMOS tube M18
Drain electrode connects the grid of PMOS tube M8, and the source electrode of PMOS tube M8 connects power vd D, the grid of a termination PMOS tube M8 of capacitance C2, electricity
Hold the grid of another termination PMOS tube M18 of C2；The first NMOS switchable current sources 23 include capacitance C3, NMOS tube M13
With M19, PMOS tube M20, the source electrode of NMOS tube M19 and PMOS tube M20 meet bias voltage BIAS_DOWN, NMOS tube M19 and PMOS
The drain electrode of pipe M20 connects the grid of NMOS tube M13, the source electrode ground connection of NMOS tube M13, the grid of a termination NMOS tube M13 of capacitance C3
Pole, the grid of another termination NMOS tube M19 of capacitance C3；The 2nd NMOS switchable current sources 24 include capacitance C4, NMOS
The source electrode of pipe M14 and M21, PMOS tube M22, NMOS tube M21 and PMOS tube M22 meet bias voltage BIAS_DOWN, NMOS tube M21
Drain electrode with PMOS tube M22 connects the grid of NMOS tube M14, the source electrode ground connection of NMOS tube M14, a termination NMOS tube of capacitance C3
The grid of M14, the grid of another termination NMOS tube M21 of capacitance C3；The grid of PMOS tube M9 and NMOS tube M11 connect input signal
INP_1, the source electrode of PMOS tube M9 connect the drain electrode of PMOS tube M7, and the source electrode of NMOS tube M11 connects the drain electrode of NMOS tube M13, PMOS tube
The source electrode of M9 and NMOS tube M11 meet output signal OUTN；The grid of PMOS tube M10 and NMOS tube M12 meet input signal INN_1,
The source electrode of PMOS tube M10 connects the drain electrode of PMOS tube M8, and the source electrode of NMOS tube M12 connects the drain electrode of NMOS tube M14, PMOS tube M10 and
The source electrode of NMOS tube M12 meets output signal OUTP.
In such scheme, the main tapping 10 includes three PMOS tube M1, M2, M3 and three NMOS tubes M4, M5, M6；
The grid of PMOS tube M1 meets bias voltage BIAS_UP, and source electrode meets power vd D；The grid of PMOS tube M2, M3 meets input CMOS respectively
Differential signal INP, INN, the source electrode of PMOS tube M2, M3 are interconnected and are connected with the drain electrode of PMOS tube M1；The grid of NMOS tube M6 connects
Bias voltage BIAS_DOWN, source electrode ground connection；The grid of NMOS tube M4, M5 meets input CMOS differential signal INP, INN respectively,
The source electrode of NMOS tube M4, M5 is interconnected and is connected with the drain electrode of NMOS tube M6.
The present invention, controls preemphasis tap by two couples of difference control signals INP, INN and INP_1, INN_1, makes preemphasis
Tap can detect the high speed hopping edge of INP, INN, and cause a unit interval of the preemphasis tap only after saltus step
Inside have electric current by and it is in running order, and at other times without electric current by off position, so as to reduce drive
The power consumption of dynamic circuit.
Brief description of the drawings
Fig. 1 is preemphasis structure diagram and principle schematic；
Fig. 2 is a traditional preemphasis construction embodiment circuit diagram；
Fig. 3 is the output current wave schematic diagram of each module of traditional preemphasis；
Fig. 4 is a specific embodiment circuit diagram of the invention；
Fig. 5 is the output current wave schematic diagram of each module of the present invention；
Fig. 6 is the curve map that the power consumption that the present invention saves changes with pre-emphasis magnitude；
Fig. 7 is the specific embodiment circuit diagram that the present invention is used for PAM4 drive circuits.
Embodiment
The present invention provides a kind of preemphasis LVDS drive circuits for saving power consumption, and the same of preemphasis is carried out to input signal
When, it is possible to achieve signal from CMOS level to the conversion of LVDS level, while preemphasis tap only output difference signal OUTP,
Have in the unit interval closely followed after OUTN level conversions electric current by and it is in running order, it is pre- so as to reduce
The power consumption of exacerbation.The present invention is described in detail below in conjunction with the accompanying drawings.
As shown in Figure 1, the preemphasis LVDS drive circuits of the saving power consumption in the present invention include main tapping 10, preemphasis is taken out
First 20 and time delay module 30.We mainly introduce the situation of non-return to zero code modulation.
Main tapping 10 completes signal from CMOS level to the conversion of LVDS level；Preemphasis tap 20 is poor according to input CMOS
Sub-signal INP, INN and CMOS differential signals INP_1, the INN_1 for postponing to obtain behind a unit interval by INP, INN
Control superposition overshoot signal on output LVDS differential signals OUTP, OUTN；Time delay module will input CMOS differential signals INP,
One unit interval of INN delays.Preemphasis is realized by above three module, reducing preemphasis tap has electric current to lead to
The in running order time is spent, and completes signal from CMOS level to the conversion of LVDS level.
Fig. 4 is main tapping 10 of the present invention and a specific embodiment circuit diagram of preemphasis tap 20.Preemphasis tap 20
Employ a kind of improved LVDS driving circuit structures.Current source in each tradition LVDS driving unit is switchable by two
Current source replaces.Preemphasis tap includes first, second PMOS switchable current sources 21,22 and first, second NMOS is switchable
Current source 23,24.When INP is high level (INN is low level), INP_1 is low level (INN_1 is high level), preemphasis
The electric current that tap is OUTN to OUTP to the output node injection direction of drive circuit；When INP is that (INN is high electricity to low level
It is flat), INP_1 is when being high level (INN_1 is low level), preemphasis tap 20 is to the output node injection direction of drive circuit
The electric current of OUTP to OUTN.Since input CMOS differential signals INP_1, INN_1 are input CMOS differential signals INP, INN delays
What one unit interval obtained, so only being changed in drive circuit output-voltage levels in the latter unit interval
20 ability of preemphasis tap is to the output node Injection Current of drive circuit, and electric current is without flow through pre-add in other unit intervals
Weight tap 20, preemphasis tap 20 are off state.Fig. 5 is the current output waveform schematic diagram of each module of the present invention, can be with
Find out in the unit interval only closely followed after drive circuit output signal progress level conversion, it is pre- in the present invention
Aggravating tap 20 just can be to the output node injecting voltage of drive circuit, and interior electric current is without flow through preemphasis tap at other times
20. but the waveform of the output current of obtained drive circuit is as traditional preemphasis.
Illustrate the principle of PMOS switchable current sources by taking the first PMOS switchable current sources 21 as an example below.Switchable current
Source is controlled by a pullup/pulldown network.When INP is changed into high level from low level, by PMOS tube M15 and NMOS tube M16 groups
Into transmission gate conducting, the grid voltage of PMOS tube M7 is changed into bias voltage BIAS_UP, and the first PMOS switchable current sources are beaten
Open.When INN is changed into high level from low level, the resistance of transmission gate becomes very high, and the Injection Current of C1 is mainly by PMOS tube
The parasitic capacitance C of M7 gridsPAbsorb, PMOS tube M7 is turned off.The changes delta V of the grid voltage of PMOS tube M7gateFormula can be used
(1) represent,
The C in formula (1)PIt is the parasitic gate capacitance of PMOS tube M7, VDDIt is supply voltage, Δ Vgate=VOFF-VON.In reality
In the circuit design on border, C1 selects a capacitance for being slightly less than calculated value, can so accelerate the speed of circuit, and reduce
The dynamic power consumption of circuit.
The principle of NMOS switchable current sources can do similar analysis.
Pullup/pulldown network is not limited to the implementation in given embodiment, using other pullup/pulldown real-time performances
With given example similar in circuit, fall within the protection domain of this patent.
If the fixed amplitude of drive circuit output current is F, in order in the transformed unit of output signal level
Between realize the current over pulse of a F+a in interval, it is F+0.5a that traditional preemphasis, which requires the output current amplitude of main tapping, pre-add
The output current amplitude of weight tap is 0.5a.For drive circuit in the present invention, the output current amplitude of main tapping 10 is F, in advance
The output current amplitude for aggravating tap 20 is a.When the transition density (transmission density) of transmission data is 0.5
When, drive circuit of the invention saves the percentage P of power consumptionsaveIt can be represented with formula (2),
In formula (2), P (i) is the probability that drive circuit output signal level is changed in a unit interval.Figure
The curve map that 6 power consumptions saved for the present invention change with pre-emphasis magnitude.As seen from Figure 6, the amplitude of preemphasis is bigger, the present invention
In the preemphasis LVDS drive circuits of saving power consumption save more power consumption.
The present invention can be used for the preemphasis of multistage pulses amplitude modulation transmitter, such as level Four pulse amplitude modulation transmitter
Preemphasis.Level Four pulse amplitude modulation transmits a symbol with four level, and a symbol includes the data of two bits.
The bandwidth of signal can be reduced using level Four pulse amplitude modulation.The preemphasis of PAM4 drive circuits is i.e. in transmitting terminal to four electricity
It is flat to carry out corresponding preemphasis, intersymbol interference is reduced, improves signal quality.
Fig. 7 is the specific embodiment circuit diagram that the present invention is used for PAM4 drive circuits.
The input signal of PAM4 drive circuit main tappings is AP, AN, BP, BN, CP and CN.The input signal of this 6 bits
Got by 2 bit parallel input codings, so the input signal of this 6 bits contains the information of 2 bit parallel inputs, i.e.,
The each output symbol of PAM4 drive circuits contains the information of two bits.
Main tapping 10 is made of two LVDS driving units, and the current amplitude of M7, M12 are 2 times of M1, M6 current amplitude.
Traditional current mode PAM4 drive circuits obtain ± RI level by electric current superposition, that is, the driving unit for exporting two times of electric currents begins
It is in running order eventually.Such embodiment causes unnecessary power wastage.In the embodiment of this patent, as ± RI
When level transmits, BN and CN can be high level at the same time, shut-off PMOS tube M8 and M9, and such PMOS current sources M7 is at turning off shape
State.Similar, BP and CP can be low level at the same time, and shut-off NMOS tube M10 and M11, NMOS current source M12 is off state.
It is only in running order with the driving unit of one times of electric current i.e. when transmission ± RI level.This embodiment is by main tapping
Lower power consumption 1/3.Other circuit structures for realizing PAM4 drive circuit main tappings are also fallen within the protection domain of this patent.
Preemphasis tap 20 is made of two above-mentioned improved LVDS driving units, the electric current width of M29, M30, M35, M36
It is worth for 2 times of M13, M14, M19, M20 current amplitude.Input (AP_1, AN_1, BP_1, BN_1, the CP_1 of preemphasis tap 20
And CN_1) be main tapping 10 input (AP, AN, BP, BN, CP and CN) through time delay module 30 be delayed a unit interval obtain
Arrive.The principle of preemphasis is similar with the preemphasis principle of foregoing NRZ crystal drive circuits, is not described in detail herein.
The present invention does not limit to the above embodiment, and anyone should learn that the structure change made under the enlightenment of the present invention
Change, the technical schemes that are same or similar to the present invention, each fall within protection scope of the present invention.
Claims (6)
1. save the preemphasis LVDS drive circuits of power consumption, it is characterised in that including：Main tapping, by CMOS differential signals INP,
INN is converted to LVDS differential signals OUTP, OUTN；Preemphasis tap, according to INP, INN and by INP, INN one unit of delay
CMOS differential signals INP_1, the INN_1 obtained after time interval produces corresponding current signal, in output signal OUTP, OUTN
To output node Injection Current in a unit interval after level conversion, the overshoot of an output voltage is produced, is increased
The high fdrequency component of output signal, so as to reach the effect of preemphasis；The main tapping include three PMOS tube M1, M2, M3 and
Three NMOS tubes M4, M5, M6；The grid of PMOS tube M1 meets bias voltage BIAS_UP, and source electrode meets power vd D；PMOS tube M2, M3
Grid connect respectively input CMOS differential signal INP, INN, PMOS tube M2, M3 source electrode interconnection and with the drain electrode phase of PMOS tube M1
Even；The grid of NMOS tube M6 connects bias voltage BIAS_DOWN, source electrode ground connection；The grid of NMOS tube M4, M5 meets input CMOS respectively
Differential signal INP, INN, the source electrode of NMOS tube M4, M5 are interconnected and are connected with the drain electrode of NMOS tube M6；The preemphasis tap bag
Include first, second PMOS switchable current sources 21,22, first, second NMOS switchable current sources 23,24, PMOS transistor M9,
M10, and nmos pass transistor M11, M12, the first, second PMOS switchable current sources 21,22 and first, second NMOS can be opened
Close current source 23,24 to be switched on and off by the control of input signal INP, INN, PMOS tube M9 and NMOS tube M11 are by input signal
INP_1 is controlled, and PMOS tube M10 and NMOS tube M12 control by input signal INN_1, the electric current of the switchable current source according to
The on off state of transistor M9, M10, M11, M12 are added on described output signal OUTP, OUTN；The preemphasis tap
First PMOS switchable current sources 21 include capacitance C1, PMOS tube M7 and M16, NMOS tube M15, NMOS tube M15 and PMOS tube M16
Source electrode connect the drain electrode of bias voltage BIAS_UP, NMOS tube M15 and PMOS tube M16 and connect the grid of PMOS tube M7, PMOS tube M7's
Source electrode connects power vd D, the grid of a termination PMOS tube M7 of capacitance C1, the grid of another termination PMOS tube M16 of capacitance C1；Institute
Stating the 2nd PMOS switchable current sources 22 includes capacitance C2, PMOS tube M8 and M18, NMOS tube M17, NMOS tube M17 and PMOS tube
The source electrode that the drain electrode of M18 meets bias voltage BIAS_UP, NMOS tube M17 and PMOS tube M18 connects the grid of PMOS tube M8, PMOS tube
The source electrode of M8 connects power vd D, the grid of a termination PMOS tube M8 of capacitance C2, the grid of another termination PMOS tube M18 of capacitance C2
Pole；The first NMOS switchable current sources 23 include capacitance C3, NMOS tube M13 and M19, PMOS tube M20, NMOS tube M19 and
The drain electrode that the source electrode of PMOS tube M20 meets bias voltage BIAS_DOWN, NMOS tube M19 and PMOS tube M20 connects the grid of NMOS tube M13
Pole, the source electrode ground connection of NMOS tube M13, the grid of a termination NMOS tube M13 of capacitance C3, another termination NMOS tube of capacitance C3
The grid of M19；The 2nd NMOS switchable current sources 24 include capacitance C4, NMOS tube M14 and M21, PMOS tube M22, NMOS
The source electrode that the drain electrode of pipe M21 and PMOS tube M22 meet bias voltage BIAS_DOWN, NMOS tube M21 and PMOS tube M22 connects NMOS tube
The grid of M14, the source electrode ground connection of NMOS tube M14, capacitance C4 mono- terminate the grid of NMOS tube M14, another termination of capacitance C4
The grid of NMOS tube M21；The grid of PMOS tube M9 and NMOS tube M11 meet input signal INP_1, and the source electrode of PMOS tube M9 meets PMOS
The drain electrode of pipe M7, the source electrode of NMOS tube M11 connect the drain electrode of NMOS tube M13, and the drain electrode of PMOS tube M9 and NMOS tube M11 connect output letter
Number OUTN；The source electrode that the grid of PMOS tube M10 and NMOS tube M12 meet input signal INN_1, PMOS tube M10 connects PMOS tube M8's
Drain electrode, the source electrode of NMOS tube M12 connect the drain electrode of NMOS tube M14, and the drain electrode of PMOS tube M10 and NMOS tube M12 connect output signal
OUTP。
2. the preemphasis LVDS drive circuits of power consumption are saved as claimed in claim 1, it is characterised in that preemphasis tap only exists
Have in a unit interval after OUTP, OUTN level conversion electric current by, it is in running order, at other times it is interior not
Can produce current signal be superimposed upon main tapping generation electric current on so that preemphasis tap without upper and lower double-current source not between
Cut-off electricity.
3. the preemphasis LVDS drive circuits of power consumption are saved as claimed in claim 1, it is characterised in that switchable current source bag
Include a static pullup/pulldown network being made of transmission gate and capacitance (passive pull up/down circuit)；This
A pullup/pulldown network can control being switched on and off for switchable current source.
4. the preemphasis LVDS drive circuits of power consumption are saved as claimed in claim 1, it is characterised in that the preemphasis tap
The preemphasis of level Four pulse amplitude modulation (PAM4) drive circuit and the pre-add of other pulse amplitude modulation circuits can be expanded to
Weight.
A kind of 5. PAM4 driving electricity that preemphasis LVDS drive circuits extension as claimed in claim 4 for saving power consumption forms
Road, it is characterised in that the main tapping of the PAM4 drive circuits includes the first LVDS driving units and the 2nd LVDS driving units,
The preemphasis LVDS of the structure of first LVDS driving units and the 2nd LVDS driving units and the saving power consumption described in claim 1
Drive circuit main tapping circuit structure is identical, and input signal is different；The input of first LVDS driving units is a pair of of Differential Input
Signal, the input of the 2nd LVDS driving units is two pairs of differential input signals；The electric current of 2nd LVDS driving unit current sources is big
Twice of the small size of current for being the first LVDS driving unit current sources；In the middle two-stage level of output level Four pulse amplitude
When, the 2nd LVDS driving units are off state.
A kind of 6. PAM4 driving electricity that preemphasis LVDS drive circuits extension as claimed in claim 4 for saving power consumption forms
Road, it is characterised in that the LVDS drivings that the preemphasis tap of the PAM4 drive circuits includes first band switchable current source are single
Member and the second LVDS driving units with switchable current source, the LVDS driving units and the second band of first band switchable current source
The preemphasis LVDS drive circuits of the structure of the LVDS driving units of switchable current source and the saving power consumption described in claim 1
Preemphasis tap structure is identical, and input signal is different；The second LVDS driving unit current sources with switchable current source are first
Twice of LVDS driving unit electric current source sizes with switchable current source；In the middle two-stage level of output level Four pulse amplitude
When, the second LVDS driving units with switchable current source are off state.
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| CN201410377242.2A CN104135272B (en) | 2014-07-31 | 2014-07-31 | Save the preemphasis LVDS drive circuits of power consumption |
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| CN201410377242.2A CN104135272B (en) | 2014-07-31 | 2014-07-31 | Save the preemphasis LVDS drive circuits of power consumption |
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| KR101621844B1 (en) * | 2014-05-08 | 2016-05-17 | (주) 픽셀플러스 | Low voltage differentail signal transmitter |
| CN104579378B (en) * | 2015-01-15 | 2017-04-19 | 中国科学技术大学先进技术研究院 | Low-voltage differential transmitter for achieving pre-emphasis circuit of capacitor |
| TWI748976B (en) * | 2016-02-02 | 2021-12-11 | 日商新力股份有限公司 | Sending device and communication system |
| CN106452424B (en) * | 2016-08-30 | 2019-04-09 | 西安空间无线电技术研究所 | A kind of differential driver with preemphasis |
| CN106598900B (en) * | 2016-11-25 | 2019-10-11 | 湖南国科微电子股份有限公司 | LVDS driver circuit |
| CN106849935A (en) * | 2016-12-23 | 2017-06-13 | 深圳市国微电子有限公司 | A kind of clock buffer drive circuit and PLD |
| CN108563599B (en) * | 2018-03-22 | 2020-06-16 | 深圳忆联信息系统有限公司 | M-phy driving circuit using voltage difference to match equivalent resistance |
| US10491428B2 (en) | 2018-04-27 | 2019-11-26 | Hewlett Packard Enterprise Development Lp | Current supply for an opto-electronic device |
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| CN109450435B (en) * | 2018-11-21 | 2024-02-13 | 灿芯半导体(上海)股份有限公司 | LVDS interface circuit |
| CN109783420B (en) * | 2019-01-09 | 2021-03-26 | 芯原微电子(上海)股份有限公司 | High-speed serial transmitter based on FDSOI technology and adopting phase pre-emphasis |
| CN110113071A (en) * | 2019-04-29 | 2019-08-09 | 天津大学 | A kind of low-power consumption LVDS circuit based on self-adaptive current adjusting method |
| CN114880263B (en) * | 2022-01-28 | 2023-04-14 | 上海先楫半导体科技有限公司 | Pre-emphasis circuit and low-voltage differential signal driver |
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| CN102545884A (en) * | 2012-02-17 | 2012-07-04 | 无锡芯骋微电子有限公司 | Voltage type data transmitter with high-efficiency pre-emphasis balance |
| CN102857211A (en) * | 2012-09-12 | 2013-01-02 | 四川和芯微电子股份有限公司 | Low-power-consumption drive and method for implementation of same |
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| CN104135272A (en) | 2014-11-05 |
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