CN104064464A - Transistor and formation method thereof - Google Patents
Transistor and formation method thereof Download PDFInfo
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- CN104064464A CN104064464A CN201310092798.2A CN201310092798A CN104064464A CN 104064464 A CN104064464 A CN 104064464A CN 201310092798 A CN201310092798 A CN 201310092798A CN 104064464 A CN104064464 A CN 104064464A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 238000000151 deposition Methods 0.000 claims description 29
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- 238000005468 ion implantation Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
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- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a transistor and a formation method thereof. The formation method of the transistor comprises: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a threshold voltage adjusting film, the surface of the threshold voltage adjusting film is provided with a barrier film, the surface of the barrier film is provided with a channel film, the threshold voltage adjusting film is internally provided with doped irons, the channel film is at an intrinsic state, and the barrier film is used for preventing penetration by the doped irons in the threshold voltage adjusting film; forming a grid structure on the surface of the channel film; forming a first side wall on the surface of the channel film at the two sides of the grid structure; by taking the grid structure and the first side wall as masks, etching the channel film, the barrier film, the threshold voltage adjusting film and a part of the semiconductor substrate to form a channel layer, a barrier layer and a threshold voltage adjusting layer; and forming a doping layer on the surface of the semiconductor substrate at the two sides of the threshold voltage adjusting layer, the barrier layer, the channel layer and the grid structure, wherein the surface of the doping layer is not lower than the surface of the channel layer. The performance of the formed transistor is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistor and forming method thereof.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor device in integrated circuit, especially MOS(Metal Oxide Semiconductor, Metal-oxide-semicondutor) size of device constantly dwindles, and meets the miniaturization of integrated circuit development and integrated requirement with this.In the process that continues to dwindle in the size of MOS transistor device, existing technique has been subject to challenge using silica or silicon oxynitride as the technique of gate dielectric layer.There are some problems using silica or silicon oxynitride as the transistor that gate dielectric layer was formed, comprised that leakage current increases and the diffusion of impurity, thereby affect transistorized threshold voltage, and then affect the performance of semiconductor device.
Prior art, in order accurately to control transistorized threshold voltage, can be adulterated ion to regulate in transistorized channel region.As shown in Figure 1, be the transistorized cross-sectional view in the channel region of prior art with doping ion, comprising: Semiconductor substrate 100; Be positioned at the doped region 110 of Semiconductor substrate 100; Be positioned at the gate dielectric layer 101 on 110 surfaces, doped region; Be positioned at the grid layer 102 on gate dielectric layer 101 surfaces; Be positioned at the side wall 103 on Semiconductor substrate 100 surfaces of gate dielectric layer 101 and grid layer 102 both sides; Be positioned at source region and the drain region 104 of the Semiconductor substrate 100 of side wall 103 and grid layer 102 both sides.Wherein, in described doped region 110, there is the ion that can regulate transistor threshold voltage, described doped region 110 in the time that transistor is worked as channel region.
But along with constantly dwindling of transistor feature size, transistorized operating voltage but cannot correspondingly reduce, and causes transistor dissipation excessive, is unfavorable for the integrated of system.
The more adjustable transistorized related data of multi-Vt please refer to the U.S. patent documents that publication number is US2012/0299111.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, reduces transistorized threshold voltage, reduces power consumption, improves the performance of transistor and semiconductor device.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprise: Semiconductor substrate is provided, described semiconductor substrate surface has threshold voltage adjustments film, described threshold voltage adjustments film surface has block film, and described block film surface has channel thin-film, in described threshold voltage adjustments film, has doping ion, described channel thin-film is eigenstate, and described block film is for stoping the doping ion penetration in threshold voltage adjustments film; Form grid structure on described channel thin-film surface; Channel thin-film surface in described grid structure both sides forms the first side wall; Taking described grid structure and the first side wall as mask, channel thin-film, block film, threshold voltage adjustments film and part semiconductor substrate, form channel layer, barrier layer and threshold voltage adjustments layer described in etching; Semiconductor substrate surface in described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides forms doped layer, and the surface of described doped layer is not less than channel layer surface.
Optionally, the material of described block film is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material, and the formation technique of described block film is selective epitaxial depositing operation.
Optionally, the material of described channel thin-film is silicon, and the formation technique of described channel thin-film is selective epitaxial depositing operation, and the thickness of described channel thin-film is 5 nanometer～20 nanometers.
Optionally, also comprise: ion adulterates in described channel thin-film, the ion adulterating is one or both in germanium and carbon, and the ion adulterating and the mol ratio of silicon atom are 0.01～0.5, and the ion adulterating is doped in channel thin-film by in-situ doped technique.
Optionally, the material of described threshold voltage adjustments film is silicon, in described silicon materials, doped with one or more combinations in carbon, germanium, tin and III-V family ion, the doping ion in described silicon materials is doped in silicon materials by in-situ doped technique or ion implantation technology.
Optionally, the formation technique of described threshold voltage adjustments film is: adopt selective epitaxial depositing operation to form silicon layer at semiconductor substrate surface; Adopt ion implantation technology or in-situ doped technique doped with II I-V family ion in described silicon layer.
Optionally, the formation technique of described threshold voltage adjustments film is: adopt ion implantation technology to Semiconductor substrate doped with II I-V family ion.
Optionally, described grid structure comprises: polysilicon layer and be positioned at the mask layer on described polysilicon layer surface, the material of described mask layer is one or more combinations in silica, silicon nitride and silicon oxynitride.
Optionally, also comprise: between channel layer and polysilicon layer, form gate dielectric layer, the material of described gate dielectric layer is silica or high K dielectric material.
Optionally, in the time that the material of described gate dielectric layer is high K dielectric material, also comprise: between channel layer and gate dielectric layer, form silicon oxide layer; Between gate dielectric layer and polysilicon layer, form protective layer, the material of described protective layer is tantalum nitride or tantalum nitride.
Optionally, in the time that the material of described gate dielectric layer is high K dielectric material, after forming doped layer, form dielectric layer on Semiconductor substrate, doped layer and the first side wall surface, described dielectric layer surface and grid structure flush; After forming dielectric layer, remove mask layer and polysilicon layer, to form opening; In described opening, form metal gate.
Optionally, the thickness of described the first side wall is 2 nanometer～8 nanometers, and material is silica, silicon nitride or silicon oxynitride.
Optionally, also comprise: before forming doped layer, form the second side wall at the semiconductor substrate surface of described channel layer, barrier layer and threshold voltage adjustments layer both sides, described the second side coping is lower than the surface of described channel layer.
Optionally, the material of described the second side wall is silica, silicon nitride or silicon oxynitride, and the material of described the second side wall is different from the material of the first side wall.
Optionally, the thickness of described doped layer is 30 nanometer～200 nanometers.
Optionally, the material of described doped layer is silicon, SiGe or carborundum, has p-type ion or N-shaped ion in described doped layer, and the formation technique of described doped layer is selective epitaxial depositing operation.
Optionally, bottom to the top of the concentration autodoping layer of described p-type ion or N-shaped ion raises gradually, and the concentration range of described p-type ion or N-shaped ion is 1e18～1e21/ cubic centimetre.
Optionally, described Semiconductor substrate is silicon substrate or silicon-on-insulator substrate, and the orientation index of described semiconductor substrate surface is <110> or <100>.
Accordingly, the invention provides a kind of transistor that adopts above-mentioned any one method to form, comprising: Semiconductor substrate; Be positioned at the threshold voltage adjustments layer of described semiconductor substrate surface, in described threshold voltage adjustments layer, there is doping ion; Be positioned at the barrier layer on described threshold voltage adjustments layer surface, described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer; Be positioned at the channel layer of described barrier layer surface, described channel layer is eigenstate; Be positioned at the grid structure on described channel layer surface; Be positioned at the doped layer of the semiconductor substrate surface of described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides, the surface of described doped layer and channel layer flush; The first side wall of the semiconductor substrate surface between threshold voltage adjustments layer and doped layer, described the first side coping is lower than channel layer surface.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form threshold voltage adjustments layer, the barrier layer on threshold voltage adjustments layer surface and the channel layer of barrier layer surface at semiconductor substrate surface.Wherein, barrier layer can stop the doping ion in threshold voltage adjustments layer to diffuse in the channel layer of eigenstate, avoid channel layer internal cause doping ion and produce random doping disturbance effect, make transistorized threshold voltage stablize, reduce and easily control, reduce transistorized power consumption, improve device performance.And because channel layer is eigenstate, therefore the carrier mobility in channel layer improves, transistor performance strengthens.Secondly, form the first side wall in grid structure both sides, taking the first side wall and grid structure after mask etching channel thin-film, block film and threshold voltage adjustments film, can continue etched portions Semiconductor substrate, and the sidewall of grid structure can not sustain damage, the degree of depth of etching is increased, the thickness of the follow-up doped layer that is formed at threshold voltage adjustments layer, separator and channel layer both sides increases, be conducive to the formation of described doped layer, can make the pattern of formed doped layer, quality good.
Further, semiconductor substrate surface in barrier layer and channel layer both sides forms the second side wall, and described the second side coping is lower than channel layer surface, described the second side wall can isolation threshold voltage regulating course and doped layer, avoid the Ion Phase counterdiffusion in ion and the doped layer in threshold voltage adjustments layer, transistorized stable performance.
Further, doped layer forms by selective epitaxial depositing operation, therefore can be by controlling the flow of the impurity gas passing in deposition process, foreign ion in doped layer is raise gradually from semiconductor substrate surface to doped layer surface, and the concentration impurity ion adulterating is easily accurately controlled by technique.And because formed doped layer thickness is thicker, the doping ion at described doped layer top is not easy to be passed down through doped layer and enters Semiconductor substrate, transistor performance is more stable.In addition, described doped layer forms by selective epitaxial depositing operation, can, by adjusting the material of doped layer, make to produce lattice mismatch between formed doped layer and channel layer, and provide stress to channel layer, to improve transistorized performance.
In transistor arrangement, between threshold voltage adjustments layer and channel layer, there is barrier layer, described barrier layer can prevent that the doping ion in threshold voltage adjustments layer from entering in channel layer, transistorized threshold voltage is stablized and easily controlled transistorized power-dissipation-reduced; And described channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.
Brief description of the drawings
Fig. 1 is the transistorized cross-sectional view in prior art channel region with doping ion;
Fig. 2 to Fig. 8 is the cross-sectional view of the transistorized forming process described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, although transistor feature size constantly reduces, transistorized operating voltage cannot correspondingly reduce, and causes transistor dissipation excessive.
Study discovery through the present inventor, along with transistorized feature size downsizing, the size of transistorized channel region is corresponding reducing also, causes the doping ion in channel region more responsive for the impact of threshold voltage.Concrete, the doping ion in channel region can produce random doping disturbance (RDF, RandomDopant Fluctuations) effect, and described random doping disturbance effect can produce threshold voltage deviations V
t, and threshold voltage deviations V
tvalue increase along with reducing of channel region size.Described threshold voltage deviations V
tcan make the cut-in voltage difference of different crystal pipe, in order to ensure transistorized normal work, put on transistorized operating voltage and need to be greater than threshold voltage and described threshold voltage deviations V
tsummation, then easily cause operating voltage too high, transistor dissipation is excessive.And, although adulterate ion in channel region time, can adjusting threshold voltage, prevent leakage current generating, in the time that the doping ion concentration in channel region is too high, can the migration of limiting carrier in channel region, affect transistorized performance.
The above-mentioned adverse effect of bringing for fear of the ion that adulterates in channel region, make transistorized threshold voltage controlled simultaneously, in one embodiment, in Semiconductor substrate, make the channel region that contacts gate dielectric layer be eigenstate, and the ion that adulterates below the channel region of described eigenstate, to form threshold voltage adjustments region.Because described channel region is eigenstate, therefore can not produce random doping disturbance effect, suppress threshold voltage deviations V
tgeneration, thereby can reduce threshold voltage, reduce device power consumption.And the channel region of eigenstate can not hinder the migration of charge carrier, the electric current in channel region increases, transistorized better performances.
But because the threshold voltage adjustments district that is positioned at below, channel region has doping ion, described doping ion very easily diffuses in the channel region of eigenstate, still can cause that transistorized threshold voltage is unstable, causes transistorized unstable properties.
Further study through the present inventor, there is barrier layer on formed threshold voltage adjustments layer surface, barrier layer surface has channel layer, described barrier layer can stop the doping ion in threshold voltage adjustments layer to diffuse in the channel layer of eigenstate, avoid channel layer internal cause doping ion and produce random doping disturbance effect, improve device performance.Secondly, making formed channel layer is eigenstate, and the carrier mobility in channel layer improves, and transistor performance strengthens.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 2 to Fig. 8 is the cross-sectional view of the transistorized forming process described in the embodiment of the present invention.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, form threshold voltage adjustments film 201 on described Semiconductor substrate 200 surfaces, in described threshold voltage adjustments film 201, there is doping ion.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided; Described Semiconductor substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates or silicon-on-insulator (SOI) substrate.The orientation index on described Semiconductor substrate 200 surfaces is <110> or <100>.
The follow-up threshold voltage adjustments layer that is used to form of described threshold voltage adjustments film 201, described threshold voltage adjustments layer is used for controlling transistorized threshold voltage, makes formed transistor threshold voltage meet design requirement; The material of described threshold voltage adjustments film 201 is semi-conducting material, comprises silicon or germanium, and has doping ion in described semi-conducting material, and described doping ion comprises one or more combinations in carbon, germanium, tin and III-V family ion; By adjusting the doping ion concentration in semi-conducting material, can accurately control transistorized threshold voltage.
In one embodiment, the formation technique of described threshold voltage adjustments film is: adopt selective epitaxial depositing operation to form silicon layer, doped with II I-V family ion in described silicon layer on Semiconductor substrate 200 surfaces.The technique of doped with II I-V family ion is: in described selective epitaxial deposition process, adopt the in-situ doped technique ion that adulterates in described silicon layer; The silicon layer thickness that adopts selective epitaxial depositing operation to form is accurate, and accurately easily control and concentration are even to adopt the ion concentration that in-situ doped technique adulterates, and make transistorized performance more stable; In addition, can also be after described selective epitaxial depositing operation, adopt the ion implantation technology ion that adulterates in described silicon layer.
In another embodiment, the formation technique of described threshold voltage adjustments film is: adopt ion implantation technology to Semiconductor substrate 200 doped with II I-V family ions, be positioned at surperficial region and form threshold voltage adjustments film 201 in described Semiconductor substrate 200.
Please refer to Fig. 3, form block film 202 on described threshold voltage adjustments film 201 surfaces, described block film 202 is for stoping the doping ion penetration in threshold voltage adjustments film 201; Form channel thin-film 203 on described block film 202 surfaces, described channel thin-film 203 is eigenstate.
The follow-up barrier layer that is used to form of described block film 202, the material of described block film 202 is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material, the formation technique of described block film 202 is selective epitaxial depositing operation; Because described block film 202 is the monocrystal material of SiGe, carborundum or Germanium carbon, in SiGe, carborundum or the silicon Germanium carbon material of monocrystalline, a little less than the diffusivity of doping ion, make the doping ion in threshold voltage adjustments film 201 be difficult to pass through, therefore described block film 202 can stop that doping ion in threshold voltage adjustments film 201 is to the interior diffusion of channel thin-film 203, and then can ensure eigenstate or the low-doped state of described channel thin-film 203; In the channel layer that follow-up described channel thin-film 203 forms, be difficult to produce random doping disturbance effect, operating voltage is reduced, improve transistorized performance.
In the present embodiment, the silicon that the material of described channel thin-film 203 is eigenstate or germanium, thickness is 5 nanometer～20 nanometers, forming technique is selective epitaxial depositing operation; In another embodiment, the ion of low concentration can also adulterate in described channel thin-film 203, described doping ion is one or both in germanium and carbon, the mol ratio of described doping ion and silicon atom is 0.01～0.5, and described doping ion is doped in channel thin-film 203 by in-situ doped technique or ion implantation technology.
The follow-up formation channel layer of described channel thin-film 203, described channel layer is as formed transistorized channel region; Because described channel thin-film 203 is eigenstate, or there is the doping ion of low concentration, in the channel layer that therefore described channel thin-film 203 forms, be difficult for random doping disturbance effect occurs, can not make threshold voltage produce deviation.Then without raising operational voltage value in order to ensure transistorized normal unlatching, formed transistorized threshold voltage is reduced, and then make transistorized Energy Intensity Reduction, improve the performance of the semiconductor device forming.
Secondly, because described channel thin-film 203 is eigenstate, or there is the doping ion of low concentration, in the channel region forming with described channel thin-film 203, the migration of charge carrier can not be hindered, and the carrier mobility in channel region improves, transistorized operating current improves, and transistorized performance strengthens.
And, owing to thering is block film 202 between threshold voltage adjustments film 201 and described channel thin-film 203, described block film 202 can prevent that doping ion in threshold voltage adjustments film 201 is to the interior diffusion of channel thin-film 203, the eigenstate or the low-doped state that have ensured described channel thin-film 203, make formed transistorized stable performance.
Please refer to Fig. 4, form grid structure (not shown) on described channel thin-film 203 surfaces.
Described grid structure comprises: polysilicon layer 205 and be positioned at the mask layer 206 on described polysilicon layer 205 surfaces, the material of described mask layer 206 is one or more combinations in silica, silicon nitride and silicon oxynitride.In the present embodiment, between described polysilicon layer 205 and channel thin-film 203, also have gate dielectric layer 204, the material of described gate dielectric layer 204 is silica or high K dielectric material.In the time that the material of described gate dielectric layer 204 is high K dielectric material, the transistor forming is high-K metal gate (HKMG, High-K Metal Gate) transistor, follow-up need to metal gate substitute described polysilicon layer 205; Described high K dielectric material comprises: hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.In the time that the material of described gate dielectric layer 204 is high K dielectric material, also between channel thin-film 203 and gate dielectric layer 204, form silicon oxide layer, strengthen the binding ability between described gate dielectric layer 204 and channel thin-film 203.
The formation technique of described grid structure is: at described channel thin-film 203 surface deposition gate dielectric membranes, in described gate dielectric membrane surface deposition polysilicon membrane, preferably chemical vapor deposition method of described depositing operation; Form mask layer 206 on described polysilicon membrane surface, described mask layer 206 has defined shape and the position of grid structure; Taking described mask layer 206 as mask, adopt polysilicon membrane and gate dielectric membrane described in anisotropic dry etch process etching, form polysilicon layer 205 and gate dielectric layer 204.It should be noted that, in the time that the material of gate dielectric layer 204 is high K dielectric material, before deposition gate dielectric membrane, adopt depositing operation or thermal oxidation technology to form silicon oxide layer on channel thin-film 203 surfaces.In addition,, in the time that the material of gate dielectric layer 204 is high K dielectric material, before deposited polycrystalline silicon thin film, at gate dielectric membrane surface deposition protective film, the material of described protective film is titanium nitride or tantalum nitride; After etch polysilicon film, described in etching protective film to form protective layer, described protective layer used when at follow-up removal polysilicon layer grill-protected dielectric layer 204 surfaces.
Please refer to Fig. 5, form the first side wall 207 on channel thin-film 203 surfaces of described grid structure both sides.
The material of described the first side wall 207 is silica, silicon nitride or silicon oxynitride, and the thickness of described the first side wall 207 is 2 nanometer～8 nanometers; The formation technique of described the first side wall 207 is: in channel thin-film 203 and grid structure surface deposition the first side wall film, preferably chemical vapor deposition method of described depositing operation; Return described in etching the first side wall film until expose mask layer 206 and channel thin-film 203.
Described the first side wall 207 and the grid structure mask during jointly as subsequent etching channel thin-film 203, block film 202 and threshold voltage adjustments film 201, has defined shape and the position of channel layer, barrier layer and threshold voltage adjustments layer that subsequent etching forms.Secondly, in subsequent etching technique, described the first side wall 207 can be protected the sidewall of polysilicon layer 205, avoids the size of described polysilicon layer 205 to dwindle, and has ensured that the size of grid structure is accurate, improves the stability of transistor performance.Again; because the sidewall surfaces of described polysilicon layer 205 is protected by described the first side wall 207; therefore described in follow-up etching again after threshold voltage adjustments film 201; can also continue etched portions Semiconductor substrate 200; and can not damage polysilicon layer 205; the total depth of described etching technics increases, and the thickness of the follow-up doped layer forming on Semiconductor substrate 200 surfaces of grid structure both sides increases, and is conducive to the formation of described doped layer.
Please refer to Fig. 6, taking described grid structure and the first side wall 207 as mask, described in etching, channel thin-film 203(is as shown in Figure 4), block film 202(as shown in Figure 4), threshold voltage adjustments film 201(as shown in Figure 4) and part semiconductor substrate 200, form channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a.
Described etching technics is anisotropic dry etch process, can make the sidewall of formed channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a vertical with Semiconductor substrate 200 surfaces, and the alignment of the sidewall of channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a; Described anisotropic dry etch process is determined according to material and the thickness of the channel thin-film 203 in concrete technology, block film 202 and threshold voltage adjustments film 201, and is well known to those skilled in the art, and should too not limit, and does not repeat at this.Described grid structure and the first side wall 207 have defined shape and the position of channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a jointly; And owing to there being the first side wall 207 to protect the sidewall of described grid structure, therefore described grid structure can not sustain damage, size can not change, and can make formed transistorized size accurate.
In the present embodiment, because the sidewall surfaces of described grid structure has the first side wall 207, therefore at etching channel thin-film 203, block film 202 and threshold voltage adjustments film 201 and after exposing Semiconductor substrate 200, can also continue etched portions Semiconductor substrate 200, and grid structure can not sustain damage, the size of grid structure can not change.After etching technics, be positioned at Semiconductor substrate 200 surfaces of threshold voltage adjustments layer 201a both sides lower than the lower surface of described threshold voltage adjustments layer 201a, the surface that is positioned at the Semiconductor substrate 200 of threshold voltage adjustments layer 201a both sides increases to the distance of the top surface of channel layer 203a, to be positioned at the process window of doped layer of channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a both sides larger in follow-up formation, is conducive to the formation of described doped layer.
Please refer to Fig. 7, form the second side wall 208 on Semiconductor substrate 200 surfaces of described channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a both sides, the top of described the second side wall 208 is lower than the surface of described channel layer 203a.
The material of described the second side wall 208 is silica, silicon nitride or silicon oxynitride, and the material of described the second side wall 208 is different from the material of the first side wall 207; The formation technique of described the second side wall 208 is: at Semiconductor substrate 200 and grid structure surface deposition the second side wall film; Return described in etching the second side wall film until expose mask layer 206 and Semiconductor substrate 200; The material of the second side wall 208 is different from the material of the first side wall 207, and therefore in described time etching technics, the removal that is difficult for being etched of described the first side wall 207, makes described the first side wall 207 can grill-protected electrode structure, has ensured that the size of described grid structure is accurate.
The second side wall 208 is isolated mutually for the doped layer that makes barrier layer 202a and channel layer 203a and follow-up formation; Because described doped layer is used for as transistorized source region or drain region, therefore in described doped layer, there is p-type or N-shaped ion, described the second side wall 208 can prevent that the ion in doped layer from spreading in barrier layer 202a or channel layer 203a, thereby suppress the generation of leakage current, make transistorized performance more stable.
And the top of described the second side wall 208 is lower than the surface of channel layer 203a, the doped layer of follow-up formation can contact with channel layer 203a, make described doped layer can serve as transistorized source region or drain region, and described channel layer 203a is as transistorized channel region.
Please refer to Fig. 8, form doped layer 209 on Semiconductor substrate 200 surfaces of described threshold voltage adjustments layer 201a, barrier layer 202a, channel layer 203a and grid structure both sides, the surface of described doped layer 209 is not less than channel layer 203a surface.
Described doped layer 209 is for as transistorized source region or drain region; The formation technique of described doped layer 209 is selective epitaxial depositing operation, the thickness of described doped layer 209 is 30 nanometer～200 nanometers, the material of described doped layer 209 is silicon, SiGe or carborundum, especially in the time that the material of described doped layer 209 is SiGe or carborundum, described doped layer 209 can provide stress to channel layer 203a; In the time that the transistor of required formation is PMOS transistor, the material of described doped layer 209 is SiGe, can provide compression to channel layer 203a, to improve the carrier mobility of channel region, improves transistorized performance; And in the time that the transistor of required formation is nmos pass transistor, the material of described doped layer 209 is carborundum, can provide tension stress to channel layer 203a.
Because described doped layer 209 is for as transistorized source region or drain region, interior doped p type ion or the N-shaped ion of needing of described doped layer 209; Wherein, described doping ion can be after selective epitaxial depositing operation forms doped layer 209, adopt ion implantation technology at the interior doping ion of described doped layer 209, can also be in described selective epitaxial deposition process, adopt in-situ doped technique at the interior doping ion of doped layer 209.Especially, in the time adopting in-situ doped technique, the ion concentration of adulterating can accurately be controlled, and then by controlling technological parameter, lower surface to the top surface of described doping ion autodoping layer 209 is raise gradually; Concrete, can be by increasing gradually the gas flow of doping ion, the concentration of the ion that makes to adulterate raises gradually, and the concentration range of described p-type or N-shaped doping ion is 1e18～1e21/ cubic centimetre.
Due to lower near the doping ion concentration of doped layer 209 bottoms, therefore can reduce the diffusion of doping ion.In the present embodiment, due to after etching forms channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a, continue etched portions Semiconductor substrate 200, make Semiconductor substrate 200 surfaces of grid structure both sides lower than the lower surface of threshold voltage adjustments layer 201a, the thickness of the doped layer 209 that formed increases, and the selective epitaxial depositing operation that is more conducive to form described doped layer 209 carries out.And, due to lower near the doping ion concentration of doped layer 209 bottoms, doping ion concentration near doped layer 209 tops is higher, when the thickness of described doped layer 209 increases, the doping ion that is positioned at doped layer 209 top area is difficult to diffuse into Semiconductor substrate 200 downwards, makes transistorized performance more stable.
It should be noted that, in the time that the material of described gate dielectric layer 204 is high K dielectric material, after forming doped layer 209, form dielectric layer (not shown), described dielectric layer surface and grid structure flush on Semiconductor substrate 200, doped layer 209 and the first side wall 207 surfaces; After forming dielectric layer, remove mask layer and polysilicon layer, to form opening; In described opening, form metal gate, form high-K metal gate transistor.
In the present embodiment, in the middle of threshold voltage adjustments layer and channel layer, form barrier layer, described barrier layer can stop the doping ion in threshold voltage adjustments layer to spread in the channel layer of eigenstate, ensure that channel layer can maintain eigenstate, avoid channel layer internal cause to there is doping ion and produce random doping disturbance effect, make formed transistor threshold voltage stable, thereby reduce transistorized power consumption, raising device performance.Secondly, because channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.Again, after etching channel thin-film, block film and threshold voltage adjustments film, due to the sidewall of the first side wall protection grid structure, can continue etched portions Semiconductor substrate, and the sidewall of grid structure can not sustain damage, the degree of depth of etching is increased, thereby the thickness of the doped layer that is formed at threshold voltage adjustments layer, separator and channel layer both sides is increased, be more convenient for forming described doped layer; And the doping ion that is positioned at doped layer top area is difficult to diffuse into Semiconductor substrate downwards, improves transistorized stability.
Accordingly, the present embodiment also provides a kind of transistor, please continue to refer to Fig. 8, comprising: Semiconductor substrate 200; Be positioned at the threshold voltage adjustments layer 201a on described Semiconductor substrate 200 surfaces, in described threshold voltage adjustments layer 201a, there is doping ion; Be positioned at the barrier layer 202a on described threshold voltage adjustments layer 201a surface, described barrier layer 202a is for stoping the doping ion penetration in threshold voltage adjustments layer 201a; Be positioned at the channel layer 203a on 202a surface, described barrier layer, described channel layer 203a is eigenstate; Be positioned at the grid structure on described channel layer 203a surface; Be positioned at the doped layer 209 on Semiconductor substrate 200 surfaces of described threshold voltage adjustments layer 201a, barrier layer 202a, channel layer 203a and grid structure both sides, the surface of described doped layer 209 and channel layer 203a flush; First side wall 207 on Semiconductor substrate 200 surfaces between threshold voltage adjustments layer 201a and doped layer 209, the top of described the first side wall 207 is lower than channel layer 203a surface.In addition, in the present embodiment, Semiconductor substrate 200 surfaces of described channel layer 203a, barrier layer 202a and threshold voltage adjustments layer 201a both sides also have the second side wall 208, and doped layer 209 is positioned at Semiconductor substrate 200 surfaces in described the second side wall 208 outsides.
In sum, form threshold voltage adjustments layer, the barrier layer on threshold voltage adjustments layer surface and the channel layer of barrier layer surface at semiconductor substrate surface.Wherein, barrier layer can stop the doping ion in threshold voltage adjustments layer to diffuse in the channel layer of eigenstate, avoid channel layer internal cause doping ion and produce random doping disturbance effect, make transistorized threshold voltage stablize, reduce and easily control, reduce transistorized power consumption, improve device performance.And because channel layer is eigenstate, therefore the carrier mobility in channel layer improves, transistor performance strengthens.Secondly, form the first side wall in grid structure both sides, taking the first side wall and grid structure after mask etching channel thin-film, block film and threshold voltage adjustments film, can continue etched portions Semiconductor substrate, and the sidewall of grid structure can not sustain damage, the degree of depth of etching is increased, the thickness of the follow-up doped layer that is formed at threshold voltage adjustments layer, separator and channel layer both sides increases, be conducive to the formation of described doped layer, can make the pattern of formed doped layer, quality good.
Further, semiconductor substrate surface in barrier layer and channel layer both sides forms the second side wall, and described the second side coping is lower than channel layer surface, described the second side wall can isolation threshold voltage regulating course and doped layer, avoid the Ion Phase counterdiffusion in ion and the doped layer in threshold voltage adjustments layer, transistorized stable performance.
Further, doped layer forms by selective epitaxial depositing operation, therefore can be by controlling the flow of the impurity gas passing in deposition process, foreign ion in doped layer is raise gradually from semiconductor substrate surface to doped layer surface, and the concentration impurity ion adulterating is easily accurately controlled by technique.And because formed doped layer thickness is thicker, the doping ion at described doped layer top is not easy to be passed down through doped layer and enters Semiconductor substrate, transistor performance is more stable.In addition, described doped layer forms by selective epitaxial depositing operation, can, by adjusting the material of doped layer, make to produce lattice mismatch between formed doped layer and channel layer, and provide stress to channel layer, to improve transistorized performance.
In transistor arrangement, between threshold voltage adjustments layer and channel layer, there is barrier layer, described barrier layer can prevent that the doping ion in threshold voltage adjustments layer from entering in channel layer, transistorized threshold voltage is stablized and easily controlled transistorized power-dissipation-reduced; And described channel layer is eigenstate, therefore the carrier mobility in channel layer improves, and transistor performance strengthens.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a transistorized formation method, is characterized in that, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface has threshold voltage adjustments film, described threshold voltage adjustments film surface has block film, described block film surface has channel thin-film, in described threshold voltage adjustments film, there is doping ion, described channel thin-film is eigenstate, and described block film is for stoping the doping ion penetration in threshold voltage adjustments film;
Form grid structure on described channel thin-film surface;
Channel thin-film surface in described grid structure both sides forms the first side wall;
Taking described grid structure and the first side wall as mask, channel thin-film, block film, threshold voltage adjustments film and part semiconductor substrate, form channel layer, barrier layer and threshold voltage adjustments layer described in etching;
Semiconductor substrate surface in described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides forms doped layer, and the surface of described doped layer is not less than channel layer surface.
2. transistorized formation method as claimed in claim 1, it is characterized in that, the material of described block film is SiGe, carborundum or Germanium carbon, and described SiGe, carborundum or silicon Germanium carbon material are monocrystal material, and the formation technique of described block film is selective epitaxial depositing operation.
3. transistorized formation method as claimed in claim 1, is characterized in that, the material of described channel thin-film is silicon, and the formation technique of described channel thin-film is selective epitaxial depositing operation, and the thickness of described channel thin-film is 5 nanometer～20 nanometers.
4. transistorized formation method as claimed in claim 3, it is characterized in that, also comprise: ion adulterates in described channel thin-film, the ion adulterating is one or both in germanium and carbon, the ion adulterating and the mol ratio of silicon atom are 0.01～0.5, and the ion adulterating is doped in channel thin-film by in-situ doped technique.
5. transistorized formation method as claimed in claim 1, it is characterized in that, the material of described threshold voltage adjustments film is silicon, in described silicon materials, doped with one or more combinations in carbon, germanium, tin and III-V family ion, the doping ion in described silicon materials is doped in silicon materials by in-situ doped technique or ion implantation technology.
6. transistorized formation method as claimed in claim 5, is characterized in that, the formation technique of described threshold voltage adjustments film is: adopt selective epitaxial depositing operation to form silicon layer at semiconductor substrate surface; Adopt ion implantation technology or in-situ doped technique doped with II I-V family ion in described silicon layer.
7. transistorized formation method as claimed in claim 5, is characterized in that, the formation technique of described threshold voltage adjustments film is: adopt ion implantation technology to Semiconductor substrate doped with II I-V family ion.
8. transistorized formation method as claimed in claim 1, it is characterized in that, described grid structure comprises: polysilicon layer and be positioned at the mask layer on described polysilicon layer surface, the material of described mask layer is one or more combinations in silica, silicon nitride and silicon oxynitride.
9. transistorized formation method as claimed in claim 8, is characterized in that, also comprises: between channel layer and polysilicon layer, form gate dielectric layer, the material of described gate dielectric layer is silica or high K dielectric material.
10. transistorized formation method as claimed in claim 9, is characterized in that, in the time that the material of described gate dielectric layer is high K dielectric material, also comprises: between channel layer and gate dielectric layer, form silicon oxide layer; Between gate dielectric layer and polysilicon layer, form protective layer, the material of described protective layer is tantalum nitride or tantalum nitride.
11. transistorized formation methods as claimed in claim 9, it is characterized in that, in the time that the material of described gate dielectric layer is high K dielectric material, after forming doped layer, form dielectric layer at described doped layer and the first side wall surface, described dielectric layer surface and grid structure flush; After forming dielectric layer, remove mask layer and polysilicon layer, to form opening; In described opening, form metal gate.
12. transistorized formation methods as claimed in claim 1, is characterized in that, the thickness of described the first side wall is 2 nanometer～8 nanometers, and material is silica, silicon nitride or silicon oxynitride.
13. transistorized formation methods as claimed in claim 1, it is characterized in that, also comprise: before forming doped layer, semiconductor substrate surface in described channel layer, barrier layer and threshold voltage adjustments layer both sides forms the second side wall, and described the second side coping is lower than the surface of described channel layer.
14. transistorized formation methods as claimed in claim 13, is characterized in that, the material of described the second side wall is silica, silicon nitride or silicon oxynitride, and the material of described the second side wall is different from the material of the first side wall.
15. transistorized formation methods as claimed in claim 1, is characterized in that, the thickness of described doped layer is 30 nanometer～200 nanometers.
16. transistorized formation methods as claimed in claim 1, is characterized in that, the material of described doped layer is silicon, SiGe or carborundum, has p-type ion or N-shaped ion in described doped layer, and the formation technique of described doped layer is selective epitaxial depositing operation.
17. transistorized formation methods as claimed in claim 16, is characterized in that, bottom to the top of the concentration autodoping layer of described p-type ion or N-shaped ion raises gradually, and the concentration range of described p-type ion or N-shaped ion is 1e18～1e21/ cubic centimetre.
18. transistorized formation methods as claimed in claim 1, it is characterized in that, described Semiconductor substrate is silicon substrate or silicon-on-insulator substrate, and the orientation index of described semiconductor substrate surface is <110> or <100>.
19. 1 kinds of employings as the transistor that claim 1 to 18 any one method is formed, is characterized in that, comprising: Semiconductor substrate; Be positioned at the threshold voltage adjustments layer of described semiconductor substrate surface, in described threshold voltage adjustments layer, there is doping ion; Be positioned at the barrier layer on described threshold voltage adjustments layer surface, described barrier layer is for stoping the doping ion penetration in threshold voltage adjustments layer; Be positioned at the channel layer of described barrier layer surface, described channel layer is eigenstate; Be positioned at the grid structure on described channel layer surface; Be positioned at the doped layer of the semiconductor substrate surface of described threshold voltage adjustments layer, barrier layer, channel layer and grid structure both sides, the surface of described doped layer and channel layer flush; The first side wall of the semiconductor substrate surface between threshold voltage adjustments layer and doped layer, described the first side coping is lower than channel layer surface.
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