CN104064161B - Data transmission system applied to display and operation method - Google Patents

Abstract

The invention discloses a data transmission system applied to a display, which comprises a transmitting end and a receiving end. The transmitting terminal is used for receiving the first clock signal and providing a display data stream according to the first clock signal. The receiving end comprises an error detection module and a clock data recovery circuit. The error detection module is used for judging whether the display data stream received by the receiving end has errors according to the second clock pulse signal and providing an error signal to the transmitting end according to the judgment result so that the transmitting end transmits the clock pulse calibration signal through the display data stream. The clock data recovery circuit is used for updating the second clock signal according to the clock calibration signal.

Description

Data transmission system and operation method applied to display

technical field

The present invention relates to an electronic system. In particular, a data transmission system and operation method applied to a display.

Background technique

With the rapid development of electronic technology, displays have been widely used in people's lives, such as mobile phones or notebook computers.

In general, a display may include a timing controller and a source driver. The timing controller can provide image data to the source driver through the data transmission interface, so that the source driver can provide proper data voltage to the pixels in the display. The pixels update their display states (such as color and gray scale) according to the data voltage. In this way, the monitor can display images.

Traditionally, the timing controller transmits the clock signal and image data to the source driver through different transmission channels. However, in this way, the clock signal and image data are likely to be misaligned due to transmission delay, so that the source driver cannot receive the image data correctly, resulting in instability of the display.

Therefore, how to solve this problem is an important research direction in this field.

Contents of the invention

An aspect of the present invention is to provide a data transmission system applied to a display. According to an embodiment of the present invention, a data transmission system includes a transmitting end and a receiving end. The transmitting end is used for generating a first clock signal and providing a display data stream according to the first clock signal. The receiving end is used for receiving the display data stream. The receiving end includes an error detection module and a clock data recovery circuit. The error detection module is used to judge whether the display data stream received by the receiving end has an error according to the second clock signal, and is used to provide an error signal to the transmitting end according to the judgment result, so that the transmitting end transmits clock calibration through the display data stream Signal. The clock data recovery circuit is used for updating the second clock signal according to the clock calibration signal.

Another aspect of the present invention is to provide an operating method applied to a display. According to an embodiment of the present invention, the display includes a transmitting end and a receiving end. The operation method includes: providing a display data stream according to the first clock signal through the transmitting end; receiving the display data stream through the receiving end, judging whether the display data stream has an error according to the second clock signal, and providing a display data stream according to the judgment result. An error signal; through the transmitting end, according to the error signal, a clock calibration data is transmitted through the display data stream; and through the receiving end, a second clock signal is updated according to the clock calibration data.

By applying the above-mentioned one embodiment, transmitting the clock calibration signal in the display data stream can prevent the clock signal and image data from being out of alignment due to transmission delay, so as to improve the stability of the display. In addition, using the error detection module to detect errors in the display data stream can notify the transmitting end when an error occurs in the display data stream, so that the transmitting end can perform corresponding error control accordingly. In this way, the stability of the display can be further improved.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a display according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a data transmission system according to an embodiment of the present invention;

FIG. 3A is a schematic diagram of a transmitting end according to an embodiment of the present invention;

FIG. 3B is a schematic diagram of a receiving end according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a display data stream according to an embodiment of the present invention;

FIG. 5 is a flowchart of an operation method according to an embodiment of the present invention; and

FIG. 6 is a schematic diagram illustrating a display data flow according to an operation example of the present invention.

Among them, reference signs:

10: Display

20: Timing controller

30: Source driver

40: Gate driver

100: Data transmission system

104: pixel array

106: pixels

110: Transmitter

111: PLL

112: Encoder

113: Processor

114: Converter

115: Teleporter

120: Receiver

121: Receiver

122: Clock data recovery circuit

123: Converter

124: Debug module

125: Decoder

126: Control module

G(1)-G(N): scan signal

D(1)-D(M): data signal

DS-S: Display Data Stream

DS-P: display data flow

LK: error signal

CLK1: the first clock signal

CLK2: Second clock signal

conf: set data

DT: image data

DT-E: encoded image data

FM: frame data

L(1)-L(N): data frame

CN: data frame

VB: Data Frame

H-BK: horizontal masking code

V-BK: vertical masking code

BAC: bit synchronization code

CTRL: control code

EOL: end code

TAJ: Clock calibration signal

S1-S13: Steps

t0-t11: point in time

detailed description

The following will clearly illustrate the spirit of the present invention with the accompanying drawings and detailed descriptions. After any person skilled in the art understands the preferred embodiments of the present invention, they can be changed and modified by the technology taught by the present invention. It does not depart from the spirit and scope of the present invention.

The terms "first", "second" and the like used herein do not refer to a sequence or sequence, nor are they used to limit the present invention, but are only used to distinguish elements or operations described with the same technical terms.

Regarding the "electrical connection" used herein, it can refer to two or more elements that are in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and "electrical connection" can also refer to two or more components. Multiple elements operate or act on each other.

As used herein, "comprising", "comprising", "having", "comprising" and so on are all open terms, meaning including but not limited to.

As used herein, "and/or" includes any or all combinations of the stated things.

The terms "approximately", "about" and the like used herein are used to modify any quantity or error that may vary slightly, but such slight changes or errors will not change its essence. Generally speaking, the range of slight variation or error modified by such terms is 20%, in some preferred embodiments, it is 10%, in some more preferred embodiments, it is 5%.

Regarding the terms used herein, unless otherwise specified, generally have the ordinary meanings of each term used in this field, in the disclosed content and in the special content. Certain terms used to describe the present invention are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the present invention.

An aspect of the present invention is to provide a data transmission system. In the following embodiments, an intra-panel interface of a display panel will be used as an example for illustration, but the present invention is not limited thereto.

FIG. 1 is a schematic diagram of a display 10 according to an embodiment of the present invention. The display 10 may include a timing controller 20 , a source driver 30 , a gate driver 40 and a pixel array 104 . The timing controller 20 is electrically connected to the source driver 30 and the gate driver 40 respectively. The source driver 30 and the gate driver 40 are electrically connected to the pixel array. Pixel array 104 may include a plurality of pixels 106 arranged in a matrix. The timing controller 20 can provide a control signal to the gate driver 40, so that the gate driver 40 can sequentially provide a plurality of scanning signals G(1), . / Turn on the pixels 106 row by row, where N is a natural number. In addition, the timing controller 20 can provide display data to the source driver 30 so that the source driver 30 can provide data signals D(1), . . . , D(M) to the turned-on pixels 106 so that the turned-on pixels 106 Update its display status (such as color and gray scale), where M is a natural number. In this way, the image can be displayed on the display 10 .

In some approaches, the timing controller 20 provides the clock signal and the image data to the source driver 30 respectively. However, in this way, the clock signal and the image data are likely to be misaligned due to transmission delay, so that the source driver 30 cannot receive the image data correctly, resulting in instability of the display 10 . Therefore, in an embodiment of the present invention, the stability of the display 10 can be improved by providing a new data transmission system 100 between the timing controller 20 and the source driver 30 .

FIG. 2 is a schematic diagram of a data transmission system 100 according to an embodiment of the present invention. In this embodiment, the data transmission system 100 includes a transmitting end 110 and a plurality of receiving ends 120, wherein the transmitting end 110 is located in the timing controller 20, and the receiving ends 120 are respectively located in different source drivers 30 and are electrically connected to each other. Transmitter 110. In some embodiments, the source drivers 30 are respectively used to output data signals to the pixels 106 in different columns. In addition, it should be noted that in this embodiment, six source drivers 30 and receiving ends 120 are taken as an example for illustration, but actually the number of source drivers 30 and receiving ends 120 is not limited thereto. In different embodiments, the quantity of the source driver 30 and the receiving end 120 may vary according to actual requirements.

In this embodiment, the timing controller 20 communicates with the source driver 30 through the data transmission system 100 . For example, the timing controller 20 can transmit the display data stream DS-S to the source driver 30 through the data transmission system 100 . On the other hand, when the source driver 30 finds an error (such as finding its own error or an error in the display data stream DS-S), the source driver 30 can transmit the error signal LK to the timing controller through the data transmission system 100 20, indicating that the source driver 30 itself is in an error state, so that the timing controller 20 can perform related control to eliminate errors.

In this embodiment, the transmission channel used to transmit the error signal LK may be a single-wire transmission channel. That is, each source driver 30 provides the error signal LK to the timing controller 20 through the same transmission channel. When any one of the source drivers 30 is in an error state, the source driver 30 provides an error signal LK (such as a signal of a low voltage level) to this transmission channel, so that the timing controller 20 can eliminate errors related controls. By doing so, the area occupied by the transmission channel can be reduced.

It should be noted that in different embodiments, the source driver 30 can also use multiple transmission channels to transmit the error signal LK, and the present invention is not limited to the above embodiments.

FIG. 3A is a schematic diagram of the transmitting end 110 according to an embodiment of the present invention. In this embodiment, the transmitting end 110 includes a phase locked loop 111 , an encoder 112 , a processor 113 , a converter 114 and a transmitter 115 . The PLL 111 is electrically connected to the encoder 112 , the processor 113 and the converter 114 . The encoder 112 is electrically connected to the processor 113 . The processor 113 is electrically connected to the converter 114 . The converter 114 is electrically connected to the transmitter 115 . In this embodiment, the phase-locked loop 111 , the encoder 112 , the processor 113 , the converter 114 and the transmitter 115 can all be implemented with specific circuits.

Those skilled in the art should clearly understand that the implementation of the above-mentioned phase-locked loop 111, encoder 112, processor 113, converter 114, and transmitter 115 is not limited to those disclosed in the above-mentioned embodiments, and the connection relationship is not limited to those disclosed in the above-mentioned embodiments. The above-mentioned embodiments are limited, and any connection method and implementation method sufficient to enable the transmitting end 110 to realize the following technical content can be applied to the present invention.

In this embodiment, the phase-locked loop 111 is used to receive and generate the first clock signal CLK1 to the encoder 112, the processor 113 and the converter 114, so that the encoder 112, the processor 113 and the converter 114 are based on the first The clock signal CLK1 performs respective operations.

In this embodiment, the encoder 112 is used to receive the image data DT, encode the image data DT, and provide the encoded image data DT-E to the processor 113 . In one embodiment, the encoder 112 can be an 8-bit to 9-bit encoder (8b/9bencoder), used to encode the 8-bit image data DT into 9-bit encoded image data DT-E . However, in practice, the type of the encoder 112 may vary according to actual requirements. In different embodiments, the encoder 112 can also be a 4-bit to 5-bit encoder or a 12-bit to 14-bit encoder, etc. The present invention is not limited to the above-mentioned embodiments.

In this embodiment, the processor 113 is configured to receive the encoded image data DT-E, the setting data CONF, and the error signal LK from the receiving end 120 . The processor 113 is used for arranging the encoded image data DT-E and configuration data CONF according to the data format predefined by the data transmission system 100 , so as to output the display data stream DS-P to the converter 114 . For the specific content of the display data stream DS-P, refer to FIG. 4 , and related content will be described in detail in subsequent paragraphs.

In addition, when the processor 113 receives the error signal LK from the receiving end 120, the processor 113 can transmit the clock calibration signal TAJ to each receiving end 120, so that each receiving end 120 can update its clock accordingly. Signal. The specific details about the clock alignment signal TAJ will be detailed in the following paragraphs.

In this embodiment, the converter 114 is used to receive the display data stream DS-P, and convert the parallel display data stream DS-P into a serial display data stream DS-P according to the transmission format predefined by the data transmission system 100. S, and provide the display data stream DS-S in serial form to the transmitter 115, so that the transmitter 115 performs the transmission operation accordingly. Besides, in this embodiment, the converter 114 generates the display data stream DS-S in serial form according to the first clock signal CLK1. That is, in each cycle of the first clock signal CLK1 , the converter 114 generates a serial display data stream DS-S. By doing so, the first clock signal CLK1 can be embedded in the display data stream DS-S for transmission.

In this embodiment, the transmitter 115 is used to receive the display data stream DS-S in serial form, and transmit the display data stream DS-S in serial form to the receiving end 120 through the transmission channel. In one embodiment, the transmitter 115 transmits the 2-bit serial display data stream DS-S to the receiving end 120, and the bandwidth of the transmission channel is also 2 bits.

With the above configuration, the transmitting end 110 can provide the display data stream DS-P to the receiving end 120 according to the first clock signal CLK1.

FIG. 3B is a schematic diagram of the receiving end 120 according to an embodiment of the present invention. The receiving end 120 includes a receiver 121 , a clock data recovery circuit 122 , a converter 123 , an error detection module 124 , a decoder 125 and a control module 126 . In this embodiment, the receiver 121 is electrically connected to the clock data recovery circuit 122 , the converter 123 and the control module 126 . The clock data recovery circuit 122 is electrically connected to the converter 123 , the error detection module 124 and the decoder 125 . The converter 123 is electrically connected to the debugging module 124 and the control module 126 . The error detection module 124 is electrically connected to the decoder 125 . The decoder 125 is electrically connected to the control module 126 . In this embodiment, the receiver 121 , the clock data recovery circuit 122 , the converter 123 , the error detection module 124 , the decoder 125 and the control module 126 can all be realized by circuits.

Those skilled in the art can clearly understand that the implementation of the receiver 121, the clock data recovery circuit 122, the converter 123, the error detection module 124, the decoder 125 and the control module 126 is not limited to those disclosed in the above embodiments. , and the connection relationship is not limited to the above-mentioned embodiments, and any connection and implementation methods that are sufficient for the receiving end 120 to realize the following technical content can be applied to the present invention.

In this embodiment, the receiver 121 is used to receive the display data stream DS-S in serial form from the transmitting end 110, and provide the display data stream DS-S in serial form to the clock data recovery circuit 122, Converter 123 and control module 126 . In this embodiment, the receiver 121 can be implemented with a comparator. The form of the receiver 121 and the form of the transmitter 115 correspond to each other.

In this embodiment, the clock data recovery circuit 122 is used to receive the serial display data stream DS-S, generate the second clock signal CLK2 according to the serial display data stream DS-S, and provide the second clock signal. The pulse signal CLK2 is sent to the converter 123 , the error detection module 124 and the decoder 125 , so that the converter 123 , the error detection module 124 and the decoder 125 perform respective operations based on the second clock signal CLK2 . In one embodiment, the frequency of the second clock signal CLK2 is substantially the same as that of the first clock signal CLK1 .

In a further embodiment, the clock data recovery circuit 122 receives the clock calibration signal TAJ in the serial display data stream DS-S, and generates or updates the second clock signal CLK2 accordingly. Related operations will be detailed in subsequent paragraphs.

In addition, in an embodiment, the clock data recovery circuit 122 can be realized by a phase locked loop (phase lock loop, PLL) or a delay locked loop (delay lock loop, DLL).

In this embodiment, the converter 123 is used to receive the second clock signal CLK2 and the serial display data stream DS-S, and convert the serial display data stream DS-S according to the second clock signal CLK2 Convert to parallel display data stream DS-P. In this embodiment, the form of the converter 123 and the form of the converter 114 correspond to each other.

In this embodiment, the error detection module 124 is used to receive the second clock signal CLK2 and the display data stream DS-P from the converter 123, and according to the content of the second clock signal CLK2 and the display data stream DS-P, It is judged whether the display data stream DS-P has an error. Then, the error detection module 124 is used to provide an error signal LK to the transmitting end 110 according to the judgment result, so that the processor 113 of the transmitting end 110 transmits the clock calibration signal TAJ through the display data stream DS-P/DS-S.

For example, when the error detection module 124 determines that the display data stream DS-P has an error, the error detection module 124 provides an error signal LK (such as a signal of a low voltage level) to the transmitting end 110 . At this time, the processor 113 of the transmitting end 110 transmits the clock calibration signal TAJ in the display data stream DS-P/DS-S to the clock data recovery circuit 122 in each source driver 30 according to the error signal LK. These clock data recovery circuits 122 update the second clock signal CLK2 according to the clock calibration signal TAJ, so that the frequency and phase of the second clock signal CLK2 are realigned with the first clock signal CLK1 (it should be noted that due to the signal Due to the propagation delay, the phase of the second clock signal CLK2 is actually slightly behind the phase of the first clock signal CLK1). Then, the transmitting end 110 can retransmit the same data (such as the same data frame) or directly transmit the next data (such as the next data frame or the next data frame).

Through the above-mentioned mechanism, when the second clock signal CLK2 is out of alignment and/or when an error occurs in the transmission of the display data stream DS-S/DS-P, the error detection module 124 can notify the transmitting end of the detected error 110 transmits the clock alignment signal TAJ to realign the frequencies and phases of the first and second clock signals CLK1 and CLK2 . Then, the transmitting end 110 continues to transmit data. Thereby, the display 10 can be made more stable.

In addition, in this embodiment, the decoder 125 is used to receive the display data stream DS-P from the error detection module 124, and decode the encoded image data DT-E in the display data stream DS-P to generate a decoded The image data DT of . Then, the decoder 125 can provide the decoded image data DT to related components at the back end of the source driver 30 , so that these related components generate data signals D( 1 ), . . . , D(M) according to the image data DT.

Furthermore, the decoder 125 may also provide the setting data CONF in the display data stream DS-P to the control module 126, so that the control module 126 performs corresponding control according to the setting data CONF (for example, controlling the color depth bit of the source driver 30 (colordepthbit)).

FIG. 4 is a schematic diagram of a display data stream DS-P according to an embodiment of the invention. The display data stream DS-P includes a plurality of frame data FM. The display 10 displays an image of each frame according to each piece of frame data FM.

In this embodiment, each frame of data FM sequentially includes a plurality of data frames L(1), L(2), . . . , L(N), CN, VB of the frame. The data frames L(1)-L(N) of one frame data FM respectively include the scanline data (scanline data) of columns 1-N of the frame. In each frame, the display 10 makes each column of pixels 106 display the image of the frame according to the scan line data of columns 1-N of the frame.

In addition, the data frame CN includes configuration data CONF. The timing controller 20 controls the source driver 30 (for example, controls the color depth bit of the source driver 30 ) through the data frame CN.

Furthermore, the data frame VB includes a vertical blanking code V-BK. The data frame VB is the last data frame of a frame data FM.

In this embodiment, the data frames L(1), L(2), . . . L(N), CN, VB all include the horizontal mask code H-BK and the operation data OPD. The operation data OPD of the data frames L(1), L(2), . The operation data OPD of the data frame CN includes bit synchronization code BAC, control code CTRL, setting data CONF and end code EOL in sequence. The operation data OPD of the data frame VB sequentially includes a bit synchronization code BAC, a control code CTRL, and a vertical mask code V-BK.

In this embodiment, the bit alignment code (bitalignment code) BAC in each data frame is the first sequential data in the operation data OPD, corresponding to the start position of the operation data OPD. The control code CTRL in each data frame is the second order data adjacent to the bit synchronization code BAC in the operation data OPD, which can be used to indicate the type of data frame (for example, data frame L(1)-L( N) or data frame CN). Each end code EOL is the last sequential data in the operation data OPD of the data frame L(1), L(2), ... L(N), CN, corresponding to the data frame L(1), L(2) , ...L(N), the end position of the operation data OPD of CN. Each encoded image data DT-E is respectively the 1-N scan line data in the frame data FM.

In addition, the transmitting end 110 transmits the horizontal blanking code H-BK and the vertical blanking code V-BK to the receiving end 120 corresponding to the horizontal blanking period or the vertical blanking period of the display 10 .

In order to make the technical content of the embodiment of the present invention easier to understand, the specific details of the present invention will be described below with an operation example in conjunction with FIGS. 5-6 .

Referring to FIGS. 5 and 6 at the same time, FIG. 5 is a flowchart of an operating method of the display 10 according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a display data stream DS-P/DS-S according to an operation example of the present invention. The operation method includes the following steps.

In step S1, after the display 10 is activated, the transmitting end 110 transmits the clock calibration signal TAJ to the receiving end 120 through the display data stream DS-S/DS-P (refer to time point t0-t1 in FIG. 6 ).

In step S2 , when the receiving end 120 receives the clock calibration signal TAJ, the receiving end 120 generates the second clock signal CLK2 according to the clock calibration signal TAJ through the clock data recovery circuit 122 . Then, before the second clock signal CLK2 is updated next time, the converter 123 , the error detection module 124 and the decoder 125 of the receiving end 120 all operate according to the second clock signal CLK2 .

In step S3, the transmitting end 110 transmits the horizontal masking code H-BK to the receiving end 120 through the display data stream DS-S/DS-P (refer to time points t1-t2 in FIG. 6 ).

In step S4, when the receiving end 120 receives the horizontal masking code H-BK, the receiving end 120 judges whether the horizontal masking code H-BK has errors through the error detection module 124 . More specifically, the error detection module 124 compares these horizontal masking codes H-BK with a preset masking code format to determine whether at least one of these horizontal masking codes H-BK conforms to the preset format. The encoding format of the masking code is set, and it is determined whether to provide the error signal LK to the transmitting end 110 accordingly. The so-called "masking code encoding format" here refers to the encoding format predefined by the designer. Under normal circumstances, each horizontal masking code H-BK should conform to the preset masking code encoding format, so according to whether the horizontal masking code H-BK received by the receiving end 120 conforms to the masking code encoding format, you can It is learned whether an error occurs in the display data stream DS-S/DS-P and/or the second clock signal CLK2.

In the case that one or more of the horizontal masking codes H-BK do not conform to the preset masking code encoding format, the receiving end 120 judges an error through the error detection module 124, and proceeds to step S14. Otherwise, go to step S5.

In step S14, the receiving end 120 transmits the error signal LK to the transmitting end 110 through the error detection module 124, and the process returns to step S1.

It should be noted that the conditions for the error detection module 124 to transmit the error signal LK (such as the number of consecutive errors in the horizontal masking code H-BK) can vary according to actual needs, and the present invention is not limited to the above-mentioned embodiments.

In step S5, the transmitting end 110 sequentially transmits the bit synchronization code BAC and the control code CTRL to the receiving end 120 through the display data stream DS-S/DS-P (refer to time points t2-t4 in FIG. 6 ).

In step S6 , when the receiving end 120 receives the bit control code CTRL, the receiving end 120 judges whether the control code CTRL is correctly received through the error detection module 124 . Specifically, after receiving the bit synchronization code BAC (that is, the first operation sequence data of the operation data OPD (refer to FIG. 4 )), the error detection module 124 judges the second operation data adjacent to the bit synchronization code BAC in the operation data OPD. Whether the sequence data conforms to at least one preset control code encoding format determines whether the receiving end 120 receives the control code CTRL correctly. Here, the so-called "control code encoding format" is predefined by the designer and can be used to represent the encoding format of the data frame type. Under normal circumstances, the control code CTRL should conform to the control code encoding format, so according to whether the control code CTRL received by the receiving end 120 conforms to the control code encoding format, it can be known that the display data stream DS-S/DS-P and/or Whether an error occurs in the second clock signal CLK2.

More specifically, in this operation example, the receiving end 120 essentially judges whether the second order data adjacent to the bit synchronization code BAC in the operation data OPD conforms to the preset image frame encoding format and preset settings. Frame coding format or the default masking code frame coding format.

In the case that the second order data adjacent to the bit synchronization code BAC in the operation data OPD does not conform to any preset control code encoding format, the receiving end 120 judges that an error occurs through the error detection module 124, and proceeds to step S14 . On the contrary, if the control code CTRL conforms to the preset image frame encoding format, then proceed to step S7, and if the control code CTRL conforms to the preset setting frame encoding format, then proceed to step S10, and if If the control code CTRL conforms to the preset frame encoding format of the masking code, proceed to step S12.

In step S7, if the control code CTRL transmitted by the transmitting end 110 conforms to the preset video frame encoding format, it means that the transmitting end 110 is transmitting one of the data frames L(1)-L(N) , the transmitting end 110 transmits multiple pieces of encoded image data DT-E (refer to time points t4-t5 in FIG. 6 ).

In step S8, when the receiving end 120 receives the aforementioned encoded image data DT-E, the receiving end 120 judges whether at least one of the encoded image data DT-E conforms to the preset through the error detection module 124. The image data encoding format set. The so-called "image data encoding format" here refers to the encoding format of the encoded image data DT-E. For example, in the case that the encoder 112 of the transmitting end 110 is an 8-bit to 9-bit encoder, the error detection module 124 is to judge whether the image data DT-E conforms to the output of the 8-bit to 9-bit encoder encoding format to determine whether to transmit the error signal LK to the transmitting end 110 . Under normal circumstances, each encoded image data DT-E should conform to the image data encoding format, so according to whether the image data DT-E received by the receiving end 120 conforms to the image data encoding format, the display data stream DS can be obtained. -whether an error occurs in the S/DS-P and/or the second clock signal CLK2.

In the case that one or more of the encoded image data DT-E does not comply with the preset image data encoding format, the receiving end 120 judges an error through the error detection module 124, and proceeds to step S14. Otherwise, go to step S9.

It should be noted that the condition for the error detection module 124 to transmit the error signal LK (such as the number of times the encoded image data DT-E does not conform to the encoding format of the image data) may vary according to actual needs, and the present invention is not limited to the above-mentioned embodiments.

In step S9, the transmitting end 110 transmits an end code EOL to the receiving end 120, indicating that the transmission of the data frame has ended (refer to time points t5-t6 in FIG. 6). Then, the flow returns to step S3, and the transmitting end 110 starts to transmit the horizontal masking code H-BK of the next data frame (for example, refer to time points t6-t7 in FIG. 6 ).

On the other hand, in step S10, if the control code CTRL transmitted by the transmitting end 110 conforms to the preset setting frame encoding format, it means that the transmitting end 110 is transmitting the data frame CN, and the transmitting end 110 transmits multiple settings Data CONF (refer to time point t8-t9 in FIG. 6).

In step S11 , when the receiving end 120 receives the aforementioned configuration data CONF, the receiving end 120 judges whether at least one of the configuration data CONF conforms to the preset configuration data encoding format through the error detection module 124 . The so-called “setting data coding format” here refers to the coding format predefined by the designer. After receiving the setting data with this format, the source driver 30 performs corresponding control (such as adjusting color depth bits, etc.). Under normal circumstances, each setting data CONF should conform to the setting data encoding format, so according to whether the setting data CONF received by the receiving end 120 conforms to the setting data encoding format, the display data stream DS-S/DS-P and /or whether an error occurs in the second clock signal CLK2.

In the case that one or more of the configuration data CONF does not comply with the preset configuration data encoding format, the receiving end 120 judges an error through the error detection module 124, and proceeds to step S14. Otherwise, go to step S9.

It should be noted that the condition for the error detection module 124 to transmit the error signal LK (such as the number of times the configuration data CONF does not conform to the configuration data encoding format) may vary according to actual needs, and the present invention is not limited to the above-mentioned embodiments.

On the other hand, in step S12, if the control code CTRL transmitted by the transmitting end 110 conforms to the preset masking code frame encoding format, it means that the transmitting end 110 is transmitting data frames L(1)-L( In one of N), the transmitting end 110 transmits a plurality of vertical masking codes V-BK (refer to time points t10-t11 in FIG. 6 ).

In step S13, when the receiving end 120 receives the aforementioned vertical masking code V-BK, the receiving end 120 judges whether at least one of these vertical masking codes V-BK conforms to the preset value through the error detection module 124. Masking code encoding format. Under normal circumstances, each vertical masking code V-BK should conform to the masking code format, so according to whether the vertical masking code V-BK received by the receiving end 120 conforms to the masking code format, it can be known that the display Whether an error occurs in the data stream DS-S/DS-P and/or the second clock signal CLK2.

In the case that one or more of the vertical masking codes V-BK do not conform to the preset masking code encoding format, the receiving end 120 judges an error through the error detection module 124, and proceeds to step S14. Otherwise, the process returns to step S3, so that the transmitting end 110 transmits the next frame of data FM.

It should be noted that the condition for the error detection module 124 to transmit the error signal LK (such as the number of times the vertical masking code V-BK does not conform to the coding format of the masking code) can vary according to actual needs, and the present invention is not limited to the above-mentioned embodiments.

Through the above operations, the error detection module 124 can be used to perform error detection on the display data stream DS-S/DS-P. An error occurs in the horizontal mask code H-BK, vertical mask code V-BK, control code CTRL, encoded image data DT-E or configuration data CONF detected in the display data stream DS-S/DS-P Or when it does not meet the preset encoding format, the error detection module 124 can notify the transmitting end 110 so that the transmitting end 110 can control the error elimination. Thereby, the stability of the display 10 can be improved.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection of the invention shall be defined by the scope of protection of the appended claims.

Claims (12)

1. A data transmission system applied to a display, characterized in that, comprising: a transmitting end, used to generate a first clock signal, and to provide a display data stream according to the first clock signal; and A receiving end, electrically connected to the transmitting end, for receiving the display data stream, wherein the receiving end includes: An error detection module is used to judge whether the display data stream received by the receiving end has an error according to a second clock signal, and to provide an error signal to the transmitting end according to the judgment result, so that the transmitting end can transparently transmitting a clock calibration signal through the display data stream; and A clock data recovery circuit is electrically connected to the error detection module, and the clock data recovery circuit is used for updating the second clock signal according to the clock calibration signal. 2. The data transmission system according to claim 1, wherein the error detection module is further used to determine whether at least one horizontal masking code or at least one vertical masking code in the display data stream conforms to a masking code. The blank code format is used to determine whether to provide the error signal to the transmitting end, and the transmitting end transmits the horizontal blanking code and the vertical blanking code corresponding to a horizontal blanking period and a vertical blanking period of the display. 3. The data transmission system according to claim 1 or 2, wherein the display data stream includes a plurality of data frames, at least one of the data frames includes a plurality of operation data, and the operation data Including a bit synchronization code and a control code, the bit synchronization code is a first order data in the operation data, and the control code is a second order order adjacent to the bit synchronization code in the operation data data, and the error detection module is also used to judge whether the receiving end receives the control code correctly, so as to decide whether to provide the error signal to the transmitting end. 4. The data transmission system according to claim 3, wherein the error detection module is further used to determine whether the second order data adjacent to the bit synchronization code in the operation data conforms to at least one control code The encoding format is used to determine whether the receiving end correctly receives the control code adjacent to the bit synchronization code in the display data stream. 5. The data transmission system according to claim 3, wherein the error detection module is also used to determine whether the control code conforms to an image frame encoding format, and is used to determine whether the control code conforms to the image frame encoding format In the case of the operation data, it is judged whether at least one piece of image data in the operation data conforms to an image data encoding format, so as to determine whether to provide the error signal to the transmitting end. 6. The data transmission system according to claim 3, wherein the error detection module is also used to judge whether the control code conforms to a set frame coding format, and is used to determine whether the control code conforms to the set frame coding format In the case of the operation data, it is judged whether at least one piece of setting data in the operating data conforms to a setting data encoding format, so as to determine whether to provide the error signal to the transmitting end. 7. An operating method applied to a display, wherein the display includes a transmitting end and a receiving end, characterized in that the operating method comprises: providing a display data stream according to a first clock signal through the transmitting end; receiving the display data stream through the receiving end, judging whether the display data stream has an error according to a second clock signal, and providing an error signal according to the judgment result; transmitting a clock calibration data through the display data stream according to the error signal through the transmitting end; and Through the receiving end, the second clock signal is updated according to the clock calibration data. 8. The operating method according to claim 7, wherein the step of judging whether the display data stream has an error, and providing the error signal according to the judging result comprises: judging whether at least one horizontal masking code or at least one vertical masking code in the display data stream conforms to a masking code encoding format, so as to determine whether to provide the error signal to the transmitting end, wherein the transmitting end corresponds to the display The horizontal blanking code and the vertical blanking code are transmitted respectively during a horizontal blanking period and a vertical blanking period. 9. The operation method according to claim 7 or 8, wherein the step of providing the display data stream comprises: providing the display data stream including a plurality of data frames, wherein at least one of the data frames includes a plurality of operation data, the operation data includes a bit synchronization code and a control code, the bit synchronization code is the A first order data among the operation data, and the control code is a second order data adjacent to the bit synchronization code among the operation data; And the step of judging whether the display data stream has an error, and providing the error signal according to the judging result includes: It is judged whether the control code is received correctly, so as to determine whether to provide the error signal to the transmitting end. 10. The operation method according to claim 9, wherein it is judged whether the receiving end correctly receives the control code adjacent to the bit synchronization code in the display data stream, so as to determine whether to provide the error signal to the transmission End steps include: judging whether the second sequential data adjacent to the bit synchronization code in the operation data conforms to at least one control code encoding format, so as to determine whether the receiving end correctly receives the display data stream adjacent to the bit synchronization code the control code. 11. The operating method according to claim 9, wherein the step of judging whether the control code is correctly received comprises: judging whether the control code conforms to an image frame encoding format; And the step of judging whether the display data stream has an error, and providing the error signal according to the judging result includes: When the control code conforms to the encoding format of the image frame, it is judged whether at least one image data in the operation data conforms to an encoding format of the image data, so as to determine whether to provide the error signal to the transmitting end. 12. The operating method according to claim 9, wherein the step of judging whether the control code is correctly received comprises: judging whether the control code conforms to a set frame coding format; And the step of judging whether the display data stream has an error, and providing the error signal according to the judging result includes: When the control code conforms to the encoding format of the setting frame, it is judged whether at least one setting data among the operating data conforms to a encoding format of the setting data, so as to determine whether to provide the error signal to the transmitting end.