CN104051419B - For the interconnection structure of stack device - Google Patents
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- CN104051419B CN104051419B CN201310463691.4A CN201310463691A CN104051419B CN 104051419 B CN104051419 B CN 104051419B CN 201310463691 A CN201310463691 A CN 201310463691A CN 104051419 B CN104051419 B CN 104051419B
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Abstract
The invention discloses a kind of stacked integrated circuit（IC）Device and method.The stacked IC device includes the first semiconductor element.First semiconductor element includes multiple first conductive components in the dielectric block in the first substrate, the first substrate and the first metal intermetallic dielectric layer being formed in above the first substrate.The stacked IC device also includes the second semiconductor element being bonded on the first semiconductor element.Second semiconductor element includes multiple second conductive components in the second substrate and the second metal intermetallic dielectric layer being formed in above the second substrate.The stacked IC device also includes the deep interconnection connector of conduction being connected between the first conductive component and the second conductive component.Conductive deep interconnection connector is isolated by dielectric block, the first metal intermetallic dielectric layer and the second metal intermetallic dielectric layer.The invention also discloses the interconnection structure for stack device.
Description
The Serial No. No.61/798 that this patent requirement on March 15th, 2013 submits to, the priority of 459 patent application,
Present patent application is herein incorporated by reference.
Technical field
The present invention relates to technical field of semiconductors, more particularly, to the interconnection structure for stack device.
Background technology
Semiconductor integrated circuit（IC）Industry has gone through rapid growth.In the course that IC is developed, functional density
（That is, the number of the interconnection devices of per unit chip area）Increased, and physical dimension（I.e., it is possible to be manufactured using manufacturing process
Minimal parts（Or circuit））Reduce.This size reduction technique is offered the advantage which raises production efficiency simultaneously
Reduce relevant cost.
As semiconductor technology further develops, stacked IC device occurs as effective optional mode, to enter one
Step reduces the physical size of semiconductor devices.In stacked IC device, active circuit（For example, logic circuit, memory are electric
Road, processor circuit etc.）Manufacture is on different semiconductor crystal wafers.Then, the semiconductor crystal wafer of two or more is arranged on
Forming stacked IC on mutual top.For example, two semiconductor crystal wafers can be bonded on one by suitable joining technique
Rise, be then assembled into single stacked IC device.A kind of advantage of stacked IC device can be achieved on high density.Although existing
Stacked IC device and the method for manufacture stacked IC device generally met the expected phase purpose of people, but people and also
Whole satisfactions can not in all respects be obtained.Expect to be improved in this field.
The content of the invention
In order to solve the problems of in the prior art, according to an aspect of the invention, there is provided a kind of device, bag
Include：
First semiconductor element, including：
First substrate；
Dielectric block in first substrate；With
Multiple first conductive components, are formed in the first metal intermetallic dielectric layer above first substrate；
Second semiconductor element, is bonded to first semiconductor element, wherein, second semiconductor element includes：
Second substrate；With
Multiple second conductive components, are formed in the second metal intermetallic dielectric layer above second substrate；And
Conductive deep interconnection connector, is connected between first conductive component and second conductive component and by described
Dielectric block, first metal intermetallic dielectric layer and second metal intermetallic dielectric layer isolation, the conductive deep interconnection connector include：
The top in the dielectric block and first metal intermetallic dielectric layer is formed in, the top has the first width；
With
The bottom in first metal intermetallic dielectric layer and second metal intermetallic dielectric layer is formed in, the bottom has
Less than the second width of first width.
In an alternative embodiment, first conductive component is used as during the bottom of the conductive deep interconnection connector is formed
Etch hard mask.
In an alternative embodiment, the top of the conductive deep interconnection connector passes through between the dielectric block and first metal
Dielectric layer is isolated.
In an alternative embodiment, the bottom of the conductive deep interconnection connector is isolated by second metal intermetallic dielectric layer.
In an alternative embodiment, the device also includes：It is formed in the groove in the first side of first conductive component
Area.
In an alternative embodiment, multiple conductive deep interconnection connectors are formed in single dielectric block.
In an alternative embodiment, single conductive deep interconnection connector is formed in the dielectric block.
According to another aspect of the present invention, a kind of stacked integrated circuit device is additionally provided, including：
First semiconductor element, with the first substrate, the dielectric block being arranged in first substrate and described first
The first conductive component above substrate；
Second semiconductor element, is bonded to first semiconductor element, and second semiconductor element includes the second lining
Bottom and the second conductive component above second substrate；And
The deep interconnection connector of conduction being connected between first conductive component and second conductive component, wherein, institute
Stating conductive deep interconnection connector includes：
Top with the first width, the part top is isolated by the dielectric block；With
Bottom with the second width.
In an alternative embodiment, first width on the top of the conductive deep interconnection connector is generally higher than the of the bottom
Two width.
In an alternative embodiment, the device also includes：It is formed in the groove in the first side of first conductive component
Area.
In an alternative embodiment, the device also includes：It is arranged between the first metal in first semiconductor element
Dielectric（IMD）Layer；And, it is arranged on the second inter-metal dielectric in second semiconductor element（IMD）Layer.
In an alternative embodiment, the top of the conductive deep interconnection connector is arranged on the dielectric block and an IMD
In layer, and the bottom of the conductive deep interconnection connector is arranged in first IMD layer and second IMD layer.
In an alternative embodiment, multiple conductive deep interconnection connectors are formed in single dielectric block.
In an alternative embodiment, single conductive deep interconnection connector is formed in the dielectric block.
According to another aspect of the invention, a kind of method is additionally provided, including：
The first semiconductor element is provided, first semiconductor element includes：
First substrate；
The first inter-metal dielectric above first substrate（IMD）Layer；With
The first conductive component in first IMD layer；
First semiconductor element is bonded to the second semiconductor element, wherein, second semiconductor element includes：
Second substrate；
The second inter-metal dielectric above second substrate（IMD）Layer；And
The second conductive component in second IMD layer；
Substrate trenches are formed in first substrate；
Fill the substrate trenches to be formed with the substantially flat surface concordant with first substrate with dielectric material
Dielectric block；
Pattern mask is formed above flat first substrate and the dielectric block；
The dielectric block, first IMD layer and part second IMD layer are etched with shape through the pattern mask
Into deep interconnection channel；And
The deep interconnection channel filled with conductive material connected with forming deep interconnection connector first conductive component and
Second conductive component.
In an alternative embodiment, the substantially flat surface of the dielectric block and first substrate is by chemically mechanical polishing
（CMP）Formed.
In an alternative embodiment, the deep interconnection channel has abundant by photoetching and relative to first conductive component
The selective etch technique of etching selectivity formed.
In an alternative embodiment, first conductive component is used as etch hard mask.
In an alternative embodiment, the deep interconnection connector has upper and lower part.
In an alternative embodiment, the width on the top of the deep interconnection connector is generally higher than the width of bottom.
Brief description of the drawings
When reading in conjunction with the accompanying drawings, the present invention may be better understood according to the following detailed description.It should be emphasized that
, the standard practices in industry, various parts are not drawn on scale and are intended solely for illustrative purposes.In fact,
In order to clearly discuss, the size of various parts can be arbitrarily increased or reduced.
Fig. 1 is the stacked integrated circuit according to each side of the present invention（IC）The sectional view of device.
Fig. 2 is the flow chart of the exemplary method of the manufacture stacked IC device according to each side of the present invention.
Fig. 3 A to Fig. 3 B and Fig. 4 to Fig. 7 are the example stacked IC devices in the fabrication stage of the method construct according to Fig. 2
The sectional view of part.
Specific embodiment
Following discloses text provides various different embodiments or example, for realizing different characteristic of the invention.Under
Face describes the particular instance of component and arrangement to simplify the present invention.Certainly, these are only examples and are not intended to the limitation present invention.
For example, in the following description, forming first component in second component above or over can include first component and second
The embodiment of part directly contact shaping, and other portions can also be formed between first component and second component including other
Part is so that the embodiment that is not directly contacted with of first component and second component.In addition, the present invention can be weighed in multiple examples
Multiple reference number and/or character.It is this to be recycled and reused for simplifying and clear, and itself does not specify described multiple embodiments
And/or the relation between configuration.
Additionally, herein can be used such as " ... under ", " ... below ", " below ", " ... above " and
" above " etc. spatial relationship term, to describe an element as illustrated in the drawing or part and another element or part
Relation.In addition to the orientation shown in figure, spatial relationship term will include device different azimuth in use or operation.Example
Such as, if device shown in flipchart, be described as be in other elements or part " below " or " under " element will be by
It is positioned in " above " of other elements or part.Therefore, exemplary term " ... below " be included in above and below
Orientation.Device can be positioned otherwise（It is rotated by 90 ° or in other orientation）, and by spatial relationship as used herein
Descriptor is correspondingly explained.
Fig. 1 is the sectional view of the stacked IC device before joint technology according to each side of the present invention.In order to clear
For the sake of, Fig. 1 is simplified, so that the content of the invention of the invention is better described.The figure illustrate the first semiconductor crystal wafer
100, it is stacked on the top of the second semiconductor crystal wafer 200.For example, the first semiconductor crystal wafer 100 is imageing sensor, such as back-illuminated
Formula imageing sensor（BIS）, complementary metal oxide semiconductors (CMOS)（CMOS）Imageing sensor（CIS）, charge-coupled image sensor
（CCD）, CMOS active pixel sensor（APS）Or passive pixel sensor.Imageing sensor can be by complementation known in the art
Metal-oxide semiconductor (MOS)（CMOS）Technology is manufactured.For example, p-type photosensitive region and N-type photosensitive region are formed in image biography
To form PN junction, the PN junction is used as photodiode for the substrate top of sensor wafer.Imageing sensor wafer 100 may include crystal
Pipe is producing the signal relevant with the intensity of the light struck on photosensitive region or brightness.Continue this example, the second semiconductor
Wafer 200 is application specific integrated circuit（ASIC）Wafer.
As shown in figure 1, the first semiconductor crystal wafer 100（Shown with inverted orientation）Including the first substrate 102 and first
One or more first inter-metal dielectrics that substrate top is formed（IMD）Layer 104.In addition, multiple first conductive components（For example,
Conductive component 106 and 108）In formation IMD layer 104.
First substrate 102 includes elemental semiconductor, such as silicon or germanium；And/or compound semiconductor, such as SiGe, carbonization
Silicon, GaAs, indium arsenide, gallium nitride and indium phosphide.Other examples backing material includes alloy semiconductor, for example, carbonization
SiGe, gallium arsenide phosphide and InGaP.First substrate 102 may also include non-semiconducting material, for example, soda-lime glass, melting
Quartz, vitreosil, calcirm-fluoride（CaF2）And/or other suitable materials.In certain embodiments, the first substrate 102 has
Its internal one layer or multilayer is limited to, for example, epitaxial layer.For example, in one suchembodiment, the first substrate 102
Including the epitaxial layer above covering bulk semiconductor.Other laminate substrates include semiconductor-on-insulator（SOI）Substrate.At one
In this SOI substrate, the first substrate 102 includes isolating by such as note oxygen（SIMOX）What technique was formed buries oxygen (BOX) layer.
In various embodiments, the first substrate 102 can be in the form of planar substrate, fin-shaped substrates, nano wire and/or art technology
Other forms known to personnel.
First substrate 102 may include one or more doped region.In the embodiments described, the first substrate 102 is mixed
It is miscellaneous to have P-type dopant.Suitable P-type dopant includes boron, gallium, indium, other suitable P-type dopants and/or combinations thereof.
First substrate 102 may also include doped with the such as N type dopant of phosphorus, arsenic and other suitable N type dopants and/or they
Combination one or more area.In plurality of step and technology, the technique reality of such as ion implanting or diffusion can be used
Apply doping.
In various embodiments, the first substrate 102 can use planar substrate, fin-shaped substrates, nano wire and/or this area skill
Other forms known to art personnel.
First semiconductor crystal wafer 100 may include various passive and active microelectronic component.These parts may include main portion
Part（For example, image sensor element）And peripheral circuit element（For example, one or more field-effect transistor）.Other examples
Including P-channel field-effect transistor (PEFT) transistor（PFET）, N-channel field-effect transistor（NFET）, metal oxide semiconductor field-effect it is brilliant
Body pipe (MOSFET), CMOS transistor, FinFET, high voltage transistor, high frequency transistor, bipolar junction transistor, resistor,
Capacitor, diode, electric fuse and other suitable devices and/or combinations thereof.In certain embodiments, peripheral circuit
Element is operable interacting with main element or control main element.However, in further embodiments, except configuring in phase
Outside on substrate 102, peripheral circuit element does not have functional relationship with main element.
First IMD layer 104 may include silica, silicon nitride, silicon oxynitride, polymer or other suitable materials.The
One IMD layer 104 can be by chemical vapor deposition（CVD）, high density ionomer cvd（HDP-CVD）, physical vapour deposition (PVD)（PVD）、
Ald（ALD）And/or other suitable depositing operations are formed.First IMD layer 104 may include by different dielectric material
Multiple layers of manufacture.
First conductive component 106 and 108 can be by any suitable formation process（For example, with etching, inlay, double edges
The photoetching of embedding grade）Manufacture, and can be used the suitable conductive material such as copper, aluminium, aluminium alloy, copper alloy to be formed.
Other parts can be coupled in the first semiconductor crystal wafer 100, and for other realities of the first semiconductor crystal wafer 100
Example is applied, some above-mentioned structures can be replaced or remove.
Compared with the first semiconductor crystal wafer 100, the second semiconductor crystal wafer 200 may include identical or different element.Example
Such as, the second semiconductor crystal wafer 200 includes the second substrate 202, the second IMD layer 204 and multiple second conductive components 206 and 208.
Fig. 2 is the flow chart of the method 300 for forming stacked IC device according to each side of the present invention.Fig. 3 A, figure
3B and Fig. 4 to Fig. 7 is the sectional view by the exemplary stack Formulas I C devices 400 handled by the method according to Fig. 2.Should manage
Solution, can before the process per se, between and additional step is provided afterwards, it is described and for the other embodiments of the method
Some steps can be replaced or remove.
Reference picture 2 and Fig. 3 A, method 300 start from step 302, by the way that such as directly the suitable joining technique of engagement will
First semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 are combined together.In one embodiment, the first semiconductor crystal wafer
100 and second are respectively formed with multiple bond pads in semiconductor crystal wafer 200.In this embodiment, positioned at the second semiconductor die
The bond pad of circle 200 is aligned face-to-face with the corresponding bond pad positioned at the first semiconductor crystal wafer 100.According to one
A little embodiments, in direct joint technology, connection between the first semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 can be with
Engaged with metal by metal（For example, copper is engaged with copper）, dielectric engages with dielectric（For example, oxide connects with oxide
Close）, metal engages with dielectric（For example, copper is engaged with oxide）Or combinations thereof is realized.In certain embodiments,
First semiconductor crystal wafer 100 and the second semiconductor crystal wafer 200 are connected to each other by suitable three-dimensional structure.It is also possible to use adhesion
Layer.
Furthermore it is possible to carry out thinning technique with from any one or two back side thinnings of substrate.Thinning technique may include
Mechanical milling tech and/or chemical thinning technique.For example, during mechanical milling tech, substantial amounts of backing material can be from
One substrate 102 is removed.Afterwards, chemical thinning technique can apply based etch chemistry with further thin to the back side of the first substrate 102
Change the first substrate 102.
With continued reference to Fig. 2 and Fig. 3 A, method 300 is carried out to step 304, removes the first substrate of part 102 to form substrate
Groove 120.In one embodiment, the back side in the first substrate 102 is formed with bottom anti-reflective painting（BARC）Layer 110.
BARC layer 110 may include nitride material, organic material, oxide material etc..BARC layer 110 can use such as CVD, PVD
Deng suitable technology formed.
Substrate trenches 120 can be formed by photoetching and etch process.As example, pass through in the top of the first substrate 102
Spin coating, exposed and developed technique form the photoresist layer of patterning.Then the photoresist by patterning enters to the first substrate 102
Row etching.The etch process may include dry method etch technology, wet etching process and/or combinations thereof.Etch process may be used also
Including selective wet etching or selective dry etching.The wet etch solution of example includes tetramethyl ammonium hydroxide
（TMAH）、HF/HNO3/CH3COOH solution or other suitable solution.The dry method etch technology of example may include to use chloro
The bias plasma etch process of chemical agent.Other examples dry etchant gas includes CF4, NF3, SF6 and He.At certain
In embodiment, relative to the first IMD layer 104, the selective etch for carrying out has sufficient etching selectivity.
As shown in Figure 3A, in one embodiment, the size of the substrate trenches 120 of formation causes it including more than one
Deep interconnection connector.This will be discussed in more detail below.As shown in Figure 3 B, in another embodiment, the substrate trenches 120 of formation
Size cause that it includes single following deep interconnection connector.For illustration purposes, disclosure below is by for the embodiment of Fig. 3 A.
It should be appreciated that identical step can be implemented in the embodiment of Fig. 3 B.
Reference picture 2 and Fig. 4, method 300 are carried out to step 306, and dielectric layer 130 is filled with first in substrate trenches 120
Dielectric block 135 is formed in substrate 102.Dielectric layer 130 may include such as silica, silicon nitride, silicon oxynitride, TEOS oxidations
Thing, phosphosilicate glass（PEG）, boron phosphorus silicate glass（BPSG）, fluorosilicate glass（FSG）, carbon doping silica, non-
Brilliant fluorocarbons, Parylene, polyimides, low k dielectric, other suitable materials and/or combinations thereof.For sinking
The common methods of product dielectric layer 130 include thermal oxidation, CVD, high-density plasma CVD（HDP-CVD）, PVD, ALD, rotation
Apply deposition and/or other suitable depositing operations.
In the present embodiment, using such as chemically-mechanicapolish polishing（CMP）Technique make dielectric block 135 planarize come and first
Substrate 102（BARC layer 110）Either flush, so as to obtain the surface with the substantially flat of photoetching process later.
Reference picture 2 and Fig. 5, method 300 are carried out to step 308, square on the first substrate 102 including dielectric block 135
Into with deep interconnection channel（DIT）The pattern mask 140 of opening 145.Pattern mask 140 can be photoresist layer or hard
Mask.Pattern mask 140 is formed in the first substrate 102 and dielectric block 135 by suitable deposition, photoetching and etching technique
On top surface.In the present embodiment, pattern mask 140 is formed in the substantially flat manufactured by the first substrate 102 and dielectric block 135
On surface, its process window that can improve photoetching process.DIT openings 145 be arranged on corresponding in the second semiconductor crystal wafer 200 leading
Electric part 206 and 208 is aligned.
Reference picture 2 and Fig. 6, method 300 are carried out to step 310, are formed from the first semiconductor crystal wafer 100 and are extended to the second half
The deep interconnection channel of semiconductor wafer 200（DIT）150.DIT150 be formed as having respectively top 156,158 and bottom 256,
258.Through the top of 145, DIT150 of DIT openings（156 and 158）Formed by etching the IMD layer 104 of dielectric block 135 and first,
And the bottom of DIT150（256 and 258）By two stackings of the first IMD layer 104 of etching and the second IMD layer 204 and connection
The composition surface of wafer and formed.Conductive component 106,108,206 and 208 is at least partially exposed through in DIT150.
Suitable etch process includes dry etching, anisotropic wet etch or any other suitable etching.
In the present embodiment, the selective etch technique with sufficient etching selectivity is applied with relative to conductive component 106,108.Cause
This, for the etch process of IMD layer 104 and 204, conductive component 106 and 108 can play hard mask layer（A kind of " built-in " hard mask）
Effect.In one embodiment, selective etch technique can be used with fast-etching IMD layer 104 and 204, while only etching
The fraction of conductive component 106 and 108.The expose portion of hard mask layer（For example, conductive component 106 and 108）Partly lost
Quarter is fallen, so as to form the groove of such as groove 157 and groove 159 etc.The depth of groove 157 and groove 159 can be according to difference
Application and design need and change.
Reference picture 2 and Fig. 7, method 300 are carried out to step 312, and conductive material is filled in DIT150 to form deep interconnection
Connector（DIP）160.DIP160 includes high conductivity and low resistive metal, metal element, transition metal etc..For example,
DIP160 includes copper, copper alloy（For example, copper magnesium alloy（CuMn）, albronze（CuAl）Or cupro silicon（CuSi））, so
And, also it is alternatively used other materials（Such as, tungsten, aluminium）.DIP160 can be by any suitable method known in the art（Example
Such as, PVD, sputtering CVD, plating etc.）Formed.In one embodiment, DIP160 is further blocked layer encirclement to prevent diffusion
And/or material bonding is provided.Barrier layer may include titanium nitride（TiN）, tantalum nitride（TaN）, tungsten nitride（WN）, titanium silicon nitride
（TiSiN）Or tantalum nitride silicon（TaSiN）.DIP160 is formed as having the first width w1Top and with the second width w2's
Bottom.In the present embodiment, the first width w1Generally higher than the second width w2.The IMD layer 104 of dielectric block 135 and first is to DIP160
Top electric isolution is provided, and the first IMD layer 104 and the second IMD layer 204 provide electric isolution to the bottom of DIP160.In addition, such as
Fruit needs desired pattern, can apply chemically mechanical polishing（CMP）To remove conductive material so as to obtain flat results.
It should be noted that although Fig. 7 shows two semiconductor crystal wafers being stacked, those of ordinary skill in the art should
Understand, the stacked semiconductor device shown in Fig. 7 is only example.There may be plurality of optional mode, deformation and change.For example,
The stacked semiconductor device can accommodate more than two wafer.
More than being based on, the invention provides stacked IC device, which employs dielectric block and deep interconnection channel structure and
Formed.Dielectric block provides the surface of substantially flat and it indicates process window and changes for the photoetching process of deep interconnection channel
Enter.Deep interconnection channel forms to use " built-in " hard mask to obtain by the selective etch technique with abundant etching selectivity
Obtain technological flexibility and control.
The invention provides stacked integrated circuit（IC）The various different embodiments of device.Stacked IC device includes the
Semiconductor element.First semiconductor element is including the dielectric block in the first substrate, the first substrate and is formed in the first substrate
Multiple first conductive components in the metal intermetallic dielectric layer of top first.Stacked IC device also includes being bonded on the first semiconductor element
The second semiconductor element on part.Second semiconductor element includes the second substrate and is formed in the second metal of the second substrate top
Between multiple second conductive components in dielectric layer.Stacked IC device also includes being connected to the first conductive component and the second conductive part
Deep interconnection connector between part.Conductive deep interconnection connector passes through dielectric block, the first metal intermetallic dielectric layer and the second inter-metal dielectric
Layer isolation.Conductive deep interconnection connector includes being formed in the top above the first side of hard mask layer.Top has the first width.Lead
Electric deep interconnection connector also has the bottom being formed in above the second side of hard mask layer.Bottom has approximately less than the first width
Second width.
In another embodiment, stacked integrated circuit（IC）Device includes the first semiconductor element, and it has the first lining
Bottom, the dielectric block being arranged in the first substrate and the first conductive component.Stacked IC device also has and is bonded on the first half and leads
The second semiconductor element on volume elements part.Second semiconductor element includes the second conduction above the second substrate and the second substrate
Part.Stacked integrated circuit（IC）Device also includes that the conduction being connected between the first conductive component and the second conductive component is deep
Interconnection connector.Conductive deep interconnection connector includes the bottom of the top isolated by dielectric block and width much smaller than upper width.
In another embodiment, it is a kind of for manufacturing stacked integrated circuit（IC）The method of device includes：There is provided first
Semiconductor element.First semiconductor element includes the first inter-metal dielectric above the first substrate, the first substrate（IMD）Layer and
Conductive component in first IMD layer.The method also includes being bonded to the first semiconductor element on the second semiconductor element.Second
Semiconductor element includes the second inter-metal dielectric above the second substrate, the second substrate（IMD）In layer and the second IMD layer the
Two conductive components.The method forms substrate trenches in being additionally included in the first substrate, fills substrate trenches to be formed with dielectric material
Dielectric block with the substantially flat surface concordant with the first substrate, pattern is formed above the first flat substrate and dielectric block
Change mask, through pattern mask etching dielectric block, the first IMD layer and the IMD layer of part second with formed deep interconnection channel and
Deep interconnection channel is filled with conductive material to form deep interconnection connector to connect the first and second conductive components.
Foregoing has outlined the feature of some embodiments so that those of ordinary skill in the art may be better understood the present invention
Each side.It will be understood by those skilled in the art that they easily the present invention can be designed as basis or
Changing other is used to reach with embodiment identical purpose described herein and/or realize the technique and structure of same advantage.This
Field those of ordinary skill should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and not
In the case of the spirit and scope of the present invention, various changes, replacement can be carried out and changed.
Claims (20)
1. a kind of stacked integrated circuit device, including：
First semiconductor element, including：
First substrate；
Dielectric block in first substrate；With
Multiple first conductive components, are formed in the first metal intermetallic dielectric layer above first substrate；
Second semiconductor element, is bonded to first semiconductor element, wherein, second semiconductor element includes：
Second substrate；With
Multiple second conductive components, are formed in the second metal intermetallic dielectric layer above second substrate；And
Conductive deep interconnection connector, is connected between first conductive component and second conductive component and by the dielectric
Block, first metal intermetallic dielectric layer and second metal intermetallic dielectric layer isolation, the conductive deep interconnection connector include：
The top in the dielectric block and first metal intermetallic dielectric layer is formed in, the top has the first width；With
It is formed in the bottom in first metal intermetallic dielectric layer and second metal intermetallic dielectric layer, the bottom has and is less than
Second width of first width, wherein, the part through first conductive component of the conductive deep interconnection connector is wrapped
Include the section with first width and the section with second width.
2. device according to claim 1, wherein, first conductive component is forming the conductive deep interconnection connector
It is used as etch hard mask during bottom.
3. device according to claim 1, wherein, the top of the conductive deep interconnection connector passes through the dielectric block and institute
State the isolation of the first metal intermetallic dielectric layer.
4. device according to claim 1, wherein, the bottom of the conductive deep interconnection connector is by between second metal
Dielectric layer is isolated.
5. device according to claim 1, also includes：
It is formed in the groove area in the first side of first conductive component.
6. device according to claim 1, wherein, multiple conductive deep interconnection connectors are formed in single dielectric block.
7. device according to claim 1, wherein, single conductive deep interconnection connector is formed in the dielectric block.
8. a kind of stacked integrated circuit device, including：
First semiconductor element, with the first substrate, the dielectric block being arranged in first substrate and first substrate
First conductive component of top；
Second semiconductor element, is bonded to first semiconductor element, second semiconductor element include the second substrate and
The second conductive component above second substrate；And
The deep interconnection connector of conduction being connected between first conductive component and second conductive component, wherein, it is described to lead
Electric deep interconnection connector includes：
Top with the first width, the part top is isolated by the dielectric block；With
Bottom with the second width,
Wherein, the part through first conductive component of the conductive deep interconnection connector is included with first width
Section and the section with second width.
9. device according to claim 8, wherein, first width on the top of the conductive deep interconnection connector is more than described
Second width of bottom.
10. device according to claim 8, also includes：
It is formed in the groove area in the first side of first conductive component.
11. devices according to claim 8, also include：
It is arranged on the first inter-metal dielectric (IMD) layer in first semiconductor element；And
It is arranged on the second inter-metal dielectric (IMD) layer in second semiconductor element.
12. devices according to claim 11, wherein, the top of the conductive deep interconnection connector is arranged on the dielectric block
In first metal intermetallic dielectric layer, and the bottom of the conductive deep interconnection connector is arranged on first inter-metal dielectric
In layer and second metal intermetallic dielectric layer.
13. devices according to claim 8, wherein, multiple conductive deep interconnection connectors are formed in single dielectric block.
14. devices according to claim 8, wherein, single conductive deep interconnection connector is formed in the dielectric block.
A kind of 15. methods for manufacturing stacked integrated circuit device, including：
The first semiconductor element is provided, first semiconductor element includes：
First substrate；
The first inter-metal dielectric (IMD) layer above first substrate；With
The first conductive component in first metal intermetallic dielectric layer；
First semiconductor element is bonded to the second semiconductor element, wherein, second semiconductor element includes：
Second substrate；
The second inter-metal dielectric (IMD) layer above second substrate；And
The second conductive component in second metal intermetallic dielectric layer；
Substrate trenches are formed in first substrate；
Fill the substrate trenches to form the dielectric block with the flat surfaces concordant with first substrate with dielectric material；
Pattern mask is formed above flat first substrate and the dielectric block；
Etched between the dielectric block, first metal intermetallic dielectric layer and part second metal through the pattern mask
Dielectric layer is forming deep interconnection channel；And
The deep interconnection channel filled with conductive material connected to form deep interconnection connector first conductive component and described
Second conductive component.
The flat surfaces of 16. methods according to claim 15, the dielectric block and first substrate pass through chemical machine
Tool polishing (CMP) is formed.
17. methods according to claim 15, wherein, the deep interconnection channel is led by photoetching and relative to described first
The selective etch technique that electric part has sufficient etching selectivity is formed.
18. methods according to claim 17, wherein, first conductive component is used as etch hard mask.
19. methods according to claim 15, wherein, the deep interconnection connector has upper and lower part.
20. methods according to claim 19, wherein, the width of the width more than bottom on the top of the deep interconnection connector
Degree.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361798459P | 2013-03-15 | 2013-03-15 | |
| US61/798,459 | 2013-03-15 | ||
| US13/937,055 | 2013-07-08 | ||
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