CN104036826A - Method for selecting error correction circuit in memory - Google Patents
Method for selecting error correction circuit in memory Download PDFInfo
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- CN104036826A CN104036826A CN201410261432.8A CN201410261432A CN104036826A CN 104036826 A CN104036826 A CN 104036826A CN 201410261432 A CN201410261432 A CN 201410261432A CN 104036826 A CN104036826 A CN 104036826A
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Abstract
The invention provides a method for selecting an error correction circuit in a memory. ECC circuits with different performances are used for correcting data contents with different importance in the memory, so that the ECC circuits with the relatively high performances are used for correcting the data contents with the relatively high importance, and the ECC circuits with the relatively low performances are used for correcting the data contents with the relatively low importance, so as to avoid the power consumption waste caused by application of the same ECC circuits with the strong performances, and meanwhile, the logics of the ECC circuits, truly used at the any moment, are effectively reduced to reduce the soft error probability of the ECC circuit.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to the selecting method of error correction circuit in a kind of storer.
Background technology
Owing to existing a lot of high energy particles in environment, and these high energy particles can make circuit produce some soft errors, thereby the performance of the performance of circuit especially storer is had to image to a certain degree, for the electronic product as PC, can be by restarting or additive method solves this soft error, but for server rank, will bring very large loss if go wrong.For example, comprise multiple memorizers at network processing unit, common are static RAM (Static Random Access Memory, be called for short: SRAM), dynamic RAM (Dynamic Random Access Memory, be called for short: DRAM), three-state content addressing register (Ternary Content Addressable Memory, be called for short: buffer memory (Cache) TCAM) and on sheet, in the time there is mistake in these storeies, can cause very large impact to user, such as the webserver is in the time distributing internet protocol address (Internet Protocol Address) to user, because mistake appears in storer, may cause the internet protocol address distributing incorrect, thereby user is impacted.
Therefore, in order to address this problem, people have proposed some solutions, and one of them solves by error correcting (Error Correcting Code) circuit exactly.Error correcting (ECC) circuit can be allowed mistake, and can be by error correction, makes system be able to correct operation, can not interrupt because of mistake.Conventionally realize by add several PARITY in data.
In current server, all have ECC circuit, almost each memory chip just has ECC circuit corresponding with it.The content of memory stores comprise important content with relative be not so important content.Data content composition while having illustrated network peak period in Fig. 1, as can be seen from the figure 58.6% is entertainment content, 12.7% is web page browsing content, 12% is file-sharing content, 4% is service platform content, 3% is Content of Communication, and 9.7% is that other are as important contents such as internet protocol addresses.In these contents, internet protocol address is most important, can bring very large impact if there is mistake, and communicate by letter, the importance of service platform, file-sharing, web page browsing, entertainment content reduces successively, even if even occur in entertainment content that a small amount of mistake can not bring too much influence yet.Therefore; in the data content of network peak period, major part is unessential data content; it is important only having little data content; the ECC circuit that namely performance is very strong in the most of the time is all at the unessential data content of protection; this had both wasted power consumption, had also increased the area of ECC logical circuit and the probability of self soft error of causing greatly due to ECC area simultaneously.
Summary of the invention
In view of the above problems, the invention provides the selecting method of error correction circuit in a kind of storer.
The technical scheme that technical solution problem of the present invention adopts is:
A selecting method for error correction circuit in storer, wherein, comprising:
Step S1 a: storer that comprises the error correction circuit that multiple performances are different is provided;
Step S2: be divided into successively several grades according to the height of importance by storing content in described storer;
Step S3: the mode with the higher content of the higher described error correction circuit protection importance of performance is matched to described error correction circuit and described grade.
The selecting method of error correction circuit in described storer, wherein, the quantity of described error correction circuit is with to store the grade quantity that content is divided in described storer identical, and each described error correction circuit only matches with a grade.
The selecting method of error correction circuit in described storer, wherein, the quantity of described error correction circuit is to store the grade quantity that content is divided in described storer different, and each described error correction circuit mates with multiple grades.
The selecting method of error correction circuit in described storer, wherein, step S3 also comprises:
Step S31: described storer is powered on, and multiple described error correction circuit does not all enable;
Step S32: described storage content is conducted interviews, enable corresponding error correction circuit according to the corresponding grade of this content;
Step S33: after described storage access to content is completed, corresponding error correction circuit cuts out or lower electricity.
The selecting method of error correction circuit in described storer, wherein, the area of the logical circuit in the higher described error correction circuit of performance is larger.
The selecting method of error correction circuit in described storer, wherein, each described error correction circuit detects that wrong figure place is more than or equal to the figure place that it is corrected a mistake.
The selecting method of error correction circuit in described storer, wherein, the power consumption of the described error correction circuit that performance is higher is larger.
The selecting method of error correction circuit in described storer, wherein, when size one timing of described storage content, the number of errors that the described error correction circuit that performance is higher can detect and correct is more.
Technique scheme tool has the following advantages or beneficial effect:
The present invention carries out error correction by the ECC circuit that adopts different performance to the data content of different importance in storer, adopt the higher ECC circuit of performance to carry out error correction to the higher data content of importance thereby realized, and adopt the ECC circuit that performance is lower to carry out the possible of error correction to the lower data content of importance, and then avoid the power wastage because adopting same performance very strong ECC circuit to bring, also make the logical validity of the ECC circuit that arbitrary moment really utilized reduce simultaneously, produce the probability of soft error to reduce ECC circuit self.
Brief description of the drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.But appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 is the schematic diagram of data content composition in the storer of network peak period;
Fig. 2 is the structural representation of data content grade and the pairing of ECC circuit in the storer of first embodiment of the invention;
Fig. 3 is the data content grade of storer in prior art and the structural representation of ECC circuit pairing;
Fig. 4 is that the inventive method applies to the device workflow schematic diagram in a storer;
Fig. 5 is the device architecture schematic diagram of the storer in Fig. 4.
Embodiment
The present invention proposes the selecting method of error correction circuit in a kind of storer, mainly be divided into some parts by the data content in storer, adopt different error correction circuits to carry out error correction to different parts, with the power consumption of optimize storage, and suitably reduce in storer the effectively size of error correction circuit.
The inventive method mainly comprises: step S1: a storer that comprises the error correction circuit that multiple performances are different is provided; Step S2: be divided into successively several grades according to the height of importance by storing content in this storer; Step S3: the mode with the higher content of the higher error correction circuit protection importance of performance is matched to all error correction circuits and grade.
Below in conjunction with the drawings and specific embodiments, the selecting method of error correction circuit in a kind of storer proposed by the invention is elaborated.
In the present embodiment, the inventive method realizes by following steps, first, provides a storer that includes the error correction circuit that multiple performances are different.
Then, storage content in this storer is divided into several grades successively according to the height of importance, in the present embodiment, storage content is divided into S grade (Level), S natural number, be respectively grade 1 (Level_1), grade 2 (Level_2), grade 3 (Level_3), grade S (Level_S), the importance of the content of wherein preserving reduces successively, be that grade 1 (Level_1) represent content is most important, can make a big impact if there is mistake, such as internet protocol address, therefore need to protect with the strongest ECC circuit of performance, and grade S (Level_S) represent content is least important, occur that the wrong impact causing is little, these contents are the entertainment contents such as picture film and music, therefore can adopt the most weak ECC circuit of performance to protect, even do not protect with ECC circuit.
Visible; the data content of different importance does not need all to adopt high performance ECC circuit to protect; therefore; mode with the higher content of the higher ECC circuit protection importance of performance is matched to ECC circuit and grade in storer, thereby makes each grade can both adopt the ECC circuit of respective performances to protect.In one embodiment of the invention, the quantity of ECC circuit is with to store the grade quantity that content is divided in storer identical, and each ECC circuit only matches with a grade.For example: grade 1 (Level_1) adopts ECC_1 circuit to protect, it can detect the mistake of M_1 position, can correct N_1 bit-errors (wherein M_1>=N_1); Grade 2 (Level_2) adopts ECC_2 circuit to protect, and it can detect M_2 bit-errors, can correct N_2 bit-errors (wherein M_2>=N_2); Grade 3 (Level_3) adopts ECC_3 circuit to protect, and it can detect M_3 bit-errors, can correct N_3 bit-errors (wherein M_3>=N_3); Grade S (Level_S) adopts ECC_S circuit to protect; it can detect M_S bit-errors; can correct N_S bit-errors (wherein M_S>=N_S); wherein; the performance of corresponding ECC circuit be ECC_1>=ECC_2>=ECC_3>=...>=ECC_S; for the raw data (as page data) of the formed objects needing protection; M_1>=M_2>=M_3>=...>=M_S>=0; N_1>=N_2>=N_3>=...>=N_S>=0, in corresponding ECC circuit, logical circuit area relationship is A
m_1>=A
m_2>=A
m_3>=...>=A
m_S>=0.
At any time, in the time that storer is read access, only have an ECC circuit to enable, other ECC circuit is closed or power-off completely.Fig. 2 is the structural representation of storer in above-described embodiment; Fig. 3 is the structural representation of storer in prior art.As shown in Figure 3, protect because storer of the prior art all adopts the ECC circuit of identical performance, and ECC performance is decided by the most important data that need protection, so all adopt ECC_1; And in the system of selection of ECC circuit in the above embodiment of the present invention, in the time that storer is read access, also only having an ECC circuit to open enables, but the power consumption that its work consumes can be less than or equal to ECC_1, himself logic area is also less than or equal to ECC_1 accordingly, error correction speed is more than or equal to ECC_1, and the probability that soft error occurs is also less than or equal to ECC_1.In other words, within a period of time (in the time that storer is read by connected reference), the equivalent power consumption that method of the present invention is produced by ECC circuit is less than the power consumption of ECC in legacy memory, equivalence ECC circuit area is less than the ECC circuit area in legacy memory, equivalence error correction speed is greater than the ECC speed in legacy memory, and the probability that soft error occurs in equivalence is also less than the ECC logical circuit in legacy memory.
But, more detailed by data content ranking score, the ECC circuit needing is just more, can cause the overall increase of chip area, thereby increase the cost of single memory chip.As a distortion of above-described embodiment, the quantity of ECC circuit is set to differently from storing grade quantity that content is divided in storer, and each ECC circuit mates with multiple grades.Concrete embodiment is first the content in storer to be divided into S grade (Level), be respectively grade 1 (Level_1), grade 2 (Level_2), grade 3 (Level_3) ..., grade S (Level_S), the importance of the content of wherein preserving respectively reduces successively, we can be divided into a class to grade 2 (Level_2) by grade 1 (Level_1), this class is protected with ECC_1, he can detect M_1 bit-errors, can correct N_1 bit-errors (wherein M_1 >=N_1); From grade 3 (Level_3) to waiting K (Level_K) to be divided into a class, this class is protected with ECC_2, and it can detect M_2 bit-errors, can correct N_2 bit-errors (M_2 >=N_2); The remaining class that is divided into, this class is protected with ECC_3, and he can detect M_3 bit-errors, can correct N_3 bit-errors (wherein M_3 >=N_3).By the above embodiments, the quantity of ECC circuit can be reduced to 3 from S is individual, thereby reduce the total area of memory chip.
As the concrete steps of above-mentioned the first embodiment, as shown in Figure 4, step 1: after system powers on, ECC_1 does not all enable to ECC_S; Step 2: in the time that system needs visit data, according to the important level of data content, enable corresponding ECC circuit, for example, when the data that will access are positioned at grade S (Level_S), enable ECC_S; Step 3: when the complete data of system access, make corresponding ECC circuit invalid (DISABLE or lower electricity), for example, when having accessed after the data of grade S (Level_S), make electricity under ECC_S.
As a specific embodiment, above-mentioned method is applied as follows in a concrete storage environment, suppose to have in a storer content of following three kinds of important level, be respectively Internet protocol address (Internet Protocol Address), document (Documents), music movie (Music and Movie), the importance rate of these three kinds of contents reduces successively, so adopt the ECC circuit of performance maximum to protect Internet protocol address, this ECC circuit can detect 8 bit-errors and correct 5 in every 256 bit data; Adopt second largest ECC circuit of performance to protect document (Documents), this ECC circuit can detect 4 bit-errors and correct 2 in every 256 bit data; Adopt the minimum ECC circuit (or without ECC circuit) of performance to protect music movie, this ECC circuit can detect 1 bit-errors and correct 1 in every 256 bit data, as shown in Figure 5.By the method, not only ensure the correctness of most important Internet protocol address, also reduce the power consumption of ECC circuit while reading music movie, also reduce because of the excessive probability that produces soft error of equivalent ECC circuit area simultaneously.
In sum; by the content in storer is divided into different grades according to importance; and adopt the ECC circuit of different performance to protect; this method is for the ECC circuit that adopts same performance is protected all the elements method; equivalence has reduced area and the power of ECC circuit; equivalence increased the speed of ECC circuit error correction, and also equivalence has reduced the probability that soft error appears in ECC circuit.
For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. a selecting method for error correction circuit in storer, is characterized in that, comprising:
Step S1 a: storer that comprises the error correction circuit that multiple performances are different is provided;
Step S2: be divided into successively several grades according to the height of importance by storing content in described storer;
Step S3: the mode with the higher content of the higher described error correction circuit protection importance of performance is matched to described error correction circuit and described grade.
2. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, the quantity of described error correction circuit is with to store the grade quantity that content is divided in described storer identical, and each described error correction circuit only matches with a grade.
3. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, the quantity of described error correction circuit is to store the grade quantity that content is divided in described storer different, and each described error correction circuit mates with multiple grades.
4. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, step S3 also comprises:
Step S31: described storer is powered on, and multiple described error correction circuit does not all enable;
Step S32: described storage content is conducted interviews, enable corresponding error correction circuit according to the corresponding grade of this content;
Step S33: after described storage access to content is completed, corresponding error correction circuit cuts out or lower electricity.
5. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, the area of the logical circuit in the higher described error correction circuit of performance is larger.
6. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, each described error correction circuit detects that wrong figure place is more than or equal to the figure place that it is corrected a mistake.
7. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, the power consumption of the described error correction circuit that performance is higher is larger.
8. the selecting method of error correction circuit in storer as claimed in claim 1, is characterized in that, when size one timing of described storage content, the number of errors that the described error correction circuit that performance is higher can detect and correct is more.
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| US11694761B2 (en) | 2021-09-17 | 2023-07-04 | Nxp B.V. | Method to increase the usable word width of a memory providing an error correction scheme |
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| CN1611027A (en) * | 2001-12-28 | 2005-04-27 | 皇家飞利浦电子股份有限公司 | Unequal error protection using forward error correction based on reed-Solomon codes |
| CN101729910B (en) * | 2008-10-15 | 2011-11-23 | 国家广播电影电视总局广播科学研究院 | Data transmission method and device based on gradable bit streams |
| CN102969028A (en) * | 2012-10-18 | 2013-03-13 | 记忆科技(深圳)有限公司 | Method, system, and flash memory of ECC dynamic adjustment |
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| US11694761B2 (en) | 2021-09-17 | 2023-07-04 | Nxp B.V. | Method to increase the usable word width of a memory providing an error correction scheme |
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