CN104022070B - The forming method of interconnection structure - Google Patents
The forming method of interconnection structure Download PDFInfo
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- CN104022070B CN104022070B CN201310064745.XA CN201310064745A CN104022070B CN 104022070 B CN104022070 B CN 104022070B CN 201310064745 A CN201310064745 A CN 201310064745A CN 104022070 B CN104022070 B CN 104022070B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The forming method of a kind of interconnection structure, including providing substrate, described substrate surface has dielectric layer；Forming the first opening in described dielectric layer, the degree of depth of described first opening is less than the height of dielectric layer；Sidewall surfaces at the first opening forms sacrifice layer；With described hard mask layer as mask, etching described sacrifice layer and dielectric layer along the first opening, form groove, described gash depth is less than the height of dielectric layer；Fill described groove, form metal level, expose the surface of sacrifice layer and dielectric layer；Remove described sacrifice layer, form the second opening in described metal level both sides；Forming cap at described dielectric layer, layer on surface of metal, described cap fills full described second opening.The forming method of described interconnection structure, can improve the Adhesion property of metal level and dielectric layer, effectively reduces metal electro-migration, thus improves the performance of circuit.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the forming method of interconnection structure.
Background technology
Along with the integrated level of semiconductor chip improves constantly, the characteristic size of transistor is constantly reducing.By
In the high-ohmic of aluminium, copper-connection gradually substitutes aluminium interconnection becomes the main flow of metal interconnection, the most extensively
The preparation method of the copper conductor used is the embedding technique of Damascus technics, wherein the double big horse of groove-priority
It is to realize one of copper conductor and the once-forming method of through hole copper that scholar removes from office technique.
Refer to Fig. 1～Fig. 4, for the generalized section of forming method of the copper interconnection structure of prior art.
Refer to Fig. 1, form dielectric layer 11 on the substrate 10, and in described dielectric layer 11, form opening
12。
The method forming described opening 12 includes: on the surface of described dielectric layer 11, spin coating photoresist is also
Patterning；Then for mask, described dielectric layer 11 is performed etching with the photoresist of described patterning, formed
Opening 12, then removes remaining photoresist.
Refer to Fig. 2, formed at the bottom of described opening 12 and sidewall and described dielectric layer surface and stop
Layer 13.
Described barrier layer 13 is possible to prevent the metal in the interconnection line being subsequently formed to external diffusion.
Refer to Fig. 3, described opening 12 is filled metallic copper, forms copper interconnecting line 14, and to described
Copper interconnecting line 14 planarizes, and exposes the surface of dielectric layer 11.
Refer to Fig. 4, form cap 15 at described dielectric layer 11 and copper interconnecting line 14 surface.
The material of described cap is the dielectric materials such as SiN, to protect described dielectric layer 11 and copper interconnecting line 14
Structure is not affected by subsequent technique.
But, the material character between described copper interconnecting line 14 and cap 15 differs relatively big, so both it
Between adhesion strength relatively low so that copper has higher diffusion at the interface of copper interconnecting line 14 with cap 15
And transport efficiency.Transporting along with quality while metal electro-migration, usual copper interconnecting line is because of copper ion
Electromigration can produce at regional area and be piled up by quality and hillock occurs, or by mass deficit, cavity occurs,
Thus cause circuit performance to degenerate or lost efficacy, have a strong impact on the reliability of circuit.
More technology about interconnection structure refer to the United States Patent (USP) of Publication No. US20040187304A1.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of interconnection structure, improves the performance of circuit.
For solving the problems referred to above, technical scheme proposes the forming method of a kind of interconnection structure,
Including: providing substrate, described substrate surface has dielectric layer；Hard mask is formed at described dielectric layer surface
Layer, described hard mask layer has opening, exposes the part surface of dielectric layer；With described hard mask layer it is
Mask, etches described dielectric layer, forms the first opening in described dielectric layer, described first opening deep
Degree is less than the height of dielectric layer；Formed at the sidewall of described first opening and the sidewall surfaces of hard mask layer
Sacrifice layer；With described hard mask layer and sacrifice layer as mask, etch described dielectric layer, shape along the first opening
Becoming groove, described gash depth is less than the height of dielectric layer；Fill described groove, form metal level, institute
State metal level fill full described groove and cover the surface of hard mask layer；With dielectric layer as stop-layer, to institute
State metal level to planarize, expose the surface of sacrifice layer and dielectric layer；Remove described sacrifice layer,
Described metal level both sides form the second opening；Cap, institute is formed at described dielectric layer, layer on surface of metal
State cap and fill full described second opening.
Optionally, the bottom of described first opening is less than hard mask layer surface
Optionally, the forming method of described sacrifice layer is: use chemical vapor deposition method described first
Opening inwall and hard mask layer surface form sacrificial material layer, then use dry etch process, remove institute
State hard mask layer and the sacrificial material layer of the first open bottom, formed and cover the first opening sidewalls and hard mask
The sacrifice layer of layer opening sidewalls.
Optionally, the etching selection ratio between described sacrifice layer and dielectric layer is more than 5:1.
Optionally, the material of described sacrifice layer is silica.
Optionally, the thickness of described sacrifice layer is
Optionally, the method removing described sacrifice layer is wet-etching technology.
Optionally, described wet-etching technology employing HF solution is as etching solution, in described HF solution,
H2The mol ratio of O Yu HF is 300: 1～1000: 1.
Optionally, described dielectric layer includes the etching barrier layer being positioned at substrate surface and is positioned at described etching resistance
The low K dielectric layer on barrier surface.
Optionally, the material of described etching barrier layer is SiN, SiCN or SiONCH, and thickness range is
Optionally, the material of described low K dielectric layer is carborundum, silicon oxide carbide, organosiloxane polymerization
Thing, fluorocarbons.
Optionally, described hard mask layer is stacked structure, including the first hard mask layer and be positioned at described first
Second hard mask layer on hard mask layer surface.
Optionally, the material of described first hard mask layer is SiO2。
Optionally, the material of described second hard mask layer is TiN.
Optionally, also include: after forming described sacrifice layer, at described hard mask layer and the first opening
Interior formation Patterned masking layer, described Patterned masking layer exposes the portion of the dielectric layer of the first open bottom
Divide surface；With described Patterned masking layer as mask, etch described dielectric layer, form through hole.
Optionally, the material of described Patterned masking layer is photoresist.
Optionally, described metal level includes the diffusion impervious layer of covering groove and through-hole wall and is positioned at described
The copper metal layer on diffusion impervious layer surface.
Optionally, the material of described diffusion impervious layer be Ta, TaN, Ti, TiN, Ru, RuN, W or
WN, thickness range is
Optionally, the material of described cap is SiN, SiCN or SiONCH, and thickness range is
Compared with prior art, the invention have the advantages that
Technical scheme, forms the first opening in dielectric layer, is formed and covers the first opening sidewalls
Sacrifice layer；With described hard mask layer and sacrifice layer as mask, etch the first open bottom along the first opening
Dielectric layer, formed groove, in described groove formed metal level；Remove sacrifice layer, at described metal
Layer both sides form the second opening；Cap, described cap is formed at described metal level and dielectric layer surface
Cover metal level, and fill full described second opening.Owing to cap fills the second of full metal level both sides
Opening, so the contact area of cap and metal level increases, can improve the viscous of metal level and cap
Attached property, effectively reduces the electromigration characteristic of metal level, thus improves the reliability of interconnection structure.
Further, technical scheme, use without mask Self-aligned etching technique, described the
One opening inwall and hard mask layer surface form sacrificial material layer, then using plasma etching technics,
Remove hard mask layer surface and the sacrificial material layer on the first open bottom surface, formed and cover the first open side
The sacrifice layer of wall, the thickness of described sacrifice layer is uniform, is easily controlled.Go subsequently through wet-etching technology
Except described sacrifice layer, the material of described sacrifice layer is compared with the material of dielectric layer, and both have higher quarter
Erosion selects ratio, dielectric layer and layer on surface of metal will not be caused damage, Ke Yiti when removing described sacrifice layer
The quality of the cap in the second opening that high subsequent deposition is formed.
Further, described metal level includes diffusion impervious layer and is positioned at the copper on described diffusion impervious layer surface
Metal level.Cap in described second opening covers on diffusion impervious layer surface, described cap and expansion
Dissipate the adhesiveness between the material on barrier layer higher, improve gluing between cap and metal level on the whole
Attached property, reduces the electromigration characteristic of metal level, thus improves the reliability of interconnection structure.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the generalized section of the prior art formation interconnection line of the present invention；
Fig. 5 to Figure 17 is the process schematic forming interconnection structure in embodiments of the invention.
Detailed description of the invention
As described in the background art, the cap of interconnection structure surface of the prior art and metal interconnecting layer
Adhesion strength relatively low so that interconnection metal tight with the case of iontophoresis at metal interconnecting layer interface in cap
Weight, affects the performance of circuit.
Technical scheme, it is provided that the forming method of a kind of interconnection structure, improves described cap
And the adhesion strength between interconnection line, thus lower the electromigration of the metal of interconnection line, thus improve circuit
Performance.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.Described embodiment be only the present invention can
A part for embodiment rather than they are whole.When describing the embodiment of the present invention in detail, for purposes of illustration only,
Schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not at this
Limit the scope of the invention.Additionally, the three of length, width and the degree of depth should be comprised in actual fabrication
Dimension space size.According to described embodiment, those of ordinary skill in the art is without creative work
Under premise, obtainable other embodiments all, broadly fall into protection scope of the present invention.Therefore the present invention
Do not limited by following public being embodied as.
Refer to Fig. 5, it is provided that substrate 100, described substrate surface has dielectric layer 110, described dielectric layer
110 etching barrier layers 101 including being positioned at substrate 100 surface and described etching barrier layer 101 surface low
K dielectric layer 102.
Described substrate 100 is Semiconductor substrate, is formed with semiconductor devices (figure in described Semiconductor substrate
Not shown in).Described substrate 100 can also is that the layer of dielectric material being formed on substrate (not shown),
It is formed with the interconnection structures such as connector in described layer of dielectric material.
Described dielectric layer 110 is as interlayer dielectric layer, and follow-up formation in described dielectric layer 110 links mutually
Structure.Described dielectric layer 110 includes etching barrier layer 101 and low K dielectric layer 102.
The material of described etching barrier layer 101 is SiN, SiCN or SiONCH, described etching barrier layer
Thickness beSemiconductor in 100 at the bottom of described etching barrier layer 101 1 aspect protection group
Device or interconnection structure are not affected by subsequent technique, are on the other hand formed logical as etching low K dielectric layer
The stop-layer in hole, and prevent the interconnection structure metal formed in described low K dielectric layer from spreading to lower floor.
Low-K dielectric material is usually incorporation carbon in silica or in porous silica and reduces material
The K value of material, the material of described low K dielectric layer 102 is that carborundum, silicon oxide carbide, organosiloxane are poly-
The low-K dielectric material such as compound, fluorocarbons.Described low K dielectric layer 102 uses spin coating or chemistry gas
Phase depositing operation is formed.Formed in the low K dielectric layer 102 that described low-K dielectric material is formed and link mutually
Structure, can reduce the electric capacity between interconnection line, reduces the time constant of interconnection line, reduces circuit signal
Postpone.
In the present embodiment, the material of described low K dielectric layer 102 is silicon oxide carbide (SiCOH).
Refer to Fig. 6, form hard mask layer 120, described hard mask layer 120 on described dielectric layer 110 surface
There is opening, expose the part surface of dielectric layer 110.
In the present embodiment, described hard mask layer 120 is stacked structure, including the first hard mask layer 103 He
It is positioned at second hard mask layer 104 on described first hard mask layer 103 surface.
Concrete, the material of described first hard mask layer 103 is SiO2, the material of the second hard mask layer 104
For TiN.Described first hard mask layer 103 uses chemical vapor deposition method to be formed, the described second hard mask
Layer 104 uses physical gas-phase deposition to be formed.
The method forming opening in described hard mask layer 120 includes: depend on described dielectric layer 110 surface
Secondary deposition forms the first hard mask layer 103 and the second hard mask layer 104, forms hard mask layer 120；Institute
Stating hard mask layer 120 surface and form graphical photoresist layer (not shown), described graphical photoresist layer is sudden and violent
Expose the position of opening, be sequentially etched downwards described second hard mask layer 104 and expose the first hard mask layer
Surface；Remove described photoresist layer；With described second hard mask layer 104 as mask, etching first is hard
Mask layer 103, exposes the part surface of dielectric layer 110, forms opening.Use firmly covering of stacked structure
Film layer, can protect the surface of described dielectric layer 110 not sustain damage during forming opening.Institute
State opening and define the position of the follow-up interconnection structure formed in dielectric layer 110.
Refer to Fig. 7, with described hard mask layer 120 as mask, etch described dielectric layer 110, described
Forming the first opening 105 in dielectric layer 110, the degree of depth of described first opening 105 is less than the height of dielectric layer.
Concrete, with described hard mask layer 120 as mask, using plasma etching technics, along described
Opening etch media layer 110, forms the first opening 105.The bottom surface of described first opening 105 is less than firmly covering
Film surfaceThe position of described first opening 105 is the position being subsequently formed interconnection structure
Put.
Refer to Fig. 8, in described first opening 105 and the sidewall surfaces shape of the opening of hard mask layer 120
Become sacrifice layer 106.
In the present embodiment, formed on the opening sidewalls surface of described first opening 105 and hard mask layer 120
The method of sacrifice layer 106 is: use chemical vapor deposition method at described first opening 105 inwall with hard
Mask layer 120 surface forms sacrificial material layer, then uses autoregistration without mask etching technique, removes institute
State hard mask layer 120 and the sacrificial material layer of the first open bottom, formed and cover the first opening 105 sidewall
And the sacrifice layer 106 of the opening sidewalls of hard mask layer 120.Use described autoregistration without mask etching technique shape
Become described sacrifice layer 106, make the thickness of described sacrifice layer 106 and the consistency of thickness of sacrificial material layer, permissible
Adjusted the thickness of the sacrifice layer 106 of formation by the thickness of the sacrificial material layer of deposition, make sacrifice layer 106
Thickness uniform so that subsequent technique is removed second formed in interconnection structure both sides after sacrifice layer 106
The width of opening is identical with the degree of depth, improves the quality of the cap being subsequently formed.
The thickness of described sacrifice layer 106 isMaterial is silica, described sacrifice layer 106
Material compared with low K dielectric layer 102, there is higher etching selection ratio, described etching selection ratio is big
In 5: 1, in order to when removing described sacrifice layer 106 in subsequent technique, do not damage described low K dielectric layer and
Metal level.
In other embodiments of the invention, described sacrifice layer can also cover hard mask layer opening sidewalls,
First opening sidewalls and the first open bottom.The forming method of described sacrifice layer is: open described first
Mouth 105 inwalls and hard mask layer 120 surface form sacrificial material layer；With described hard mask layer 120 for stopping
Only layer, planarizes described sacrificial material layer, removes the sacrificial material layer on hard mask layer surface, after
Before continuous etching low-K material layer, first etching covers the sacrifice layer of the first open bottom.
Refer to Fig. 9, refer to Fig. 8 at described hard mask layer 120 and the first opening 105() in formed
Patterned masking layer 107, described Patterned masking layer 107 exposes the portion bottom surface of the first opening 105.
In the present embodiment, dual-damascene technics is used to form described interconnection structure.So being initially formed etch media
Layer 110 forms the Patterned masking layer of through hole.
The method of described Patterned masking layer 107 is: on described hard mask layer 120 surface, forms mask
Layer, described mask layer covers the surface of hard mask layer, and fills full described first opening 105；Cover described
Membrane graphic, forms Patterned masking layer 107, and described Patterned masking layer 107 exposes the first opening
Part surface bottom 105, defines the width of the through hole being subsequently formed.
In the present embodiment, the material of described Patterned masking layer 107 is photoresist layer.
Refer to Figure 10, with described Patterned masking layer 107 as mask, etch described low K dielectric layer 102,
Form through hole 108.
Concrete employing dry etch process, with described Patterned masking layer 107 as mask, etches sacrificial
Low K dielectric layer 102, with described etching barrier layer 101 as stop-layer, forms through hole 108.
Refer to Figure 11, remove described Patterned masking layer 107(and refer to Figure 10).
In the present embodiment, use cineration technics to remove described Patterned masking layer 107, expose the first opening
105, sacrifice layer 106 and hard mask layer 120.So far step, in dual-damascene technics to the etching of through hole
Through completing.
Refer to Figure 12, with described hard mask layer 120 and sacrifice layer 106 as mask, along the first opening 105
(refer to Figure 11) etches described low K dielectric layer 102, forms groove 109.
Using plasma etching technics, is sequentially etched described sacrifice layer 106 and low K dielectric layer 102,
Forming the groove 109 of certain depth, described groove 109 connects with through hole 108.Described groove is used for being formed
The interconnection line being connected with the connector formed in through hole.Described groove 109 both sides also have partial sacrificial layer 106.
Further, in described etching process, described etching barrier layer 101 is etched the most simultaneously, makes described
Through hole 108 is positioned at substrate 100 surface, follow-up formation connector and the company in substrate 100 in through hole 108
Access node structure or the electrical connection of semiconductor devices (not shown).
Refer to Figure 13, formed at described groove 109 and through hole 108 inwall and hard mask layer 130 surface
Diffusion impervious layer 130.
The material of described diffusion impervious layer 130 is Ta, TaN, Ti, TiN, Ru, RuN, W or WN
Deng material, scope isThe forming method of described diffusion impervious layer 130 is that chemical gaseous phase is sunk
Long-pending technique or sputtering technology.
Described diffusion impervious layer 130, as the barrier layer of the interconnection structure being subsequently formed, is possible to prevent described
Metal in interconnection structure is to external diffusion, and has preferable adhesiveness with interconnection metal, thus improves
Adhesiveness between interconnection structure and dielectric layer 110.
Refer to Figure 14, form the copper metal layer 131 being positioned at described diffusion impervious layer 130 surface.
Described copper metal layer 131 covers the surface of diffusion impervious layer 130, and fill full described groove and
Through hole.The forming method of described copper metal layer 131 is plating or electrochemical plating technique.In the present embodiment,
First use sputtering technology, form one layer of copper seed layer (not shown) on described diffusion impervious layer 130 surface,
Described copper seed layer is as the nucleus of formation copper metal layer, and forms copper gold as follow-up employing electroplating technology
Belong to the electrode of layer 131, the quality of the copper metal layer 131 of formation can be improved.
Refer to Figure 15, with low K dielectric layer 102 as stop-layer, described copper metal layer 131(please be joined
Examine Figure 14) planarize, expose sacrifice layer 106 and the surface of low K dielectric layer 102.
Concrete, use chemical mechanical milling tech, described copper metal layer 131(be refer to Figure 14)
It is ground, using described low K dielectric layer as polish stop layer, removes described low K dielectric layer 102 table
The hard mask layer 120(in face refer to Figure 14), part diffusion impervious layer 130(refer to Figure 14) and portion
Copper metal layer 131(is divided to refer to Figure 14), make copper metal layer 131a, diffusion impervious layer 130a, sacrifice layer
106 and the surface of low K dielectric layer 102 flush, described copper metal layer 131a and diffusion impervious layer 130a
Form interconnection structure.
Refer to Figure 16, remove described sacrifice layer 106(and refer to Figure 15), at described copper metal layer 131a
The interconnection structure both sides formed with diffusion impervious layer 130a form the second opening 132.
Concrete, remove described sacrifice layer 106(and refer to Figure 15) method be selective etch technique.
In the present embodiment, using wet-etching technology, use HF solution as etching solution, described HF is molten
In liquid, H2The mol ratio of O Yu HF is 300: 1～1000: 1.
Owing to the material of described sacrifice layer 106 is different from the material of low K dielectric layer 102 and described sacrificial
Domestic animal layer 106 has higher etching selection ratio compared to low K dielectric layer 102, uses wet-etching technology
Described sacrifice layer 106 can be removed, and copper metal layer 131a and diffusion impervious layer 130a will not be caused
Damage.After removing described sacrifice layer, the second opening of formation exposes the part of diffusion impervious layer 130a
Sidewall.
Refer to Figure 17, at described low K dielectric layer 102, diffusion impervious layer 130a, copper metal layer 131a
Surface forms cap 140, and described cap 140 fills full described second opening 132.
Concrete, in the present embodiment, use chemical vapor deposition method to form described cap 140, described
The material of cap 140 is SiN, SiCN, SiOCH or SiONCH, and thickness is
Described cap 140 is possible to prevent copper metal layer surface to be passivated, and protects described interconnection structure to exist
Subsequent technique is not affected, and, the gold that described cap 140 is also prevented from interconnection structure
Belong to and outwards diffusing in low K dielectric layer, affect the performance of circuit.
In the present embodiment, owing to eliminating described sacrifice layer 106, at diffusion impervious layer 130a and copper metal
The interconnection structure both sides that layer 131a is formed form the second opening 132.Described cap 140 is filled full described
Second opening 132, improves the contact area between cap and interconnection structure, improves cap 140
And the adhesion property between interconnection structure.And, between described cap 140 and diffusion impervious layer 130a
Adhesiveness higher, further increase cap 140 and copper metal layer 131a and diffusion barrier on the whole
Adhesiveness between layer 130a, reduces the case of iontophoresis of metal interconnection structure, thus improves interconnection
Reliability of structure.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology, therefore, every without departing from this
The content of inventive technique scheme, according to the technical spirit of the present invention above example is made any simply
Amendment, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (19)
1. the forming method of an interconnection structure, it is characterised in that including:
Thering is provided substrate, described substrate surface has dielectric layer；
Forming hard mask layer at described dielectric layer surface, described hard mask layer has opening, exposes medium
The part surface of layer；
With described hard mask layer as mask, etch described dielectric layer, in described dielectric layer, form first open
Mouthful, the degree of depth of described first opening is less than the height of dielectric layer；
Sacrifice layer is formed at the sidewall of described first opening and the sidewall surfaces of hard mask layer；
With described hard mask layer and sacrifice layer as mask, etch described dielectric layer along the first opening, form ditch
Groove, described gash depth is less than the height of dielectric layer；
Filling described groove, form metal level, described metal level is filled full described groove and covers hard mask
The surface of layer；
With dielectric layer as stop-layer, described metal level is planarized, expose sacrifice layer and dielectric layer
Surface；
Remove described sacrifice layer, form the second opening in described metal level both sides；
Forming cap at described dielectric layer, layer on surface of metal, described cap is filled full described second and is opened
Mouthful.
The forming method of interconnection structure the most according to claim 1, it is characterised in that described first opening
Bottom less than hard mask layer surface
The forming method of interconnection structure the most according to claim 1, it is characterised in that described sacrifice layer
Forming method is: use chemical vapor deposition method in described first opening inwall and hard mask layer surface shape
Become sacrificial material layer, then use dry etch process, remove described hard mask layer surface and the first opening
The sacrificial material layer of bottom, forms the sacrifice layer of the opening sidewalls covering the first opening sidewalls and hard mask layer.
The forming method of interconnection structure the most according to claim 1, it is characterised in that described sacrifice layer with
Etching selection ratio between dielectric layer is more than 5:1.
The forming method of interconnection structure the most according to claim 1, it is characterised in that described sacrifice layer
Material is silica.
The forming method of interconnection structure the most according to claim 1, it is characterised in that described sacrifice layer
Thickness is
The forming method of interconnection structure the most according to claim 1, it is characterised in that remove described sacrifice
The method of layer is wet-etching technology.
The forming method of interconnection structure the most according to claim 7, it is characterised in that described wet etching
Technique employing HF solution is as etching solution, in described HF solution, and H2The mol ratio of O with HF is
300:1～1000:1.
The forming method of interconnection structure the most according to claim 1, it is characterised in that described dielectric layer bag
Include the etching barrier layer being positioned at substrate surface and the low K dielectric layer being positioned at described etching barrier layer surface.
The forming method of interconnection structure the most according to claim 9, it is characterised in that described etch stopper
The material of layer is SiN, SiCN or SiONCH, and thickness range is
The forming method of 11. interconnection structures according to claim 9, it is characterised in that described low-K dielectric
The material of layer is carborundum, silicon oxide carbide, organic siloxane polymer, fluorocarbons.
The forming method of 12. interconnection structures according to claim 1, it is characterised in that described hard mask layer
For stacked structure, including the first hard mask layer and the second hard mask being positioned at described first hard mask layer surface
Layer.
The forming method of 13. interconnection structures according to claim 12, it is characterised in that described first hard
The material of mask layer is SiO2。
The forming method of 14. interconnection structures according to claim 12, it is characterised in that described second hard
The material of mask layer is TiN.
The forming method of 15. interconnection structures according to claim 1, it is characterised in that also include: in shape
After becoming described sacrifice layer, in described hard mask layer and the first opening, form Patterned masking layer, described
Patterned masking layer exposes the part surface of the dielectric layer of the first open bottom；With described pattern mask
Layer is mask, etches described dielectric layer, forms through hole.
The forming method of 16. interconnection structures according to claim 15, it is characterised in that described graphically
The material of mask layer is photoresist.
The forming method of 17. interconnection structures according to claim 15, it is characterised in that described metal level
Diffusion impervious layer and the copper metal being positioned at described diffusion impervious layer surface including covering groove and through-hole wall
Layer.
The forming method of 18. interconnection structures according to claim 17, it is characterised in that described diffusion hinders
The material of barrier is Ta, TaN, Ti, TiN, Ru, RuN, W or WN, and thickness range is
The forming method of 19. interconnection structures according to claim 1, it is characterised in that described cap
Material is SiN, SiCN or SiONCH, and thickness range is
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| CN111063655A (en) * | 2018-10-17 | 2020-04-24 | 无锡华润上华科技有限公司 | Method for manufacturing semiconductor device |
| CN113488392B (en) * | 2021-07-13 | 2022-08-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing integrated circuit device |
| CN117253850B (en) * | 2023-11-15 | 2024-02-02 | 合肥晶合集成电路股份有限公司 | Method for forming interconnection opening and method for forming interconnection structure |
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| US7348672B2 (en) * | 2005-07-07 | 2008-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnects with improved reliability |
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| US6066556A (en) * | 1997-12-23 | 2000-05-23 | Samsung Electronics Co., Ltd. | Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated |
| CN1832126A (en) * | 2005-03-08 | 2006-09-13 | 联华电子股份有限公司 | Manufacturing method of in-connection and manufacturing method of composite dielectric barrier-layer |
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