CN104009020B - Wafer and its acceptance test method - Google Patents
Wafer and its acceptance test method Download PDFInfo
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- CN104009020B CN104009020B CN201310062594.4A CN201310062594A CN104009020B CN 104009020 B CN104009020 B CN 104009020B CN 201310062594 A CN201310062594 A CN 201310062594A CN 104009020 B CN104009020 B CN 104009020B
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Abstract
The present invention discloses a kind of wafer, including being formed thereon and chip arranged in arrays, the chip is divided into multiple test zones, each test zone includes at least four chips arranged in arrays, interval region formation between the chip of each test zone is located at the scribe line in the test zone, at least two alignment patterns are provided with scribe line in each test zone, and an alignment patterns are respectively provided with least in horizontal scribe line and in the scribe line of longitudinal direction.A kind of wafer acceptance test method is also disclosed, is arranged on alignment patterns in horizontal and longitudinal direction scribe line using above-mentioned and is positioned test zone.Above-mentioned wafer and method of testing, can be prevented effectively from because misidentification alignment patterns and caused by wafer damage.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of wafer acceptance test method and one kind are brilliant
Circle.
Background technology
WAT（Wafer acceptance test, wafer acceptance test）It is the important step in chip manufacturing proces,
For detecting whether the chip on wafer meets expected design object, namely whether the electrical parameter of chip meets client's need
Ask.
WAT's is subregion（block）Carry out, every time one region of test.One region includes multiple chips
（die）, multiple chips are all spaced apart each other, and the region being wherein spaced between chip is referred to as scribe line or Cutting Road
（subscribe line）.In order to be accurately positioned the position of test zone, some alignment patterns will be generally set on wafer,
To aid in alignment.Alignment patterns are just arranged in above-mentioned scribe line, and the circuitous pattern on its figure and chip is completely not
Together, in favor of resolution.
However, in traditional WAT methods, because the aligning accuracy of probe program is inadequate, the alignment patterns in scribe line
When relatively, if occurring the situation of misidentification alignment patterns, locating bias may result in.So probe, which cannot accurately fall, is surveying
Pilot, and the other parts of chip are scratched, cause wafer loss.
The content of the invention
Based on this, it is necessary to which providing one kind being capable of pinpoint wafer acceptance test method.
In addition, also providing a kind of wafer for enabling WAT methods to be accurately positioned test zone.
A kind of wafer, including be formed thereon and chip arranged in arrays, the chip is divided into multiple test sections
Domain, each test zone includes the interval between at least four chips arranged in arrays, the chip of each test zone
Region, which is formed, is provided with least two pairs in the scribe line in the scribe line being located in the test zone, each test zone
Quasi- figure, and it is respectively provided with least an alignment patterns in the scribe line of horizontal scribe line and longitudinal direction.
In one of the embodiments, the alignment patterns are arranged on farthest horizontal and longitudinal direction the scribing of mutual distance
In groove.
A kind of wafer acceptance test method, comprises the following steps：Set at least in the scribe line of each test zone
Two alignment patterns, and it is respectively provided with least an alignment patterns in horizontal scribe line and in the scribe line of longitudinal direction；Using
Angle of the low power benchmark contraposition adjustment wafer on testboard；Test zone is positioned using the contraposition of high power benchmark, specifically
Including：The alignment patterns being arranged on respectively described in positioning in horizontal scribe line and the alignment figure being arranged in longitudinal scribe line
Shape；Define test module；Verification Wafer alignment information is simultaneously tested.
In one of the embodiments, the step of adjustment angle of the wafer on testboard is aligned using low power benchmark it
Before, also the edge of wafer is aligned.
In one of the embodiments, the step of use low power benchmark contraposition adjusts angle of the wafer on testboard
The angle of wafer is adjusted using the upper, middle and lower under low power contraposition module, left and right 5 contraposition modules.
In one of the embodiments, the step of being positioned using the contraposition of high power benchmark to test zone is using height
Upper, middle and lower, left and right 5 contraposition modules under times contraposition module are positioned to test zone.
Above-mentioned wafer and method of testing, it is horizontal and vertical due to being separately positioned on when being aligned using alignment patterns
To scribe line in, the relative coordinate of the two is fixed, when one of alignment patterns are easily mistaken for, the position of another alignment patterns
Put and necessarily lead to skew（Usually it is displaced to the position of chip）, and the circuitous pattern in alignment patterns and chip is not the same
Or it is similar.When being easily mistaken for due to one of them and produce skew, another alignment patterns can not be identified in the position of mistake,
Test zone can not thus be positioned, follow-up testing procedure can not just be carried out, therefore it is possible to prevente effectively from because of misidentification pair
Quasi- figure and the wafer that causes is damaged.
Brief description of the drawings
Fig. 1 is the wafer schematic diagram of an embodiment；
Fig. 2 is the partial enlarged drawing of part A in Fig. 1；
Fig. 3 is the flow chart of the wafer acceptance test method of an embodiment.
Embodiment
As shown in figure 1, being the wafer schematic diagram of an embodiment.The wafer 10 includes being formed thereon and arranged in arrays
Chip 100, the chip 100 is divided into multiple test zones 200.The division of test zone 200 can be according to test needs
Or divided with functional area.Each test zone 200 includes at least four chip 100 arranged in arrays.
As shown in Fig. 2 being the partial enlarged drawing of part A in Fig. 1.In wafer 10, chip 100 is not close-packed arrays
, but there is 60 ~ 100 microns of interval, i.e. scribe line or Cutting Road each other（subscribe line）.The present embodiment
Wafer 10 be, provided with two alignment patterns 202,204, and to be separately positioned on horizontal stroke in scribe line in each test zone 200
To scribe line in and longitudinal direction scribe line in.The position of alignment patterns in other test zones 200 can refer to part A progress
Set.
Above-mentioned wafer 10, it is horizontal and vertical due to being separately positioned on when being aligned using alignment patterns 202,204
Scribe line in, the relative coordinate of the two is fixed, when one of alignment patterns are easily mistaken for, the position of another alignment patterns
Necessarily lead to skew（Usually it is displaced to the position of chip）, and the circuitous pattern in alignment patterns and chip is not the same or
It is similar.When being easily mistaken for due to one of them and produce skew, another alignment patterns can not be identified in the position of mistake, because
And test zone 200 can not be positioned, follow-up testing procedure can not just be carried out, therefore it is possible to prevente effectively from because of misidentification pair
Quasi- figure and the wafer that causes is damaged.
In a preferred embodiment, alignment patterns 202,204 are arranged on the farthest horizontal and longitudinal direction of mutual distance
Scribe line in.So, when one of alignment patterns are easily mistaken for, the position of another alignment patterns can produce the inclined of maximum
Move, be conducive to avoiding mistake.
As shown in figure 3, the flow chart of the wafer acceptance test method for an embodiment.This method comprises the following steps.
S101：Two alignment patterns are set in the scribe line of each test zone, and described two alignment patterns are distinguished
It is arranged in horizontal scribe line and in the scribe line of longitudinal direction.The specific mode that may be referred in Fig. 2 sets alignment patterns.
S102：The edge of wafer is aligned.Wafer 10 as shown in Figure 1, with two edges scabbled, is utilized
The edge is slightly aligned, and wafer is placed on to the correct position on testboard.
S103：Angle of the adjustment wafer on testboard is aligned using low power benchmark.This step is aligned using low power
Upper, middle and lower, left and right 5 contraposition modules under module adjust the angle of wafer.
S104：Test zone is positioned using the contraposition of high power benchmark.This step is specifically included：Set respectively described in positioning
Put the alignment patterns in horizontal scribe line and the alignment patterns being arranged in longitudinal scribe line.Likewise, high power benchmark
Contraposition is positioned using the upper, middle and lower under high power contraposition module, left and right 5 contraposition modules to test zone.
Positioning can carry out test job after completing, that is, perform following steps.
S105：Define test module.
S106：Verification Wafer alignment information is simultaneously tested.
Above-mentioned method of testing, the alignment patterns 202,204 being arranged on due to being utilized respectively in horizontal and vertical scribe line
It is aligned, and the relative coordinate of the two is fixed, when one of alignment patterns are easily mistaken for, the position of another alignment patterns
Necessarily lead to skew（Usually it is displaced to the position of chip）, and the circuitous pattern in alignment patterns and chip is not the same or
It is similar.When being easily mistaken for due to one of them and produce skew, another alignment patterns can not be identified in the position of mistake, because
And test zone 200 can not be positioned, follow-up testing procedure can not just be carried out, therefore it is possible to prevente effectively from because of misidentification pair
Quasi- figure and the wafer that causes is damaged.
Embodiment described above only expresses the several embodiments of the present invention, and it describes more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (4)
1. a kind of wafer acceptance test method, comprises the following steps：
At least two alignment patterns are set in the scribe line of each test zone, and in the scribing of horizontal scribe line and longitudinal direction
An alignment patterns are respectively provided with least in groove；
Angle of the adjustment wafer on testboard is aligned using low power benchmark；
Test zone is positioned using the contraposition of high power benchmark, specifically included：Respectively horizontal scribing is arranged on described in positioning
Alignment patterns and the alignment patterns being arranged in longitudinal scribe line in groove；
Define test module；
Verification Wafer alignment information is simultaneously tested.
2. wafer acceptance test method according to claim 1, it is characterised in that adjustment is being aligned using low power benchmark
Before the step of angle of the wafer on testboard, also the edge of wafer is aligned.
3. wafer acceptance test method according to claim 1, it is characterised in that the use low power benchmark contraposition is adjusted
The step of angle of the whole wafer on testboard, is using the upper, middle and lower under low power contraposition module, left and right five contrapositions mould
Block adjusts the angle of wafer.
4. wafer acceptance test method according to claim 1, it is characterised in that using the contraposition of high power benchmark to test
The step of region is positioned is using the upper, middle and lower under high power contraposition module, left and right five contraposition modules to test section
Domain is positioned.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310062594.4A CN104009020B (en) | 2013-02-27 | 2013-02-27 | Wafer and its acceptance test method |
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|---|---|---|---|
| CN201310062594.4A CN104009020B (en) | 2013-02-27 | 2013-02-27 | Wafer and its acceptance test method |
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| CN104009020A CN104009020A (en) | 2014-08-27 |
| CN104009020B true CN104009020B (en) | 2017-08-08 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104297659B (en) * | 2014-10-28 | 2017-08-08 | 北京思比科微电子技术股份有限公司 | The band pattern CP test devices of CMOS image sensor product |
| CN111665689A (en) * | 2019-03-08 | 2020-09-15 | 长鑫存储技术有限公司 | Alignment mark and semiconductor structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6905897B1 (en) * | 2003-12-10 | 2005-06-14 | Nanya Technology Corp. | Wafer acceptance testing method and structure of a test key used in the method |
| KR20050064287A (en) * | 2003-12-23 | 2005-06-29 | 삼성전자주식회사 | Wafer with overlay measurement key in the middle area of photolithography field |
| US7387950B1 (en) * | 2006-12-17 | 2008-06-17 | United Microelectronics Corp. | Method for forming a metal structure |
| CN102931186B (en) * | 2011-12-15 | 2015-05-06 | 无锡中星微电子有限公司 | Wafer with narrower scribing slots |
| CN102722082B (en) * | 2012-07-04 | 2019-01-18 | 上海华虹宏力半导体制造有限公司 | A kind of mask plate and alignment precision measurement method |
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