CH717513B1 - Output driver controlled by slew rate. - Google Patents

Abstract

The present invention relates to a slew rate control circuit (100) for an integrated circuit having an input node (101) and an output node (102). Said slew rate control circuit (100) comprises at least one main circuit (110) connected to at least one current generator (160). Said main circuit (110) comprises at least a pair of first auxiliary circuit transistors (103), at least one first main capacitor (120) for reducing electromagnetic interference, at least one first main circuit transistor (130) connected to said first main capacitor (120) and at least one pair of second auxiliary circuit transistors (107), at least one second main capacitor (140), and at least one second main circuit transistor (150) connected to said second main capacitor ( 140). The invention also relates to a method of controlling transition times for an input/output interface using said slew rate control circuit.

Description

Technical area

[0001] The present invention relates to the field of driver circuits controlled by scanning speed and in particular concerns USB drivers.

Background of the invention

[0002] In many general-purpose input/output interfaces, such as USB, it is necessary to provide a signal which varies between a low state, generally 0 volts, and a high state, generally 3.3 volts, and features controlled rise/fall time to reduce electromagnetic interference, EMI for short, and power/ground noise.

[0003] In addition, the transition time ratio (rise time to fall time) and the differential output crossover voltage range must be well controlled. The output crossover voltage of two drivers operating in opposite phases can be regulated by the ratio of the delay time to increase to the delay time to decrease using capacitive feedback.

However, if the initial conditions of said capacitive feedback at each clock cycle are not well controlled, this leads to a problem.

Summary of the invention

[0005] In order to achieve this objective, the present invention proposes a circuit for controlling the scanning speed of an integrated circuit; said slew rate control circuit having an input node and an output node; said slew rate control circuit comprising at least one main circuit configured to be connected to at least one current generator; said at least one main circuit comprising: – at least one pair of first auxiliary circuit transistors configured to be connected to said at least one current generator; – at least one first main capacity; said at least one first main capacitor is configured to control the rising output slope; – at least one first main circuit transistor having a first main source connected to a first terminal of a power supply, having a first main gate connected to said at least one pair of first auxiliary circuit transistors, and having a first main drain connected to said output node; said at least one first main capacitor being connected between said first main gate and said first main drain; – at least one pair of second auxiliary circuit transistors operating in phase opposition and configured to be connected to said at least one current generator; – at least one second main capacity; said at least one second main capacitor is configured to control the downward output slope; and, – at least one second main circuit transistor having a first second source connectable to a second terminal of said power supply, having a second main gate connected to said at least one pair of second auxiliary circuit transistors, and having a second drain main connected to said output node; said at least one second main capacitor being connected between said second main gate and said second main drain.

Consequently, this configuration makes it possible to provide a signal which varies between the voltage of said first terminal of said power supply, for example 3.3 V, and the voltage of said second terminal of said power supply, for example 0 V , to a controlled transition output slope to reduce electromagnetic interference and power supply noise, for example. Additionally, the transition time ratio, i.e. rise time to fall time, and the differential output crossover voltage range between two slew rate controlled driver circuits operating in opposition, are perfectly ordered.

[0007] According to one embodiment, said at least one pair of first auxiliary circuit transistors comprises a first PMOS transistor configured to connect said first main gate to the first terminal and to block the conduction of said at least one first main circuit transistor and a first NMOS transistor configured to connect said first main gate to a current generator and to enable controlled conduction of said at least one first main circuit transistor and/or said at least one pair of second auxiliary circuit transistors comprises a second transistor NMOS configured to connect said second main gate to the second terminal and to block the conduction of said at least one second main circuit transistor and a second PMOS transistor configured to connect said second main gate to a current generator and to allow controlled conduction of said at least one second main circuit transistor.

[0008] Consequently, thanks to this configuration, said scanning speed control circuit can control the transition times.

[0009] According to one embodiment, said at least one pair of first auxiliary circuit transistors and/or said at least one pair of second auxiliary circuit transistors is or are configured to be connected to said node d 'entrance.

Consequently, this configuration makes it possible to connect said first main grid to said first terminal of said electrical power supply, for example 3.3 V, or said current generator and/or said second main grid to said second terminal of said power supply electrical, for example 0 V, or said current generator.

[0011] According to one embodiment, said at least one first main circuit transistor is a PMOS transistor and/or said at least one second main circuit transistor is an NMOS transistor.

[0012] Thanks to this configuration, said at least one first main circuit transistor and said at least one second main circuit transistor can alternate in order to provide an output signal which varies between the voltage of said first terminal and the voltage of said second terminal of said power supply.

[0013] According to one embodiment, said at least one current generator comprising at least one first current source connected to at least one second current source: – said at least one first current source being configured to be connected to said second terminal of said power supply and to said at least one pair of first auxiliary circuit transistors; and, – said at least one second current source being configured to be connected to said first terminal of said power supply and to said at least one pair of second auxiliary circuit transistors.

[0014] According to one embodiment, said at least one first current source comprises a first current mirror, preferably comprising NMOS transistors, and/or said at least one second current source comprises a second current mirror, comprising preferably PMOS transistors.

Consequently, this configuration makes it possible to supply a current to said at least one pair of first and second auxiliary circuit transistors when the signal varies between the voltage of said first terminal of said electrical power supply, for example 3.3 V, and the voltage of said second terminal of said power supply, for example 0 V.

[0016] According to one embodiment, said first current mirror comprises a first cascode output made of a first NMOS cascode output connected to said at least one pair of first auxiliary circuit transistors and a second NMOS cascode output connected to said second terminal of said power supply, and an NMOS transistor connected as an input diode having a first NMOS source connected to said second terminal of said power supply, a first NMOS drain connected to a first NMOS gate, to a gate of said second NMOS cascode output and preferably to a terminal of a first resistor; preferably, another terminal of said first resistor is connected to a gate of said first NMOS cascode output and to a terminal of a common resistor; and said second current mirror comprises a second cascode output made of a first PMOS cascode output to said at least one pair of first auxiliary circuit transistors and a second PMOS cascode output connected to said first terminal of said power supply, a PMOS transistor connected as an input diode having a first PMOS source connected to said first terminal of said power supply, a first PMOS drain connected to a first PMOS gate, to a gate of said second PMOS cascode output and preferably to a terminal d 'a second resistance; preferably another terminal of said second resistor is connected to a gate of said first PMOS cascode output and to another terminal of a common resistor.

Consequently, this configuration makes it possible to provide a first current used to control the upward slope and a second current used to control the downward slope, to have a small offset, which is necessary to control the ratio of upward to downward slope. , and to be little dependent on the electrical supply, which reduces the dependence of the transition time on said electrical supply. Furthermore, this configuration optimizes the relationship between the two current sources and the currents generated by this configuration depend on the supply voltage and therefore reduce the dependence on the transition times of the supply voltage.

[0018] In order to achieve this objective, the present invention provides a slew rate controlled method for a slew rate control circuit; said slew rate controlled method comprising: – a transition of said input node between said second terminal of said power supply and said first terminal of said power supply; – a connection of said output node to said first terminal of said power supply via said at least one first main circuit transistor or said second terminal of said power supply via said at least one second main circuit transistor; – an initiation of conduction of said at least one first main circuit transistor or of said at least one second main circuit transistor; – by having a constant control voltage, said main circuit transistors supply a constant current to a load capacitor so as to produce a linear output voltage variation and therefore a constant current flow through at least a first main capacitor or at least one second main capacity; – by having an output node reaching said second terminal of said power supply or said first terminal of said power supply and a current passing through, at least one first main capacitance or at least one second main capacitance decreases until the currents are canceled and make it possible to resume the transition of said first main gate or said second main gate; – a connection of said first main gate to said first terminal of said power supply so as to deactivate said at least one first main circuit transistor or said second main gate to said second terminal of said power supply so as to deactivate said at least one second main circuit transistor.

Consequently, this configuration makes it possible to provide a signal which varies between the voltage of said first terminal of said power supply, for example 3.3 V, and the voltage of said second terminal of said power supply, for example 0 V. , to a controlled transition output slope to reduce electromagnetic interference and power supply noise, for example. Additionally, the transition time ratio, i.e. rise time to fall time, and the differential output crossover voltage range between two slew rate controlled driver circuits operating in opposition, are perfectly ordered.

Brief description of the drawings

[0020] The foregoing objectives, characteristics, aspects and advantages, as well as others, of the invention will emerge from the following detailed description of the embodiments, given by way of illustration and not limitation with reference to the appended drawings , in which: – Figure 1 represents a scanning speed control circuit 100 according to one embodiment; and, – Figure 2 illustrates a control sequence of the scan rate controlled method 500 according to one embodiment.

Description of the invention

[0021] As previously mentioned, in many general purpose input/output interfaces, such as USB, it is necessary to provide a signal which varies between a low state, generally 0 volts, and a high state, generally 3 ,3 volts, and it is necessary to have a controlled rise/fall time to reduce EMI and power/ground noise. The ratio of upslope to downslope is primarily controlled by two paired capacitive feedbacks. Additionally, this matched capacitive feedback will help control the output crossover voltage of two drivers operating in opposite phases, which is the ratio of delay time to increase to delay time to decrease. This transition time ratio is controlled by the present invention, which provides a slew rate control circuit 100 for an integrated circuit. As illustrated in Figure 1, said slew rate control circuit 100 has an input node 101 and an output node 102, and comprises at least one main circuit 110 configured to be connected to at least one current generator 160 Said at least one main circuit 110 comprises at least a pair of first auxiliary circuit transistors 103 configured to be connected to a first terminal 901 of a power supply 900, to said at least one current generator 160 and to said input node 101, at least one first main capacitor 120, and also comprises at least one pair of second auxiliary circuit transistors 107 configured to be connected to said at least one current generator 160 and to said input node 101, at least one second main capacitor 140.

[0022] The state of the art uses only a single feedback capacitor, which is switched at each half-period of the clock signal from the gate of the NMOS driver to the gate of the PMOS driver and vice versa. This topology seriously affects the ratio between the delay time to increase and the delay time to decrease. Due to capacitive feedback, the gate voltage of the drivers is constant during the transition and not too far from the threshold voltage. Then the gate voltage must increase until the supply voltage is turned off so that the feedback capacitor is fully charged before being switched to the other gate. The initial condition is therefore the same for each transition. As the transition time can be a large portion of the half clock period, up to about 50%, the voltage gate slope is approximately equal to the output slope and the voltage going from the 'plateau' Until the supply is large enough, the gate voltage does not have enough time to reach the supply voltage before the end of the half clock period. In this case, the initial condition may be very different between the up and down transition, which affects the transition but much more the delay before the transition. Therefore, the present invention uses two capacitors, said at least one first main capacitor 120 and said at least one second main capacitor 140, and thus improves the ratio of transition time, i.e. rise time to time down, and the differential output crossover voltage range. The output crossover voltage of two drivers operating in opposite phases is mainly controlled by the ratio of the delay time to increase and the delay time to decrease.

Said at least one current generator 160 comprises at least one first current source 170 connected to at least one second current source 180. Said at least one first current source 170 can be connected to a second terminal 902 of said power supply 900 and to said at least one pair of first auxiliary circuit transistors 103, and said at least one second current source 180 can be connected to said first terminal 901 of said power supply 900 and to said at least one pair of second auxiliary circuit transistors 107, as shown in Figure 1. It should be noted that a specific implementation of the current source reduces the dependence of the transition time on the supply voltage and improves the control of the time ratio of transition.

[0024] On the one hand, said first current mirror 170 comprises a first cascode output 176, 177 made of a first NMOS cascode output 177 connected to said at least one pair of first auxiliary circuit transistors 103 and a second NMOS cascode output 176 cascoded by said first NMOS cascode output 177 and connected to said second terminal 902 of said power supply 900.

As shown in Figure 1, an NMOS transistor connected as an input diode 171 has a first NMOS source 172 connected to said second terminal 902 of said electrical power supply 900, a first NMOS drain 173 connected to a first NMOS gate 174 , to a gate of said second NMOS cascode output 176 and, according to certain embodiments, to a terminal of a first resistor 179.

Another terminal of said first resistor 179 can be connected to a gate of said first NMOS cascode output 177 and to a terminal of a common resistor 190.

[0027] Furthermore, said second current mirror 180 comprises a second cascode output 186, 187 made of a first PMOS cascode output 187 to said at least one pair of first auxiliary circuit transistors 107 and a second PMOS cascode output 186 cascoded by said first PMOS cascode output 187 and connected to said first terminal 901 of said power supply 900.

[0028] A PMOS transistor connected as an input diode 181 has a first PMOS source 182 connected to said first terminal 901 of said electrical power supply 900, a first PMOS drain 183 connected to a first PMOS gate 184, to a gate of said second PMOS cascode output 186 and preferably to one terminal of a second resistor 189. The other terminal of said second resistor 189 is connected to a gate of said first PMOS cascode output 187 and to another terminal of a common resistor 190.

[0029] Furthermore, said at least one first main capacitor 120 is configured to control the rising output slope and at least one first main circuit transistor 130, generally a PMOS transistor 130, having a first main source 131 connected to said first terminal 901 of said power supply 900, having a first main gate 132 connected to said at least one pair of first auxiliary circuit transistors 103, and having a first main drain 133 connected to said output node 102; said at least one first main capacitor 120 being connected between said first main gate 132 and said first main drain 133, on one side of a load capacitor 999.

[0030] Indeed, said output node 102, said at least one first main capacitor 120 and said at least one second main capacitor 130 construct a Y circuit. The Y circuit has three terminals and, on each of them, there is at least one electrical component. For example, on one terminal, there is said output node 102, on another terminal, said at least one first main capacity 120 and, on the last, there is said at least one second main capacity 140.

Said at least one main circuit 110 comprises at least one pair of second auxiliary circuit transistors 107 operating in phase opposition and configured to be connected to said second terminal 902, to said at least one current generator 160, to said node d input 101, and at least one second main capacitor 140. Said at least one second main capacitor 140 is configured to control the downward output slope and at least one second main circuit transistor 150 having a first second source 151 connectable to said second terminal 902 of said power supply 900, having a second main gate 152 connected to said at least one pair of second auxiliary circuit transistors 107, and having a second main drain 153 connected to said output node 102; said at least one second main capacitor 140 being connected between said second main gate 152 and said second main drain 153.

Consequently, said scanning speed control circuit 100 makes it possible to provide a signal which varies between the voltage of said first terminal 901 of said electrical power supply 900, for example 3.3 V, and the voltage of said second terminal 902 of said power supply 900, for example 0 V, to a controlled transition output slope to reduce electromagnetic interference and power supply noise, for example. Furthermore, the transition time ratio, i.e. rise time to fall time, and the differential output crossover voltage range between two slew rate controlled driver circuits operating in opposition, are perfectly orders.

[0033] In fact, said scanning speed control circuit 100 implements a method controlled by scanning speed 500, as illustrated in Figure 2.

Said input node 101, generally a clock signal input, can make the transition 510 from the low state to the high state, for example from said second terminal voltage value 902 to said first value voltage of terminal 901.

[0035] At the same time, said output node 102 can be connected 515 to said first terminal 901 of said power supply 900 via said at least one first main circuit transistor 130, which is activated and begins to conduct 517 when a second NMOS transistor 109, which is included by said at least one pair of second auxiliary circuit transistors 107, connects said second main gate 152 to the second terminal 902 and thus deactivates said at least one second main circuit transistor 150, generally an NMOS transistor 150.

More precisely, a first NMOS transistor 105 connects said first main gate 132 to the current generator 160 and allows the controlled conduction of said at least one first main circuit transistor 130.

[0037] Indeed, by having a constant control voltage 525, said first main circuit transistors 130 provide a constant current at a load capacity 999 so as to produce a linear output voltage variation and therefore a constant current passes to through at least a first main capacity 120.

[0038] As soon as the voltage of said first terminal 901 of said electrical power supply 900 is reached 530, the current passing through at least a first main capacitor 120 begins to decrease until the currents are canceled and this makes it possible to resume the transition of said first main gate 132 and said at least one first main circuit transistor 130 is deactivated, since said input node 101 can pass 540 from the high state to the low state, for example said first terminal voltage value 901 to said second terminal voltage value 902 so as to connect said first main gate 132 to said first terminal 901 of said power supply 900.

[0039] At this moment, said process controlled by scanning speed 500 starts the second half-period of clock signal and said load capacitor 999 can be connected 545 between said output node 102 and said second terminal 902 of said power supply 900 via said at least one second main circuit transistor 150. As a result, said at least one second main circuit transistor 150 is activated and begins to conduct 547, when a first PMOS transistor 104, which is included by said at least one pair first auxiliary circuit transistors 103, connects said first main gate 132 to the first terminal 901 and thus deactivates said at least one first main circuit transistor 130.

More precisely, a second PMOS transistor 108 connects said second main gate 152 to the current generator 160 and thus allows the controlled conduction of said at least one second main circuit transistor 150.

[0041] Indeed, by having a constant control voltage 555, said second main circuit transistors 150 provide a constant current at a load capacity 999 so as to produce a linear output voltage variation and thus a constant current passes to through at least a second main capacity 140.

[0042] As soon as the voltage of said second terminal 902 of said electrical power supply 900 is reached 560, the current passing through at least a second main capacitor 140 begins to increase until the currents are canceled and this makes it possible to resume the transition of said second main gate 152 and said at least one second main circuit transistor 150 is deactivated, since said input node 101 can go 510 from the low state to the high state so as to connect said second main gate 152 to said second terminal 902 of said power supply 900.

[0043] Thus, the signal which varies between the voltage of said first terminal 901 of said electrical power supply 900, for example 3.3 V, and the voltage of said second terminal 902 of said electrical power supply 900, for example 0 V, at a controlled transition output slope to reduce electromagnetic interference and power supply noise, for example. Furthermore, the transition time ratio, i.e. rise time to fall time, and the differential output crossover voltage range between two slew rate controlled driver circuits operating in opposition, are perfectly orders.

[0044] In other words, when said clock signal input 101 can go 540 from the high state to the low state, the initial conditions can be: – said output node 102 can be equal to said first terminal voltage value 901; – said first main gate 132 can represent approximately 10% to 20% of said first terminal voltage value 901; and, – said second main gate 152 can be equal to said second terminal voltage value 902.

Said first PMOS transistor 104 connects said first main gate 132 to the first terminal 901 and thus deactivates said at least one first main circuit transistor 130.

Said second PMOS transistor 108 is activated and allows a pull-up current to charge said second main gate 152 and thus allows the controlled conduction of said at least one second main circuit transistor 150.

When said second main gate 152 exceeds the threshold voltage of said at least one second main circuit transistor 150, said output node 102 begins to fall by drawing a current, proportional to its downward slope, from said at least one second capacitor main 140. When this current reaches the value of the recall current of said at least one second current source 180, said second main gate 152 stops varying 555. Then, said output node 102 continues to fall at constant slope, whatever its load capacity 999. When said output node 102 reaches said second terminal voltage value 902, said second main gate 152 resumes its rise until said input node 101 passes from the low state in the high state.

[0048] Thus, said second NMOS transistor 109 connects said second main gate 152 to said second terminal 902, which deactivates said at least one second main circuit transistor 150, because a first NMOS transistor 105 has enabled the descent of said first main gate 132 to begin, the up transition of said output node 102 in the same way as the down transition of said output node 102 seen above.

[0049] Thus, the minimum slope, or the maximum transient time, is when the voltage of said first main gate 132 is flat 525 or when the voltage of said second main gate 152 is flat 555, which can be equal to half of the clock period. When said last transition time 535 of said first main gate 132 begins, that is to say after the voltage of said first terminal 901 of said power supply 900 is reached 530, the upward transition of said output node 102 is carried out 545, that is to say when said first terminal of said power supply is connected via said at least one first main circuit transistor. Consequently, said input node 101 can fall and start the next half-period 540. This means that said last transition time 535, last transition time of said first main gate 132, can be short, close to zero, which allows the maximum transition time to be quite close to half of the transition period. clock.

[0050] It is the same for said second main gate 152 and the last transition time 565. Indeed, as illustrated in Figure 2, said last transition time 565 of said second main gate 152 begins, that is that is to say after the voltage of said second terminal 902 of said power supply 900 is reached 560, the downward transition of said output node 102 is carried out 515, that is to say when said second terminal of said power supply is connected via said at least one second main circuit transistor. Therefore, said input node 101 can go up 510 and start the next half period. This means that said last transition time 565, last transition time of said second main gate 152, can be short, close to zero, which allows the maximum transition time to be quite close to half the period of clock.

[0051] In the case where there is only one capacitor, one of its electrodes is connected to the output node 102 and the other is switched between said first main gate 132 and said second main gate 152 to the transition 510, 540 of said input node 101, the last transition time 535 of said first main gate 132 can be sufficiently long so that the voltage at said first main gate 132 can reach said second terminal voltage value 902 and the last transition time 565 of said second main gate 152 can be long enough so that the voltage at said second main gate 152 can reach said first terminal voltage value 901.

[0052] Said charging capacity 999 is therefore always in the same initial condition which is a complete charge at the electrical supply voltage. This constraint limits the maximum transition time to less than a quarter of the clock period.

[0053] In this particular case, the maximum transient time must be less than a quarter of the clock period. Just after switching, the gate voltage of the main circuit which will control the next transition depends on the charge in the capacitor and the ratio between this capacitor and the capacitance of the gate of the main circuit. Since the gate capacitors of the two main drivers are not the same, the initial conditions of the two transitions are not the same. This will at least affect the crossover voltage. One solution may be to reduce this effect by having a much larger capacitor than the main circuit gate capacitors. However, the main disadvantage is the space required in the integrated circuit, in terms of surface area, compared to the present invention.

[0054] If in addition the initial gate voltage is greater than the threshold when regulating the slope, the main transistor will be too conductive at the start of the transition, producing a slope higher than the controlled slope, until that the loop reaches its target value. This will affect both the ratio of rise and fall time and crossover voltage.

[0055] Finally, the target transition time must be much smaller than half the clock period, the value of the capacitor must be much larger than the main circuit gate capacitors, a non-overlapping clock is necessary, and the conduction of the switches should not affect the performance, which is not the case in the present invention.

Claims (8)

1. Scan speed control circuit (100) of an integrated circuit; said slew rate control circuit (100) having an input node (101) and an output node (102); said slew rate control circuit (100) comprising at least one main circuit (110) connected to at least one current generator (160); said at least one main circuit (110) comprising: – at least one pair of first auxiliary circuit transistors (103) connected to said at least one current generator (160); – at least one first main capacity (120); said at least one first main capacitor (120) is configured to control an upward output slope; – at least one first main circuit transistor (130) having a first main source (131) connected to a first terminal (901) of a power supply, having a first main gate (132) connected to said at least one pair of first auxiliary circuit transistors (103), and having a first main drain (133) connected to said output node (102); said at least one first main capacitor (120) being connected between said first main gate (132) and said first main drain (133); – at least one pair of second auxiliary circuit transistors (107) operating in phase opposition and connected to said at least one current generator (160); – at least one second main capacity (140); said at least one second main capacitor (140) is configured to control a downward output slope; And, – at least one second main circuit transistor (150) having a first second source (151) connectable to a second terminal (902) of said power supply, having a second main gate (152) connected to said at least one pair of second auxiliary circuit transistors (107), and having a second main drain (153) connected to said output node (102); said at least one second main capacitor (140) being connected between said second main gate (152) and said second main drain (153). 2. A slew rate control circuit (100) according to claim 1, wherein said at least one pair of first auxiliary circuit transistors (103) comprises a first PMOS transistor (104) configured to connect said first main gate (132). ) to the first terminal (901) and to block the conduction of said at least one first main circuit transistor (130) and a first NMOS transistor (105) to connect said first main gate (132) to the current generator 160 and to allow the controlled conduction of said at least one first main circuit transistor (130) and/or said at least one pair of second auxiliary circuit transistors (107) comprises a second NMOS transistor (109) configured to connect said second main gate (152) to the second terminal (902) and to block the conduction of said at least one second main circuit transistor (150) and a second PMOS transistor (108) to connect said second main gate (152) to the current generator (160) and to allow the controlled conduction of said at least one second main circuit transistor (150). 3. Scan rate control circuit (100) according to claim 1 or 2, wherein said pair of first auxiliary circuit transistors (103) and/or said pair of second auxiliary circuit transistors (107) are connected to said node input (101). 4. Scan rate control circuit (100) according to any one of the preceding claims, wherein said first main circuit transistor (130) is a PMOS transistor (130) and/or said second main circuit transistor (150). ) is an NMOS transistor (150). 5. Scan speed control circuit (100) according to any one of the preceding claims, wherein said current generator (160) comprises at least a first current source (170) connected to at least a second current source (180): – said first current source (170) being connected to said second terminal (902) of said power supply and to said pair of first auxiliary circuit transistors (103); And, – said second current source (180) being connected to said first terminal (901) of said power supply (900) and to said pair of second auxiliary circuit transistors (107). 6. Scan speed control circuit (100) according to claim 5, wherein said at least one first current source (170) comprises a first current mirror (170), preferably comprising NMOS transistors, and/or said at least one second current source (180) comprises a second current mirror (180), preferably comprising PMOS transistors. 7. Scan speed control circuit (100) according to claim 6, in which: – said first current mirror (170) comprises a first cascode output (176, 177) made of a first NMOS cascode output (177) connected to said at least one pair of first auxiliary circuit transistors (103) and a second NMOS cascode output (176) connected to said second terminal (902) of said power supply, and an NMOS transistor connected as an input diode (171) having a first NMOS source (172) connected to said second terminal (902) of said power supply, a first NMOS drain (173) connected to a first NMOS gate (174), to a gate of said second NMOS cascode output (176) and preferably to a terminal of a first resistor (179); preferably, another terminal of said first resistor (179) is connected to a gate of said first NMOS cascode output (177) and to a terminal of a common resistor (190); And, – said second current mirror (180) comprises a second cascode output (186, 187) made of a first PMOS cascode output (187) to said at least one pair of first auxiliary circuit transistors (107) and a second PMOS cascode output (186) connected to said first terminal (901) of said power supply (900), a PMOS transistor connected as an input diode (181) having a first PMOS source (182) connected to said first terminal (901) of said power supply, a first PMOS drain (183) connected to a first PMOS gate (184), to a gate of said second PMOS cascode output (186) and preferably to a terminal of a second resistor (189); preferably, another terminal of said second resistor (189) is connected to a gate of said first PMOS cascode output (187) and to another terminal of a common resistor (190). 8. Method for controlling transition times for an input/output interface by means of a scan rate control circuit (100) according to any one of the preceding claims; said scan rate controlled method (500) comprising: – a transition (510, 540) of said input node (101) between said second terminal (902) of said power supply and said first terminal (901) of said power supply; – a connection (515, 545) of said output node (102) to said first terminal (901) of said power supply via said at least one first main circuit transistor (130) or said second terminal (902) of said power supply via said at least one second main circuit transistor (150); – an initiation of conduction (517, 547) of said at least one first main circuit transistor (130) or of said at least one second main circuit transistor (150); – by having a constant control voltage (525, 555), said main circuit transistors (130, 150) provide a constant current at a load capacitance (999) so as to produce a linear output voltage variation and therefore a constant current flow through at least one first main capacitor (120) or at least one second main capacitor (140); – by having the output node (102) reaching said second terminal (902) of said power supply or said first terminal (901) of said power supply and a current passing through the at least one first main capacitor (120) or the at least one second main capacitance (140) decreases until the currents are canceled and allow the transition of said first main gate (132) or said second main gate (152) to resume; – a connection of said first main gate (132) to said first terminal (901) of said power supply so as to deactivate said at least one first main circuit transistor (130) or said second main gate (152) to said second terminal (902) of said power supply so as to deactivate said at least one second main circuit transistor (150).