CA2746761A1

CA2746761A1 - Power converter apparatus and methods

Info

Publication number: CA2746761A1
Application number: CA2746761A
Authority: CA
Inventors: Robert Jay Hume; Barry F. Waltman; Stefan Jon Kristjansson; Jay Allen Kuehny; Yan Lu; Bertrand Nkei; Rodney Alan Hughes; Reid Adriance
Original assignee: Crane Electronics Inc
Current assignee: Crane Electronics Inc
Priority date: 2011-07-18
Filing date: 2011-07-18
Publication date: 2013-01-18

Abstract

A power converter provides current limit/current share functionality, allowing use in a point-of-load architecture and/or in parallel with one or more other power converters. Power converters are operable as masters or slaves, and include sense input and trim input terminals. Control may be based on output current sensed over only a portion of a duty cycle, with adequate compensation. A
swinging choke may be employed. A bias voltage supply very low input voltages to supply regulated current at higher voltages while inherently synchronizing to dynamic load demands. An oscillator may provide an ramp modulated by an external input.
Inrush current and over or under voltage conditions may be handled based on capacitively sensed input voltage.

Description

POWER CONVERTER APPARATUS AND METHODS
BACKGROUND

Technical Field This disclosure is generally related to power converters, and is more particularly related to regulated power converters.

Description of the Related Art Power converters are used to transform electrical energy, for example converting between alternating current (AC) and direct current (DC), adjusting (e.g., stepping up, stepping down) voltage levels and/or frequency.
Power converters take a large variety of forms. One of the most common forms is the switched-mode power converter or supply. Switched-mode power converters employ a switching regulator to efficiently convert voltage or current characteristics of electrical power. Switched-mode power converters typically employ storage components (e.g., inductor, transformer, capacitor) and switches that quickly switches between full ON and full OFF
states, minimizing power losses. Voltage regulation may be achieved by varying the translated power by modulating the ratio of ON to OFF time or duty cycle. Various topologies for switched-mode power converters are well known in the art including non-isolated and isolated topologies, for example boost converters, buck converters, synchronous buck converters, buck-boost converters, and fly-back converters, and others.
In the interest of efficiency, digital logic technology is employing ever lower voltage or potential logic levels. This requires power converters to deliver the lower voltages at higher current levels. To meet this requirement, power converters are employing more energy efficient designs. Power converters are also increasingly being located in close proximity to the load in as point of load (POL) converters in a POL scheme. These power converters must generate very low voltage levels (e.g., less than 1V) at increasingly higher current levels (e.g., greater than 10A). These relatively high current levels may be difficult to achieve with a single power converter.
Manufacturers are increasingly employing POL schemes in light of the widely varying voltage requirements in modern systems (e.g., computer systems). A POL scheme may be easier to design and/or fabricate, take up less area, and/or produce less interference than employing multiple different power buses. The POL schemes typically employ one or two power buses with a number of POL regulators located close to specific components or subsystems to be powered, for example microprocessors, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), volatile memory. The POL regulators adjust voltage or potential to supply localized busses feeding the specific components or subsystems.
Some attempts at addressing the requirement for high currents at low voltages or potentials employ power converters with current limiting and current sharing functions. Those power converters may be coupled in parallel to each provide a portion of the current drawn by the load.
New approaches to providing power converters which can satisfy the demands for high currents and low voltages or potentials in an energy efficient and cost effective manner are desirable.
Power converters which implement synchronous rectifiers to regulate the output voltage are susceptible to power inefficiencies caused by circulating currents during light and no load conditions. Circulating currents are currents that flow from the load back through the converter during light and no load conditions. The high side active switch of the synchronous rectifier compensates for the back flow of current when the high side active switch is turned ON. The current passes through lossy system components, e.g., traces and transistor channels, and dissipates power through the parasitic resistances in accordance with Pdissipation = 12Rparasitic= Thus, current circulating from the output back into the synchronous rectifier of a power converter results in an inefficient power loss.

New approaches to providing power converters which can improve the inefficiencies caused during light and no load conditions are desirable.
Many devices employ an auxiliary power or bias voltage power supply to provide supply voltages VCC, VSS. For example, switched mode power converters typically include an auxiliary power or bias voltage supply.
Existing approaches to auxiliary power or bias voltage supplies include those that generate unregulated voltages. Other existing approaches employ linear regulators or inefficient circuitry to provide regulated bias voltages. Existing approaches that generate unregulated bias supply voltages are generally not suitable for very low input voltage applications since the bias voltage that is generated is not high enough for most electronic circuitry.
Existing approaches that employ a linear regulator to generate a regulated bias voltage suffer from relatively high inefficiency due to the dissipation of energy through the regulating element (e.g., series pass element). Additionally, a linear regulator is typically not able to supply multiple output bias voltages.
Hence, multiple linear regulators are needed for applications that required multiple output bias voltages, adding substantial cost. These existing approaches also tend to have a somewhat limited operational temperature range.
For very or ultra low voltage inputs, an auxiliary power or bias voltage supply must generate a regulated voltage that is higher than the input voltage. It is also desirable that the auxiliary power or bias voltage supply operate efficiently throughout its voltage range, and be tolerant of dynamic load transients. It is also desirable that the auxiliary power or bias voltage supply operating frequency be compatible with the main supply. Further, an auxiliary power or bias voltage supply should also operate over a wide temperature range.
New approaches to auxiliary power or bias voltage supplies and the generation of bias supply voltages are desirable.

Many devices employ input capacitors. For example, switched mode power converters typically include a large internal bulk filter capacitor to filter the input power to reduce noise conducted out of the power converter 100, back upstream to the source of the input power. The input capacitor may also store and/or smooth input power.
However, upstream devices (e.g., power converters) may not be able to source or start up devices with large capacitances. Often times, upstream power converters are internally limited, and enter a "hiccup" mode or repeatedly restart when faced with a large capacitive load. Thus, various attempts have been made to design circuits which effectively limit inrush current.
Present approaches to controlling the capacitive inrush current of a device typically employ a series resistance or directly sensing the inrush current of the device through resistive sensing, magnetic sensing, or Hall effect sensing. These approaches to sensing the actual input current waveform lead to a substantial power loss, complicated designs, and/or high costs to address electrical isolation requirements, as well as slow transient response. For example, sensing an input current with a resistive element dissipates power and requires specific circuitry to amplify the sense signal and reduce common mode noise. Sensing with a magnetic element reduces power dissipation.
However, such an approach adds significant cost, requires added circuitry to amplify the signal, and is only applicable in AC current sensing applications.
Thus, this approach is only useful for very high AC current applications. Due to their low sensitivity Hall effect sensors likewise require added circuitry to amplify the signal and to reduce common mode noise.
Thus, the various approaches require a number of tradeoffs due to design issues. For example, approaches which employ a permanently placed resistor to limit inrush current suffer from a substantial decrease in efficiency. It is typically difficult to derive an accurate input current signal without degrading the overall efficiency. Signal integrity degradation resulting from common mode noise/current is also a problem. Additionally, a voltage shift of the signal down to the electrical circuit ground potential may occur in some designs. Further, many approaches have had difficulty in maintaining fast transient response.
Additionally, many applications require that voltage be maintained within an acceptable range. Thus, under voltage and over voltage conditions must be monitored and handled.
New approaches to handling inrush current, under voltage and over voltage monitoring are desirable.
Switched mode power converters typically include an oscillator or oscillator circuit which generates, provides or supplies a periodic, oscillating ramp voltage waveform to a gate timing and drive control for use in generating pulse width modulated control signals for controlling one or more switches of the converter circuit. It is desirable that the oscillator provide a linear ramp signal with ramp voltage rate of change (dv/dt) rate proportional to the supply input voltage while maintaining a fixed frequency over a wide range of frequencies and over a wide range of temperatures. Additionally, the oscillator may need to be synchronized with other oscillating waveforms and other frequencies, for example those from a system clock or another power converter. Further, it is typically desirable that the oscillator is relatively inexpensive to manufacture.
New approaches related to oscillation circuits are desirable.
BRIEF SUMMARY

Existing approaches for controlling an output current of a power converter to accomplish current limiting and to force multiple power converters to share the output load current are not as efficient as might otherwise be desired. Typically, existing power converts require sensing of a complete current waveform of the output current of the power converter. There are numerous approaches to sensing the complete output current of the power converter. For example, a typical approach to deriving an output current signal is to sense the current in the output current path. Current sensing may be accomplished by various sensors, for instance resistive, magnetic and Hall effect sensors. These approaches are associated with significant issues, for instance lower sensitivity, lower efficiency, and the need for high common mode rejection due to the wide (e.g., 4:1) range of the output voltage or potential.
Additionally, there are a variety of problems in implementing a current limit/current share function in a power converter. For example, deriving an accurate output current signal without severely impacting the efficiency of the converter. Also for example, signal integrity degradation of the signal resulting from common mode noise/current. As a further example, voltage level shift degradation may occur. Further problems may include difficult to predict current limit level and/or difficulty in obtaining accurate sharing of the load current in a parallel current share mode configuration.
Further, existing approaches tend to be relatively complex, require a large number of parts, and/or may be less efficient than the approaches described herein.
Some of the approaches described here may implement current limit and current sharing functions in a power converter with higher efficiency, lower parts count, and/or greater flexibility in selecting the current limit level than existing approaches.
Some of the approaches described herein utilize an average current mode control methodology and structure to allow accurate control of the output current of a power converter. This allows for paralleling of power converters, with each converter sharing the total output power delivered to the load. This may provide more flexibility in application of the power converters.
Some of the approaches described herein uses a unique combination of sensing only a portion of the total output current referenced to the converter ground with a compensation for a variance of the sensed current signal over the range of duty cycle operation of the power converter. Thus, the current limit and current sharing functionality of a power converter may be achieved with a higher efficiency than possible with existing approaches.
Advantageously, the current sensing is referenced to the ground reference of the circuit, significantly reducing the complexity of deriving a signal representative of the output current of the power converter. The derived current sense signal may be compensated for changes in duty cycle with a signal that is a function of 1-D (i.e., one minus duty cycle) of the power converter.
Some of the approaches described herein provide a POL power converter design that facilitates the ability to parallel individual power converters, each power converter providing a portion of the total output load current. Two or more power converters may be operated in a current sharing mode, to supply the current draw of a commonly coupled component or subsystem.
The high degree of accuracy of the current share function with this implementation is achieved by utilization of average current mode control. As compared to existing approaches, the approach described herein may advantageously provide one or more of: 1) current limiting function to protect the converter from a load fault condition; 2) current sharing function using average current mode control to generate higher output currents; 3) higher efficiency; 4) lower component count; and/or 5) flexibility in selecting the current limit level.
An existing approach for regulating the output voltage of a buck converter at light and no load conditions when implemented with a lowside switch as a Schottky diode is to replace the output inductor with a swinging choke. This approach is capable of supplying current at light load conditions by allowing the inductance to increase as load decreases and thus maintain forward conduction down to lighter loads. Applicants have recognized that this approach eventually requires the high side transistor to pulse skip or completely shut off to maintain output regulation otherwise at a critical light load constant conduction will become discontinuous. The common solution of pulse skipping or shutting off the converter causes negative side-effects such as increased electro-magnetic interference (EMI) and reduced load range. Applicants have also recognized that this approach may require extra sensing circuitry to determine when discontinuous conduction mode is reached. Additionally, this approach is less efficient than using a low side active switch because more power is dissipated in a forward biased diode than in a low side active switch during normal operating conditions. In particular, power dissipating in the diode is determined by the voltage drop clamped across the forward-biased diode multiplied by the current flowing through the diode (P=I"Vdiode). In contrast, the power dissipated in the low side active switch is determined by the square of the current flowing through the switch multiplied by the channel resistance Rds.
Another existing approach includes preloading an output inductor of a power converter with a resistor. Applicants have recognized that at light loads the resistor may continue to provide a discharge path for the current supplied to the output inductor, allowing lighter load continuous conduction at the expense of greater power loss and thus lower efficiency, especially at light and no load conditions.
The use of synchronous rectification for low output voltage converters does not suffer the same problem of the inductor current becoming discontinuous at light and no load conditions because the low side active switch does not clamp the inductor at a specific voltage. Instead, reversed circulating currents in the inductor are allowed to flow which unlike a diode clamp do not disrupt converter stability and are thus commonly ignored but these currents do lead to inefficiencies at light and no load conditions.
An approach described here results in a power converter with higher efficiency at light and no load conditions than existing approaches.
At least one approach described herein utilizes the varying inductance of a swinging choke with a synchronous rectifier to reduce the effects of circulating currents that arise during light and no load conditions, i.e_, as the current demands at the load approach zero.
Described herein are approaches to generating regulated bias supply voltages useful in powering internal circuitry of a device that operates to a very low input voltage with a wide temperature range. The described approaches employ a step up switch mode DC/DC power converter to very efficiently step up a very or ultra low input voltage to generate or supply a regulated bias supply voltages. The step up switch mode DC/DC power converter may advantageously provide multiple regulated output voltages, which may be of both "+" and "-" polarities. The step up switch mode DC/DC
power converter provides such low input voltage (e.g., less than 2V), and operates over a wide range of input voltage. The step up switch mode DC/DC
power converter may advantageously operate over a wide temperature range.
Use of the step up switch mode DC/DC converter topology advantageously allows parts count to be kept low, and allows a compact volume to be achieved.
The approaches described here allow the auxiliary power supply or bias voltage supply to synchronize to a dynamic load, while also reducing switching interaction with the main converter over at least some existing approaches.
While described herein in terms of a regulated bias supply for use in power converters, the approaches described herein may be utilized in any device that is required to operate in similar situations. The regulated bias supply described herein could be sold as a standalone device.
Some of the control circuits described herein may effectively accomplish inrush current limiting. Such allows for predictable startup of a converter from bus sources that may themselves be current limited during the source startup. Inrush current limiting also protects relatively large input or filter capacitors from damage at startup. Such may improve reliability for circuit designs that require a high capacitance density in order to meet stringent noise specifications. Establishing a low and predictable inrush current can advantageously prevent occurrence of power-on reset events or non-monotonic startup from a current-limited or protected source.
The inrush current limiting may advantageously limit the inrush current into a bulk capacitance of a device during the initial power up of a device or during voltage transients without the need to directly sense the input current of the device. Instead, the inrush current limiting may be based on a signal that is proportional to the input current of the device.
Such may be particularly useful in power converters that have a large internal bulk filter capacitor. Power converter requirements continue to evolve toward higher efficiency and minimizing the number external parts needed. In the case of a switch mode power converter, incorporating bulk capacitive filtering of the input power internal to the power converter reduces noise conducted out of the power converter back into the source.
Controlling the inrush current to a device (e.g., power converter) capacitance reduces electrical stresses on the device, and on the any system employing the device.
Some of the approaches described herein may have a number of benefits over existing approaches. For example, the approaches described herein may effectively limit inrush current without directly sensing the input current, resulting in overall higher efficiency. In particular, the approaches described herein may effectively limit inrush current based on a signal that is a mirror or representation of actual input current. The signal may advantageously be inherently referenced to a ground return of the circuit, dramatically reducing isolation requirements. By basing the inrush current control on a signal that is much smaller proportion of the actual inrush current, faster transient response to changes in the initial start up conditions or transient conditions can be achieved. The approaches described herein can implement inrush current limiting without an intrusive current measurement implementation, simplifying the circuit design and reducing cost. The approaches described herein may enable the reliable use of high-capacitance-density devices in the input filter of a power converter or other device. Further, the approaches described herein may use common elements to accomplish four different functions: inrush current limiting, under voltage lockout, remote enable, and over voltage lockup, using less complicated and less costly circuitry than prior approaches. Since only a small current proportional to the total capacitive inrush current is sensed to monitor the total input current, higher efficiency, faster transient response , lower circuit complexity and lower cost can be achieved than with existing solutions. Lower parts count and lower cost result from the shared circuitry.
A
series switch or series pass device as the primary component to accomplish the four functions allows for protection of downstream circuitry and monitoring a state of the converter, whether delivering power or OFF. The approaches described herein are not limited to power converters.
Some of the approaches described herein to generate a periodic ramp oscillator signal may advantageously provide one or more of.. 1) the oscillator is self oscillating and requires no start up input; 2) the slope of the ramp is modulated by an external signal and is linear over a wide range of operating conditions of input signal range and temperature; 3) the oscillator signal output can be synchronized to an external clock signal input; 4) the oscillator signal output synchronizes to the external signal input up to two times the self oscillation frequency of the oscillator; and/or 5) method uses less complex, lower cost discrete semiconductor components, chip resistors and capacitors.
In contrast, existing approaches utilize more costly and complex integrated circuit devices, such as comparators/operational amplifiers with additional components or a custom designed complex integrated circuit.
Existing approaches appear to lack all the features described above. Existing approaches also appear to fail to operate over an ultra wide synchronous frequency range and temperature range as desired, with external slope modulation of the ramp oscillator signal. Existing approaches use terrestrial technology.
A method of operating a first switch mode power converter having a synchronous buck converter circuit that includes a transformer having a swinging choke, a high side active switch operable to selectively coupled a portion of the transformer to an input terminal and a low side active switch operable to selectively couple the portion of the transformer to a ground reference, may be summarized as including sensing an output current of the synchronous buck converter circuit with reference to the ground reference of the synchronous buck converter circuit over only a portion of a waveform of the output current; compensating a sensed current signal that is proportional to the sensed output current at least for any variation in a duty cycle of a portion of the synchronous buck converter circuit of the first switch mode power converter;

averaging a signal that is at least proportional to a compensated sensed current signal to produce an averaged signal; during a first portion of a cycle causing the high side active switch to electrically pass current from the input terminal to an output terminal through the swinging choke to vary an inductance of the swinging choke; and during a second portion of the cycle causing the low side active switch to electrically pass current through the swinging choke to the ground reference, wherein an inductance of the swinging choke varies over the cycle.
The method may further include level shifting the compensated sensed current signal to produce a level shifted compensated sensed current signal, wherein averaging a signal that is at least proportional to the compensated sensed current signal includes averaging the level shifted compensated sensed current signal. Sensing an output current with reference to a ground reference of the synchronous buck converter circuit over only a portion of a waveform of the output current may include sensing the output current with reference to the ground at the low side active switch. The swinging choke may include a first core piece and a second core piece and at least one winding, a portion of the first core piece separated from a portion of the second core piece by a stepped gap therebetween. The method may further include determining a compensation signal that is a direct function of the duty cycle of the portion of the synchronous buck converter circuit; scaling the compensation signal; and wherein compensating a sensed current signal that is proportional to the sensed output current at least for any variation in a duty cycle of the synchronous buck converter circuit may include summing a scaled compensation signal with the sensed current signal that is at least proportional to the sensed output current. The duty cycle may be the duty cycle of a high side switch of the circuit and scaling the compensation signal may include scaling the compensation signal to account for a difference between the duty cycle of the high side switch and a low side switch duty cycle of the low side switch of the synchronous buck converter circuit. The method may further include sensing an output voltage or potential of the synchronous buck converter circuit; producing a voltage error signal indicative of an error between the sensed voltage and a reference voltage; and controlling the synchronous buck converter circuit based at least in part on the voltage error signal. The method may further include capacitively producing a signal proportional to an input current; mirroring the signal proportional to input current; and adjusting a flow of the input current in response at least to the signal that is proportional to the input current to control an inrush current. Capacitively producing a signal proportional to input current may include allowing a sense capacitor coupled in parallel with an input filter capacitor between an input line and a ground to be charged by the input current and adjusting a flow of the input current may include supplying a signal from a clamp circuit to a series pass device electrically coupled in series in an input line between the input terminal and the high side active switch. The method may further include detecting at least one of an over voltage condition or an under voltage condition on the input line;
and in response to detecting at least one of the over voltage condition or the under voltage condition on the input line providing a signal to the clamp circuit that causes the series pass device to stop the flow of the input current. The method may further include detecting an enable signal indicative of a selected one of two states; in response to detecting the enable single of a first one of the two states providing a signal that causes the series pass device to stop the flow of the input current; and in response to detecting the enable single of a second one of the two states providing a signal that causes an under voltage lockout monitor circuit to function. The power converter may include an auxiliary voltage supply to supply a VCC supply potential and a VSS supply potential, the auxiliary voltage supply comprising an auxiliary transformer having at least a first winding, a second winding and a core; an auxiliary converter switch operable to selectively couple the first winding to a ground reference node; a drive capacitance coupled to drive the converter switch; and a synchronization capacitance, the method may further include increasing a supply of current via the auxiliary converter switch to the first winding of the auxiliary transformer; in response to an increase in current flow through the first winding via the auxiliary converter switch, reflecting a corresponding voltage change by the first winding to the second winding ; increasing a drive voltage to turn the auxiliary converter switch full ON in response to the reflection of the voltage change corresponding to the increase in current flow through the first winding ; decreasing the supply of current via the auxiliary converter switch to the first winding of the auxiliary transformer; in response to the decrease in current flow through the first winding via the auxiliary converter switch, reflecting a corresponding voltage change by the first winding to the second winding ; decreasing a drive voltage to turn the auxiliary converter switch OFF in response to the reflection of the voltage change corresponding to the decrease in current flow through the first winding ; in response to a dynamic load current demand larger than a threshold, providing a voltage pulse to the first winding by the synchronization capacitance; reflecting the voltage pulse by the first winding to the second winding ; and applying the voltage pulse via the second winding to turn the auxiliary converter switch ON to synchronize a cycle of the bias voltage supply.
The method may further include determining a time averaged difference of a sum of the VCC supply potential and a reference potential; and applying a signal to the second winding based on the determined time averaged difference. The method may further include driving a charge pump coupled to the first winding of the auxiliary transformer to supply the VSS supply potential.
The method may further include receiving an input voltage signal at the input terminal; receiving a synchronizing signal at a synchronizing signal input terminal; charging a ramp timing capacitor via the input voltage signal through a ramp timing resistance; producing a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal; in response to a value of a voltage across the ramp timing capacitor being equal to the discharge trigger reference voltage, discharging the ramp timing capacitor if a state of the synchronization signal indicates synchronization and delaying discharging of the ramp timing capacitor if the state of the synchronization signal does not indicate synchronization; and in response to the state of the synchronization signal indicating synchronization while the voltage across the ramp timing capacitor is less than the discharge trigger reference voltage, discharging the ramp timing capacitor. Comparing the voltage across the ramp timing capacitor to the discharge trigger reference voltage may include supplying the discharge trigger reference voltage to a first transistor of a differential pair of transistors and supplying the voltage across the ramp timing capacitor to a second transistor of the differential pair of transistors. The method may further include determining whether to trigger discharging of the ramp timing capacitor when the value of a voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage. Determining whether to trigger discharging of the ramp timing capacitor when the value of a voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage may include supplying the synchronization signal to a logic network comprising a synchronization capacitor, a first synchronization diode and a second synchronization diode, triggering the discharging of the ramp timing capacitor via the first synchronization diode in response to a first synchronization state and suppressing triggering of the discharging of the ramp timing capacitor via the second synchronization diode in response to a second synchronization state. The method may further include buffering an output voltage signal via an emitter follower buffer amplifier having a discrete transistor and resistor.
A first switch mode power converter may be summarized as including a converter circuit including at least one inductor wound on a swinging choke and at least a first active switch; an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current; a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the first active switch of the converter circuit; a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal; and a drive controller coupled to the current control amplifier to receive the averaged signal and is coupled to drive at least the first active switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier.
The compensation circuit level may shift the compensated sensed current signal, and the current control amplifier may be coupled to receive a level shifted compensated sensed current signal from the compensation circuit.
The first active switch may be a high side switch and the converter circuit may include at least a second active switch which is a low side switch, and wherein the output current sensor may sense the output current with reference to the ground on a low side of the low side active switch. The compensation circuit may be coupled to receive a signal indicative of a duty cycle of the high side switch and may determine a compensation signal that is a direct function of the duty cycle of the high side switch, may scale the compensation signal, and may sum the scaled compensation signal with the sensed current signal. The compensation circuit may scale the compensation signal to account for a voltage level offset. The first switch mode power converter may further include a voltage error amplifier coupled to receive a signal indicative of an output voltage of the converter circuit and a signal indicative of at least a reference voltage, the voltage error amplifier operable to provide a voltage error signal indicative of an error between the output voltage and the reference voltage to the current control amplifier. The compensation circuit may include a switch that selectively couples an input of the current control amplifier between an output of the voltage error amplifier and a shared line that is coupleable to receive a voltage input from a second switch mode power converter to operate the first and the second switch mode power converters in a current sharing mode to supply current in parallel to a common load. The compensation circuit may include a common emitter stage that drives a shared line that is selectively coupleable to receive a voltage input from a second switch mode power converter to operate the first and the second switch mode power converters in a current sharing mode to supply a common load. The first switch mode power converter may further include a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line; a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current; a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line. The current sense mirror may include a first mirror transistor coupled to the ground reference through a first mirror resistor and a second mirror transistor coupled to the ground reference through a second mirror resistor, a base of the first mirror transistor and a base of the second mirror transistor commonly coupled to the sense capacitor to maintain a constant inrush charge current to the input filter capacitor. The first switch mode power converter may further include a pair of trickle bias resistors electrically coupled between the input line and a source of the first mirror transistor of the current sense mirror. The first switch mode power converter may further include an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.
The over voltage lockout monitor circuit may include a pair of over voltage lockout resistors coupled as a voltage divider between the input line and the ground reference via an over voltage lockout Zener diode which is coupled to drive a switch controlling transistor which is in turn coupled to control the series switch. The over voltage lockout monitor circuit may further include a low impedance charge path formed by a speedup diode and a speedup resistor electrically coupled between the input line and the base of the transistor.
The first switch mode power converter may further include an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line. The under voltage lockout monitor circuit may include an under voltage lockout comparator that has a first input and a second input, the first input coupled to the input line via a first under voltage lockout resistor and the second input coupled to a voltage reference source via a second under voltage lockout resistor. The first switch mode power converter may further include an enable monitor circuit operable in response to an enable single to provide control signals to cause the series switch to stop the flow of the input current along the input line. The first switch mode power converter may further include an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit; an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit; an enable monitor circuit operable in response to an enable single to provide control signals to the clamp circuit indicative of a disable state, and wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit, the under voltage lockout monitor circuit, and the enable monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line in response to a signal indicative of the over voltage condition, the under voltage condition, or a disable state. The sense capacitor may have a capacitance that is less than a capacitance of the input filter. The first switch mode power converter may further include an auxiliary bias voltage supply to supply a VCC supply potential and a VSS supply potential, the auxiliary bias voltage supply comprising: an auxiliary transformer having at least a first winding , a second winding and a core, the first winding coupled at a first node to receive an input at a first input potential and coupled at a second node to provide a first output potential and a second output potential with an output voltage which is higher than an input voltage supplied to the first switch mode power converter, and also including an auxiliary converter switch operable to selectively couple the second node of the first winding to a ground reference node; an error circuit coupled to control the auxiliary converter switch through the second winding of the auxiliary transformer based at least in part on a difference between the first output potential and a reference potential; and a synchronization capacitance electrically coupled in parallel with the diode between the first winding and the VCC output node that in response to a dynamic load condition provides a signal that is reflected by the first winding across the auxiliary transformer to the first winding to drive the auxiliary converter switch to synchronize operation with a periodic load demand. The synchronization capacitance of the auxiliary bias voltage supply may be supplied at least in part by a parasitic capacitance of an output diode electrically coupled between the second node of the first winding and a VCC output node and at least in part by a substrate capacitive coupling.
The error circuit of the auxiliary bias voltage supply may include an error amplifier that sums the first output potential and the reference potential and produces a time average of a difference between the first output potential and the reference potential. The error circuit of the auxiliary bias voltage supply may include a current mirror coupled to reflect an output of the error amplifier to the second winding of the auxiliary transformer. The auxiliary bias voltage supply may further include a charge pump coupled to the second node of the first winding of the auxiliary transformer to supply the second output potential.
The auxiliary bias voltage supply may further include an over voltage clamp circuit coupled to turn OFF the auxiliary converter switch in response to a transient condition in at least one of the first input potential or the first output potential. The first switch mode power converter may further include an oscillator, the oscillator including a voltage input terminal to receive an input voltage signal; a synchronizing signal input terminal to receive a synchronizing signal; a ramp timing resistance; a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance; an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal; a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage; and a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor. The input voltage resistor divider network of the oscillator includes a first divider resistor, a second divider resistor, and a temperature compensation resistor to compensate the discharge trigger reference voltage for temperature variation, the input voltage resistor network coupled to provide the discharge trigger reference voltage the comparator. The comparator of the oscillator may include a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors, with a base of the first comparator transistor coupled as an inverting input to the input voltage resistor divider network to receive the discharge trigger reference voltage and a base of the second comparator transistor coupled as a non-inverting input to the ramp timing capacitor to receive the voltage across the ramp timing capacitor. The comparator of the oscillator may include a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors. The oscillator may further include a control transistor; a discharge controlling capacitor; and a discharge termination transistor; a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor to a ground reference node. The logic circuit of the oscillator may include a synchronization capacitor coupled to the synchronization input terminal to receive the synchronization signal, a first diode coupled to cause the control transistor to be in a first state in response to a first state of the synchronization signal and a second diode coupled to the control transistor to cause the control transistor to be in a second state in response to a second state of the synchronization signal. The oscillator may further include a level shifting diode electrically coupling a control transistor resistor to a ground to level shift the control transistor resistor reducing a voltage required to turn on the control transistor. The oscillator may further include a buffer transistor; and a buffer resistor, the buffer transistor and buffer resistor coupled to form an emitter follower buffer amplifier between a voltage supply and a ground to provide a low source impedance driver.
A switch mode power converter may be summarized as including a converter circuit which may include at least one inductor and at least one converter switch operable to selectively coupled the at least one inductor to a ground reference and a drive controller coupled to control the at least one converter switch; an auxiliary voltage supply to supply a VCC supply potential and a VSS supply potential which may include an auxiliary transformer having at least a first winding, a second winding and a core; an auxiliary converter switch operable to selectively couple the first winding of the auxiliary transformer to a ground reference; a drive capacitance coupled to drive the auxiliary converter switch; and a synchronization capacitance, wherein the auxiliary transformer, the auxiliary converter switch and the drive capacitance are coupled in a positive feedback loop such that as a current flow through the first winding via the auxiliary converter switch increases, the first winding reflects a corresponding voltage change to the second winding that increases a drive voltage to turn the auxiliary converter switch full ON and as current flow through the first winding via the auxiliary converter switch decreases, the first winding reflects a corresponding voltage change to the second winding that decreases the drive voltage to turn the auxiliary converter switch full OFF;
and wherein the auxiliary transformer, the auxiliary converter switch and the synchronization capacitance are coupled such that in response to a dynamic load current demand larger than a threshold the first winding reflects a voltage pulse to the second winding to turn the auxiliary converter switch ON to synchronize a cycle of the bias voltage supply; and an oscillator which may include a voltage input terminal to receive an input voltage signal; a synchronizing signal input terminal to receive a synchronizing signal; a ramp timing resistance; a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance; an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal; a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage; and a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor.
The synchronization capacitance of the auxiliary voltage supply may be supplied at least in part by a parasitic capacitance of an output diode electrically coupled between the first winding of the auxiliary transformer and a VCC output node and may be supplied at least in part by a parasitic substrate capacitive coupling. The auxiliary voltage supply may further include an error circuit coupled to control the auxiliary converter switch through the first winding of the auxiliary transformer based at least in part on a difference between an output voltage and a reference voltage. The error circuit of the auxiliary voltage supply may produce a time averaged difference of the sum of the VCC supply potential and a reference potential. The comparator of the oscillator may include a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors, with a base of the first comparator transistor coupled as an inverting input to the input voltage resistor divider network to receive the discharge trigger reference voltage and a base of the second comparator transistor coupled as a non-inverting input to the ramp timing capacitor to receive the voltage across the ramp timing capacitor. The oscillator may further include a control transistor; a discharge controlling capacitor; a discharge termination transistor and a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor. The logic circuit of the oscillator may include a synchronization capacitor coupled to the synchronization input terminal to receive the synchronization signal, a first diode coupled to cause the control transistor to be in a first state in response to a first state of the synchronization signal and a second diode coupled to the control transistor to cause the control transistor to be in a second state in response to a second state of the synchronization signal. The oscillator may further include a level shifting diode electrically coupling a control transistor resistor to a ground to level shift the control transistor resistor reducing a voltage required to turn on the control transistor. The switch mode power converter may further include an input control circuit that controls inrush current, the input control circuit comprising: a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line; a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current; a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line. The current sense mirror may include a first mirror transistor coupled to the ground reference through a first mirror resistor and a second mirror transistor coupled to the ground reference through a second mirror resistor, a base of the first mirror transistor and a base of the second mirror transistor commonly coupled to the sense capacitor to maintain a constant inrush charge current to the input filter capacitor. The input control circuit may further include an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line. The input control circuit may further include an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line. The switch mode power converter may further include an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current; a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the first active switch of the converter circuit; a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal; and wherein the drive controller is coupled to the current control amplifier to receive the averaged signal and is coupled to drive at least the first active switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier. The compensation circuit level may shift the compensated sensed current signal, and the current control amplifier is coupled to receive a level shifted compensated sensed current signal from the compensation circuit. The at least one converter switch may include a high side switch and a low side switch, and wherein the output current sensor may sense the output current with reference to a ground coupling of the low side active switch. The at least one inductor may include a first winding or primary associated with a swinging choke.

A switch mode power converter may be summarized as including a converter circuit including at least one inductor and at least one converter switch; an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current; a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the converter circuit; a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal; and a drive controller coupled to the current control amplifier to receive the averaged signal and is coupled to drive the at least one converter switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier; a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line to the at least one inductor of the converter circuit; a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current; a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line.
The switch mode power converter may further include an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line. The switch mode power converter may further include an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line. The compensation circuit level may shift the compensated sensed current signal, and the current control amplifier may be coupled to receive a level shifted compensated sensed current signal from the compensation circuit. The compensation circuit may be coupled to receive a signal indicative of a duty cycle of a high side switch and determines a compensation signal that is a direct function of the duty cycle of the high side switch, scales the compensation signal, and sums the scaled compensation signal with the sensed current signal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not intended to convey any information regarding the actual shape of the particular elements, and have been solely selected for ease of recognition in the drawings.
Figure 1 is a schematic diagram of a power converter including an inner current loop and an outer voltage loop thereof, according to one illustrated embodiment.
Figure 2 is a detailed electrical schematic diagram of the inner current loop and the outer voltage loop illustrated in Figure 1, according to one illustrated embodiment.
Figure 3 is a detailed electrical schematic diagram of the inner current loop and the outer voltage loop illustrated in Figure 1, according to another illustrated embodiment.

Figure 4 is a schematic diagram of a number of power converters of Figure 1 arranged as point-of-load devices, according to one illustrated embodiment.
Figure 5 is a schematic diagram of a number of power converters of Figure 1 arranged to operate in a current sharing mode with respect to a common load, according to one illustrated embodiment.
Figure 6 is a flow diagram of a method of operating the power converter of Figures 1-3, according to one illustrated embodiment.
Figure 7 is a flow diagram of a method of operating the power converter of Figures 1-3, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 6.
Figures 8A-8C are simplified drawings of swinging choke cores, according to the illustrated embodiments.
Figure 9A is a flow diagram of a method of operating the power converters of Figure 1, according to one illustrated embodiment.
Figure 9B is a flow diagram of an additional method that may be performed as part of the method Figure 9A, according to one illustrated embodiment.
Figure 10 is a functional block diagram of the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figure 1, according to one illustrated embodiment.
Figure 11 is a detailed electrical schematic diagram of the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figures 1 and 11, according to one illustrated embodiment.
Figure 12 is a functional block diagram of the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figure 1, according to one illustrated embodiment.
Figure 13 is a detailed electrical schematic diagram of the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figure 1 and 12, according to one illustrated embodiment.

Figure 14 shows a method of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figures 1, 10-13, according to one illustrated embodiment.
Figure 15 shows a method of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figures 1, 10-13, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 14.
Figure 16 shows a method of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply of Figures 1, 10-13, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 14.

Figure 17 is a functional block diagram of the input control circuit of Figure 1 to control a current flow on an input line, according to one illustrated embodiment.

Figure 18 is a detailed electrical schematic diagram of the input control circuit of Figures 1 and 17, according to one illustrated embodiment.
Figure 19 is a flow diagram of a method of operating the input control circuit of Figures 1, 17-18, according to one illustrated embodiment.
Figure 20 is a flow diagram of a method of operating the input control circuit of Figures 1, 17-18, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 19.
Figure 21 is a functional block diagram of the oscillator circuit of Figure 1, according to one illustrated embodiment.
Figure 22 is a detailed electrical schematic diagram of the oscillator circuit of Figures 1 and 21, according to one illustrated embodiment.
Figure 23 is a flow diagram of a method of operating the oscillator circuit of Figures 1, 21-22, according to one illustrated embodiment.
Figure 24 is a flow diagram of a method of operating the oscillator circuit of Figures 1, 21-22, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 23.

Figure 25 is a flow diagram of a method of operating the oscillator circuit of Figures 1, 21-22, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 23.
Figure 26 is a flow diagram of a method of operating the oscillator circuit of Figures 1, 21-22, according to one illustrated embodiment, which may be implemented as part of performing the method of Figure 23.

DETAILED DESCRIPTION

In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed embodiments.
However, one skilled in the relevant art will recognize that embodiments may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with power conversion topologies have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the embodiments.
Unless the context requires otherwise, throughout the specification and claims which follow, the word "comprise" and variations thereof, such as, "comprises" and "comprising" are to be construed in an open, inclusive sense, that is as "including, but not limited to."
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.
As used in the specification and the appended claims, references are made to a "node" or "nodes." It is understood that a node may be a pad, a pin, a junction, a connector, a wire, or any other point recognizable by one of ordinary skill in the art as being suitable for making an electrical connection within an integrated circuit, on a circuit board, in a chassis or the like.
The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.
Figure 1 shows a power converter 100, according to one illustrated embodiment. The description of Figure 1 provides an overview of the structure and operation of the power converter 100, which structure and operation are described in further detail with reference to Figures 2-7.
The power converter 100 may, for example, take the form of a DC/DC power converter to convert (e.g., raise, lower) DC voltages. The power converter 100 may, for example, include an output inductor Lout electrically coupled to an output terminal +VOUT, a first active switch (i.e., high side active switch) T1 selectively operable to electrically couple the inductor Lout to a voltage input terminal VIN. A second device T2 electrically couples the output inductor Lout to a ground GND which is in turn electrically coupled to a ground or common input terminal VIN COM and a ground or common output terminal VOUT COM.
As illustrated, the power converter 100 may advantageously take the form of a synchronous buck converter, operable to lower a DC voltage.
Where implemented as a synchronous buck converter, the second device T2 takes the form of a second active switch (i.e., high side active switch), selectively operable to electrically couple the output inductor Lout to ground GND. The power converter 100 may take forms other than a synchronous buck converter, for example a buck converter where the second device takes the form of a passive device, such as a diode (not shown).

The switches T1, T2 may take a variety of forms suitable for handling expected currents, voltages and/or power. For example, the switches T1, T2 make take the form of an active device, such as one or more metal oxide semiconductor field effect transistors (MOSFETs). As illustrated in the Figures, the first or high side switch T1 may take the form of P-Channel MOSFET, while the second or low side switch T2 make take the form of an N-Channel MOSFET. The output inductor Lout may be coupled via a node 102 to the drains D1, D2 of the MOSFET switches T1, T2 respectively. The power converter 100 may employ other types of switches, for example insulated gate bipolar transistors (IGBTs). While only one respective MOSFET is illustrated, each of the first and/or second switches T1, T2 may include two or more transistors electrically coupled in parallel.
The power converter 100 may include an output capacitor Cout electrically coupled between ground GND and a node 104 between the output inductor Lout and the output terminal +VOUT. Output capacitor Cout may smooth the output supplied to the output terminal +VOUT.
On an input side, the power converter 100 may include an auxiliary power supply and voltage reference generation block 106, an over voltage/under voltage monitor block 108 and/or an "inrush" current control block 110.
The auxiliary power supply and voltage reference generation block 106 implements a house keeping supply generation function, amplifier bias generation function and precision reference generation function, resulting in a positive supply voltage or potential VCC, a negative supply voltage or potential or ground VSS, and a precision reference voltage or potential VREF.
The over voltage/under voltage monitor block 108 monitors instances of over voltage and/or under voltage conditions, supplying a control signal via a control line (not called out in Figure 1) to the "inrush" current control block 110 as needed. The over voltage/under voltage monitor block 108 or other components may be triggered via an enable signal via an enable input terminal ENABLE. The "inrush" current control block 110 controls "inrush"

current, directly limiting current to input capacitor(s) Cin, reducing electrical stresses on the power converter 100 and any system into which the power converter 100 is incorporated. Power converters 100 typically employ large internal bulk filter capacitors to filter the input power to reduce noise conducted out of the power converter 100, back upstream to the source of the input power.
The input capacitor Cin is electrically coupled between ground GND and a node 111 between the "inrush" current control block 110 and the first active switch T1. The "inrush" current control block 110 is configured to control the "inrush"
current that flows to the input capacitor, particularly at initial application of the input voltage or potential VIN.
The structure and operation of the over voltage/under voltage monitor block 108, the "inrush" current control block 110, and the input capacitor(s) Cin may take any existing form, and are not subjects of this application so are not described in further detail.
Control of the converter circuit (e.g., synchronous buck converter) is realized via a number of components or assemblies, represented in Figures 1 and 2 as blocks.
The power converter 100 includes a synchronous gate timing drive control and pulse width modulation (PWM) block 112 and an oscillator ramp generation block 114. The is interchangeably referred to herein and in the claims as the gate drive or switch controller since the control signals produced thereby drive the pass switch of the converter. The oscillator ramp generation block 114 generates an oscillating ramp signal and provides the oscillating ramp signal to the synchronous gate timing drive control and pulse width modulation block 112. The oscillator ramp generation block 114 may optionally receive a synchronization signal via a synchronization input terminal SYNC IN, to synchronize operation with one or more other power converters or other devices or systems, for example a clock of a system in which power converter 100 is installed. The synchronous gate timing drive control and pulse width modulation block 112 generates gate control signals to control the switches T1, T2, for example via amplifiers U1, U2, respectively. The synchronous gate timing drive control and pulse width modulation block 112 may optionally receive a share signal via a share input terminal SHARE from one or more other power converters, for example when electrically coupled to a common load for current sharing operation. The structure and operation of the synchronous gate timing drive control and pulse width modulation (PWM) block 112 and the oscillator ramp generation block 114 can take any existing form, and are not subjects of this application, so are not described in further detail.
At a high level, the power converter 100 utilizes an inner current control loop and an outer voltage control loop. The inner current control loop is implemented via a current sense block 116, a current limiting/current sharing (CUCS) resistor network 118, a 1-D (one minus duty cycle) compensation block 120 and a current control amplifier 122. The outer voltage control loop is implemented by a voltage sense resistor divider network 124 and a voltage error amplifier 126 which feeds the CL/CS resistor network 118 to ultimately control the output voltage or potential of the power converter 100.
With respect to the inner current control loop, the current sense block 116 implements current sensing over a portion of a cycle of the power converter 100, for example over the ON or CLOSED portion of one of the switches T1, T2. The current sense block 116 provides a signal to the CL/CS
resistor divider network 118 to control the current control amplifier 122, which signal is indicative of the sensed current. For example, the current sense block 116 may sense current over each portion of a cycle during which portion the low side switch T2 is ON or CLOSED (i.e., conducting), electrically coupling the output inductor Lout to ground GND, while neglecting those portions of the cycle when the low side switch T2 is OFF or OPEN.
Where the output current of the synchronous buck converter circuit in the power converter 100 is sensed at the low side switch (e.g., MOSFET synchronous switch) T2, the average of this sensed current is equal to to*(1-D), where D is defined as the duty cycle of the high side switch (e.g., MOSFET) T1. Since this signal is dependent on the duty cycle and negative in value, a compensation signal that is a direct function of the duty cycle is scaled via the 1-D compensation block 120, and summed with the sensed current signal by the CUCS resistor network 118. The resultant signal is optionally level shifted in the CL/CS resistor network 118 to create a level shifted compensated signal. The level shifted compensated signal may then be averaged by the current control amplifier 122, and the averaged signal used to control the output current of the power converter 100.
This approach to current sensing presents both advantages and disadvantages. This current sensing approach may advantageously improve efficiency since only a portion (1-D) of the total output current of the power converter 100 is sensed. Also, the generated sensed current signal is directly referenced to the ground of the circuit, providing a significant simplification of the circuit implementation. However, the derived signal is disadvantageously a direct function of the duty cycle D of the high side switch T1 of the power converter 100. However, this disadvantage may be effectively overcome by a unique approach of summing in a compensation signal Vx(1-D) that sufficiently compensates for the duty cycle variation in the sensed current signal. As explained above, the summation of the compensation signal may be accomplished via the CUCS resistor divider network 118.
The current control amplifier 122 generates control signals based at least on the level shifted compensated signals from the CL/CS resistor divider network 117 to control the synchronous gate timing drive control and pulse width modulation block 112.
With respect to the inner current control loop, the voltage sense resistor network 124 (e.g., resistor Rfb coupled between voltage output terminal +VOUT and sense terminal SENSE, divider resistors Rd, Rc, and trim resistors Rb, Ra coupled to trim terminals TRIMB, TRIMA, respectively) senses voltage or potential at the output terminal +VOUT with respect to the ground terminal VOUTCOM. The voltage sense resistor network 124 supplies a signal indicative of the sensed voltage or potential to the voltage sense amplifier 126.
The voltage sense amplifier 126 generates a voltage error signal which indicates a difference between the sensed voltage or potential and a reference voltage or potential. Hence, the voltage sense amplifier 126 is interchangeably referred to herein and in the claims as voltage error amplifier 126. The voltage error amplifier 126 provides the voltage error signal to the current control amplifier 122 via the CUCS resistor divider network 118, for use in generating the control signals supplied to the synchronous gate timing drive control and pulse width modulation block 112 to control output voltage or potential of the power converter 100.
The power converter 100 may optionally include a soft start control block 128. The soft start control block 128 may receive the precision voltage reference signal VREF from the auxiliary power supply and voltage reference generation block 106. The soft start control block 128 may control various soft start characteristics of the power converter 100, for example soft-start time, current limit thresholds, current limit on-time and output voltage or potential level at which control is handed over to a main control loop. The soft start control block 128 may, for example, provide a progressively increasing pulse width, forming a startup voltage ramp which is proportional to a level of a supply voltage VCC, for instance without the need of an external capacitor.
The structure and operation of the soft start control block 128 can take any existing form, and is not a subject of this application so is not described in further detail.
Figure 2 shows the inner current loop and the outer voltage loop illustrated in Figure 1, according to one illustrated embodiment.
As illustrated, the inner current control loop includes a current control amplifier (e.g., operational amplifier) U_CA while the outer voltage control loop includes a voltage error amplifier (e.g., operational amplifier) U_VA.
The interface from the output of the current control amplifier U_CA
to the gate timing drive control and PWM module 112 (Figure 1) requires the output of the current control amplifier U_CA to be voltage level HIGH to generate a minimum duty cycle and to be voltage level LOW to generate maximum duty cycle. The current control amplifier U_CA averages a voltage across a sense resistor RSENSE produced by the switched current in the low side switch (e.g., MOSFET) T2 (Figure 1) of the switching power path, which is equal to (1 - D) times the DC output current where D is the converter duty ratio or duty cycle of the high side switch T1 (Figure 1). The Vx signal input to a resistor R1, a constant voltage switched with approximately the same (1 - D) timing as the RSENSE current, allows the current control amplifier U_CA to regulate for a constant output current independently of duty ratio. The resistor R1 is also coupled to a diode D1.
The voltage or potential Vc at a node 130 supplied to a resistor R3 is either the output voltage or potential of the voltage error amplifier U_VA or a voltage or potential on a SHARE input, pin or terminal. The voltage or potential on the SHARE input, pin or terminal is supplied from another power converter unit, as an active input to control the output current of the power converter 100. For limiting output current, the voltage or potential Vc at the node 130 is clamped to a maximum of approximately VREF via a transistor Q1.
A divider formed by resistors R5, R6 provides an offset to either cancel a nominal clamped voltage or potential Vc at the node 130 input during current limiting, or to provide an intentional shift of current limit value with duty cycle.
This bias also moves the reference point off of ground so that the current control amplifier U_CA can be powered from a single supply. An output of the current control amplifier U_CA is coupled to a negative pin thereof via a current forward capacitor Ccf and current forward resistor Rcf. A capacitor C1 is coupled across the positive and negative pins or inputs of the current control amplifier U_CA. An output of the voltage error amplifier U_CA is coupled to a negative pin thereof via a voltage forward capacitor Cvf and current forward resistor Rvf..
The 1-D compensation approach is best explained with a derivation of the controlling equation for the CL/CS resistor divider network (Figure 1). The derivation uses Millman's theorem to simplify the expressions and generate a design oriented equation that explicitly shows the impact of each signal summed in the CL/CS resistor divider network 118 (Figure 1).

Solving for the voltages at each input of the current control amplifier U_CA:
Vpositive(Vp) = (VREF/R5)*R511R6 Vnegative(Vn) = [Vc/R3 + ((1-D)*Vx)/R1 - (lout*(1-D)*RSENSE)/R4]*R1IIR311R4 Setting Vp = Vn, and solving for lout:
lout = [Vc*a3 - VREF*a5 + (1-D)*Vx*a1]/(RSENSE*(1-D)*a4) Where al = (R1IIR3tIR4)/R1 a3 = (R1 11 R31 IR4)/R3 a4 = (R1 IIR3IIR4)/R4 a5 = (R511R6)/R5 The resulting equation shows that the dependence on 1-D for either the maximum output current lout or a current limit trip point (C.L.T.P) for an overload fault condition, can be greatly reduced with adjustment of the terms al, a3, a4 & a5, or 1-D compensation. The optimum 1-D compensation may also be made to satisfy the following additional operating constraints.
Minimum Duty Cycle Operation Minimum duty cycle condition results when the output voltage of the voltage error amplifier U -VA drives LOW, generating minimum output voltage and consequently reduced duty cycle. The Vx(1-D) offset signal simultaneously increases to Vx at 0% duty cycle. To reach and maintain this state, the resulting inputs to the current error amplifier U_CA must be such that a positive pin thereof is guaranteed to be greater than a negative pin thereof, guaranteeing a HIGH output state at an output of the current control amplifier U-CA. This is shown by the following equation:
Vp>Vn VREF*a5 > Vx*al (VREF*R6)/(R6+R5) > (Vx*R411R3)/(R411R3 + R1) During the minimum duty cycle condition, Vx is HIGH, Vc is LOW
resulting in the above equation.
Short Circuit Protection / Lock-On Protection A short circuit condition on the output of the power converter 100 creates the possibility of a 100% duty cycle condition. This 100% duty cycle condition will be indefinite if not mitigated. If 100% duty cycle is ever achieved, the low side current sense in the power converter 100 will not sense an output current, which will result in the current control loop attempting to indefinitely drive to a higher duty cycle.
This state is most likely to occur at the application of a hard short circuit on the output. Further precipitating a 100% lock-on condition is the voltage feed forward function in the ramp generator circuit 114 (Figure 1), a function often utilized in power converters to compensate gain as the input voltage or potential changes. During a load short condition, the input line is pulled low due to impedance drop in the input source connections. The oscillator ramp amplitude can consequently drop below the reference of the comparator and throw the circuit into 100% duty cycle before the control system has time to compensate.
This state can be avoided with a number of different approaches.
The chance of this occurring can be alleviated or remedied by reducing feed forward or by sufficiently increasing the bandwidth of the current control loop so as to react fast enough to shut down the power converter. Other possible approaches include logic which monitors for a lock-on state and resets or prevents the condition from occurring. Blanking the oscillator ramp is also a viable approach, which forces a switch signal to always appear at the switches T1, T2 (Figure 1) and thus remove the possibility of 100% duty cycle. However each of these approaches disadvantageously requires additional components.
In the power converter 100, the undesirable 100% duty cycle state may be avoided through the careful selection of the current error amplifier resistors such that the positive pin of the current error amplifier U_CA is guaranteed to be greater than the negative pin of the current error amplifier U -CA in a short circuit condition:
Vp > Vn VREF*a5 > Vc*a3 (VREF*R6)/(R6+R5) > (Vc*R111R4)/(R111R4 +R3) During the short circuit condition, Vc is HIGH, Vx is LOW resulting in the above equation.
Current Limit Trip Point The final constraint that the Current Limit Trip Point (C.L.T.P.) must meet a specification range that does not interfere with normal operation, and is not so high as to not offer reasonable current limit protection. The C.L.T.P set point range is represented by the following equation:
CLTP.min < (Vc *a3 - VREF*a5 + (1-D)*Vx*a1)/(RSENSE*(1-D)*a4) < CLTP.max where al = (R1IIR3!1R4)/R1 a3 = (R1 IIR3IIR4)/R3 a4 = (R1 11 R3IIR4)/R4 a5 = (R511R6)/R5 In summary, the described power converter 100 may meet the above constraint relationships, guaranteeing that minimum duty cycle can be maintained, that 100% duty cycle lock-on is prevented, and that the C.L.T.P.
can meet minimum specification without being too high.
Figure 3 shows the inner current loop and the outer voltage loop illustrated in Figure 1, according to another illustrated embodiment. Many of the structures or components are similar or even identical to those discussed with reference to Figure 2. Some of the similar or identical components are identified by the same reference numbers as used in Figure 2, and detailed discussion of such may not be repeated in the interest of brevity.
In embodiment of Figure 3, the small working range and the sensitivity to error at the inputs of the current control amplifier U_CA
present a few possible limitations. First, a change to any gain term at the current control amplifier junction has a dramatic effect on the C.L.T.P. Second, the voltage error amplifier U -VA is forced to drive into the current sense scaling resistor which must be relatively small to enable proper current sense drive and thus the gain of the voltage error amplifier U VA is significantly reduced.
Additionally, at any condition three signals must be summed and compared against a static reference, yielding higher sensitivity to error than might otherwise be desired. Lastly, although the Vx(1-D) compensation signal properly level shifts the negative Vsense(1-D) signal, Vx(1-D) signal can only fully remove the 1-D component at one condition and simply be scaled to reduce its effect at other operating points. Thus, the C.L.T.P is to some degree always a function of duty ratio.
The embodiment of Figure 3 may overcome some or all of the limitations of the embodiment of Figure 2, and may reduce complexity as well.
As illustrated in Figure 3, the control signal from the voltage error amplifier U_VA is fed into the positive input or pin of the operational amplifier U_CA. Since the gain of the voltage error amplifier U VA is dependent on the value of resistor R3, the SHARE line is decoupled from the resistor R3 and is driven from a common emitter stage, allowing numerous power converter units to current share without affecting the performance or integrity of the current control loop. A pair of resistors R6 and R7 can be used as bias resistors to raise a DC operating point at the inputs of the current control amplifier U_CA
to a level sufficiently above ground, or not used in cases were positive bias on the pins of the current control amplifier U_CA is not required.
Similar to the embodiment of Figure 2, a derivation of the lout current relationship using Millman's Theorem produces a design oriented equation that explicitly shows the impact of each signal summed in the CL/CS
resistor divider network 118 (Figure 1) can be derived.
Solving for the voltages at each input of the current control amplifier U_CA:
Vpositive(Vp) = (VREF/R7+lc)*R3IJR7 Vnegative(Vn) = [VREF/R6 + ((1-D)*Vx)/R1 - (lout*(1-D)*RSENSE)/R4]*R111R411R6 Setting Vp = Vn, and solving for lout lout = [(1-D)*Vx*[31 + VREF* ([36 - [37) - ic* Rp1]/(RSENSE*(1-D)*
34) Where Rpl=R311R7 R1 = (R1IIR411R6)/R1 R4 = (R111 R41 I R6)/R4 R6 = (R111 R41 IR6)/R6 R7 = (R311R7)/R7 The resulting equation is similar in form to that described in reference to Figure 2. However, the implementation shows improvements over the embodiment of Figure 3, in that the maximum lout or current limit trip point (C.L.T.P) dependence on 1-D can be completely canceled with adjustment of the terms [i6 & [37 to make the ([36 - (37) equal to or nearly zero.
The optimum 1-D compensation of this embodiment can satisfy the same additional operating constraints as that of Figure 2:
Minimum Duty Cycle Operation Similar to the embodiment of Figure 2, minimum duty cycle condition results when the output voltage of the voltage error amplifier U_VA
drives LOW, generating minimum output voltage or potential and consequently reduced duty cycle. The Vx(1-D) offset signal simultaneously increases to Vx at 0% duty cycle. To reach and maintain this state the resulting inputs to the current control amplifier U_CA must be such that the positive pin is guaranteed to be greater than the negative pin, guaranteeing a HIGH output state at the output of the current control amplifier U_CA. This requirement is shown by the following equation:
Vp>Vn VREF* (37 + Ic* Rp1 > Vx*R1 + VREF*R6 VREF*R3/(R3+R7) + Ic*R3*R7/(R3+R7) > (Vx*R411R6)/(R411R6 +
R1) + VREF* R1 IIR4/(R6+ R1 JJR4) During the minimum duty cycle condition, Vx is HIGH, Ic is fully ON resulting in the above equation.
Short Circuit Protection / Lock-On Protection As in the embodiment of Figure 2, the undesirable 100% duty cycle state is avoided through the careful selection of the current error amplifier resistors such that the positive pin of the current error amplifier U_CA is guaranteed to be greater than the negative pin of the current error amplifier U -CA in a short circuit condition:
Vp > Vn VREF* (37 > VREF* (36 - (lout*(1-D)*RSENSE*(34) VREF*R3/(R3+R7) > (VREF*R1 IIR4)/(R1 IIR4 + R6) - (lout*(1-D)*RSENSE* R1 JIR6/(R4+ R1 IIR6) During the short circuit condition, Vc is HIGH and Ic is OFF, Vx is LOW resulting in the above equation. Assuming the same lock-on state and conditions as before, at 100% duty cycle, Vx(1-D) goes low and the voltage error amplifier drives HIGH, thus cutting OFF Ic and the voltage at resistor R3.
Consequently, if any current is sensed, the resistor R4 will pull the inverting pin of the current error amplifier U_CA below the positive pin of the current error amplifier U_CA and the power converter 100 will current limit.
Overload Current Limit Trip Point With this implementation, as the current increases towards overload, the voltage error amplifier U_VA will again drive HIGH to maintain the output voltage or potential, driving Ic OFF and the voltage at resistor R3 LOW.
Thus, at the C.L.T.P, the relationships are:
Vpositive = Vnegative VREF* 137 = Vx*(1-D) *(31 + VREF* (36 - (lout*(1-D)*RSENSE*(34) This equation yields the following maximum lout result:
C.L.T.P = [(1-D)*Vx*11 + VREF* ([36 - R7)]/(RSENSE*(1-D)* (34) During the C.L.T.P condition, Vc is HIGH and Ic is OFF resulting in the above equation.
It can be seen that duty cycle dependence does come back into the equation, but it only exists as a small error term, which can be substantially reduced by minimizing the bias difference between the pins of the operational amplifier.
An additional improvement with this circuit is the voltage error amplifier U _VA is no longer forced to drive into the scaling resistor for the current sense signal and the forward voltage loop gain can now be independently set by the resistor R3 with no effect on the current limit.
In summary, this second approach again utilizes the fundamental (1-D) current sense and (1-D) compensation. The circuit implementation may improve load transient response, minimum duty cycle operation, inherent short circuit and lock-on protection, C.L.T.P. set point, and the ability to drive multiple power converter units from the share output pin SHARE without degrading the control loop or C.L.T.P set point.
Figure 4 shows a number of power converters 400a, 400b, 400c, 400d (four illustrated, collectively 400) of Figure 1 arranged as point-of-load devices, according to one illustrated embodiment.
The power converters may be electrically coupled to a common DC voltage or potential input VIN DC. The common DC voltage or potential input VIN DC may take any of a variety of forms including an output of a rectifier, a DC/DC converter, an isolating conversion stage, and/or a DC
electrical power storage device such as an array of chemical battery cells or ultra-capacitors.
A first power converter 400a may be operated to provide an output at a first voltage or potential (e.g., 0.8V) to a first power bus to service a first load (e.g., 0.8V load). A second power converter 400b may be operated to provide an output at a second voltage or potential (e.g., 1.2V) to a second power bus to service a second load (e.g., 1.2V load). A third power converter 400c may be operated to provide an output at a third voltage or potential (e.g., 2.5V) to a third power bus to service a third load (e.g., 2.5V load). A fourth power converter 400d may be operated to provide an output at a fourth voltage or potential (e.g., 3.3V) to a fourth power bus to service a fourth load (e.g., 3.3V
load).
Each of the power converters 400 may receive an enable signal via an enable line and switches, collectively 402. This allows remote operation (e.g., turn ON, turn OFF) of the respective power converters 400. The enable lines and switches 402 may be buffered with respective external timing capacitors CT1, CT2, CT3, CT4. Such may delay startup of the power converters 400. This delay is between application of power and beginning of internal power conversion. There is typically an additional delay as the power converter 400 begins normal startup sequence and ramps to final or nominal output voltage or potential.
Output current monitoring may be performed by appropriate monitoring circuitry 404 which receives signals from respective share pins SHARE of the power converters 400. As explained above, the power converters 400 may include a current sharing feature that allows multiple power converters 400 to operate as a single supply, capable of providing a total current that is the sum of the maximum current of the individual power converter units, when operated in parallel. Such current sharing operation is illustrated and discussed in reference to Figure 5.

Figure 5 shows a number of power converters 500a, 500b (only two shown, collectively 500) of Figure 1 electrically coupled in parallel to perform current sharing with respect to a common load 502, according to one illustrated embodiment.
The power converters 500 may be coupled to receive DC power from one or more DC power sources on input pins WIN, VIN COM. For example, the power converters 500 may be coupled to receive power from a single DC source 504 as illustrated in Figure 5. The DC source 504 may take any of a variety of forms including an output of a rectifier, an isolating conversion stage, a DC electrical power storage device such as an array of chemical battery cells or ultra-capacitors, or as illustrated a DC/DC
converter.
The DC source 504 may in turn receive power from an upstream DC source 506, for example a rectifier or power supply, and may receive a synchronization or clock signal on a synchronization input pin SYNC IN from a system clock 508. The DC source 504 may provide a synchronization or clock signal from a synchronization output pin SYNC OUT to the power converters 500 via respective synchronization input pins SYNC IN. Such may allow the oscillator ramp generator 114 (Figure 1) of the power converter 500 to be synchronized with a system clock or with a bus voltage source of the system in which the power converter 500 is incorporated, thereby preventing the generation of low frequency (e.g., audio range) sub-harmonics.
As described above, each of the power converters 100a-100n may include a share input terminal SHARE to facilitate current sharing operation. In connecting the power converters 500 in parallel, one of the power converters is configured and functions as a master (illustrated as power converter 500a), while the other power converters are configured and function as slaves (illustrated as power converter 500b, only one slave shown).
In connecting the power converters 500 in parallel, the share pin SHARE is connected between the power converters, and all except the power converter 500a acting as the master will have trim pins TRIMA, TRIMB tied to the positive output voltage terminal +VOUT and the sense pin SENSE. The trim pins TRIMA, TRIMB of the power converter 500a acting as master are configured to set a desired output voltage or potential. The power converters 500b acting as slaves will match the current and voltage or potential of the power converter 500a acting as master. The power converter 500a acting as master will have the highest pre-set output voltage or potential (e.g., as illustrated in Figure 5 both trim pins TRIMA, TRIMB of power converter 500a are open, for a 0.8 V output.) Notably, the voltage or potential on the share pin SHARE is proportional to the output current supplied by the power converter 500, and thus may be used to monitor output current. Thus, the share pin SHARE can be used to drive a power converter 500 as a voltage controlled current source, where the output current will be proportional to the applied voltage with an offset.
Figure 6 shows a method 600 of operating the power converter of Figures 1-3, according to one illustrated embodiment. In particular, Figure 6 illustrates operation of the inner current control loop.
At 602, a current sensor 116 senses output current of first switch mode power converter 100 with reference to ground over only portion of waveform. For example, the current sensor may sense current at a source of a low side active switch (e.g., MOSFET) T2, thus only over an ON duty cycle portion of the low side active switch T2.
At 604, a compensation circuit 120 determines a compensation signal that is direct function of a duty cycle of the switch. At 606, the compensation circuit 120 scales the compensation signal to account for duty cycle differences.
As previously described the compensation signal may compensate for the fact that the sensed current is sensed for only portion of the cycle when the low side active switch T2 is conducting or ON, during which time the high side active switch T1 is off. Thus, the compensation signal may reflect this difference in duty cycle, as the sum of 1-D.

At 608, a CL/CS resistor network 118 compensates a sensed current signal that is proportional to sensed output current at least for variation in duty cycle switch. For example, the CL/CS resistor network 118 may sum the scaled compensation signal with the sensed current signal. At 610, the CL/CS resistor network 118 level shifts the compensated sensed current signal to produce a level shifted compensated sensed current signal. The compensation and the level shifting may be performed concurrently, sequentially, or as part of a single operation (e.g., summing).
At 612, a current control amplifier 122 averages a signal that is at least proportional to compensated sensed current signal to produce averaged signal. For example, the current control amplifier 122 may average the level shifted compensated sensed current signal.
Optionally at 614, the values of select resistors maintain a positive pin of the current control amplifier U_CA more positive than a negative pin of the current control amplifier U_CA during a short circuit condition. Proper selection may provide short circuit protection, preventing a lock-on condition from occurring.
At 616, the synchronous gate timing drive control and PWM block 112 controls the switches T1, T2 based at least in part on averaged signal received from the current control amplifier 122.
The method 600 may repeat while the power converter 100 is operational, continually updating sensed values and applied signals.
Figure 7 shows a method 700 of operating the power converter of Figures 1-3, according to one illustrated embodiment. In particular, Figure 7 illustrates operation of the outer voltage control loop. The method 700 may be implemented as part of performing the method 600 of Figure 6.
At 702, a voltage sensor senses output voltage or potential of first switch mode power converter. For example, the a voltage sense resistor network 122 may sense the output voltage or potential.

At 704, a voltage error amplifier 126 produces a voltage error signal indicative of error between sensed voltage or potential and reference voltage or potential.
At 706, one or more switches (e.g., transistor Q1 of Figure 2 or switches Q1, Q2 of Figure 3) switch between voltage error signal and voltage input from second switch mode power converter to operate first and second switch mode power converters 500a, 500b (Figure 5) in current sharing mode to supply common load.
At 708, the synchronous gate timing drive control and PWM block 112 (Figure 1) controls the switches T1, T2 (Figure 1) based at least in part on the voltage error signal generated by the voltage error amplifier.
At 710, a feedback voltage error signal is provided to the non-inverting input of the current error amplifier U_CA (Figures 2 and 3).
As illustrated and described in reference to Figures 8-XX, below, the power converter 100 or a power converter employing a different topology or without the 1-D compensation discussed above, may advantageously employ a swinging choke 800a, 800b, 800c (collectively 800, Figures 8A-8C) as the inductive element Lout (Figure 1) of the converter topology. Some structures and/or acts may be similar, or even identical, to those previously described.
Such structures and/or acts will be referred to using the same reference numbers as above.
In particular, because the gate drive 112 may be responsive to voltages across resistors that are coupled to the output terminal +VOUT, if a conventional inductor were used a discontinuous or reversed current through the conventional inductor may cause an instability in the output regulation loop.
If a current flowing through a feedback resistor Rfb at the output terminal +VOUT stops or is reversed, then the gate drive 112 may determine that the voltage at the output terminal +VOUT should be increased, even if such is not the case. The gate drive 112 may then adjust the duty cycle by which switches T1, T2 are driven to increase the voltage at the output terminal +VOUT until expected voltage are realized across the feedback resistor Rfb. Such loop instability may damage voltage sensitive devices or loads, which may be coupled to the output terminal +VOUT. Such may be remedied by use of the swinging choke 800a, rather than a conventional inductor.
The swinging choke 800a may be a single component or a network of several discrete components. The swinging choke 800a provides a low inductance path between the switches T1, T2 and the output terminal +VOUT for medium and high current load conditions and may provide a high inductance path between the switches T1, T2 and the output terminal +VOUT
for light and no current load conditions. The swinging choke 800a provides a low inductance path at medium and high current load conditions to facilitate fast transient responses to changes in load demands, such as is typical in digital devices. The swinging choke 800a provides a high inductance at light and no current load conditions to maintain continuous current conduction or to decrease reverse current through the swinging choke 800a. Maintaining a continuous conduction at the load may be desirable because discontinuities in current conduction at the load may cause instability in the output regulation loop, as discussed above, and may cause increased electromagnetic interference (EMI).
Discontinuities in current conduction typically arise when a power converter stops driving a high side active switch, a low side active switch, or both the high side and low side active switches in order to decrease light load inefficiencies caused by circulating currents. According to existing approaches, a power converter utilizing a synchronous rectifier (without the benefit of a swinging choke) will induce a circulating current when the associated load demand decreases towards zero amps. The synchronous rectifier draws a circulating current from an output capacitor or other storage element through a reverse inductor current into the input terminal through a high side active switch when the high side active switch is turned ON. An input capacitance that may exist in the power converter temporarily stores charge from the circulating current before the high side transistor redistributes the stored charge back to the output capacitor. In an ideal lossless system, the transfer of charge from an output capacitor to an input capacitor and back again in the form of a circulating current during light or no load conditions would not be detrimental to power converter efficiency. However, real circuits dissipate power in the many parasitic resistances. The dissipated power is proportional to the square of the current multiplied by the sum of the parasitic resistances (Pdissipated =
12Rparasitic).
To reduce the effect of circulating currents some power converters completely disable the synchronous rectifier at light loads or selectively turn off the synchronous converter as the inductor current reaches the zero-crossing point, i.e., the inductor current begins to reverse. Each of these options reduce the issue of circulating currents but do so with many associated costs. For example, selectively shutting down the synchronous rectifier produces discontinuities in the current and results in loop instability and in ringing in the switch voltage waveform, thereby adding EMI to the system.
Furthermore, completely disabling the synchronous rectifier at light loads is a forfeiture of range (the ability to supply light load currents), and sensing the zero-crossing point of the inductor current may result in addition of complex circuitry to the power converter.
The swinging choke 800a advantageously decreases the effect of circulating currents inherent in the synchronous rectifier inclusive of gate drive 112 and active switches T1, T2. The swinging choke 800a provides the inductance to smooth out ripple at both high and medium load currents without reducing efficiency. At light (near-zero) load conditions, the swinging choke 800a also assumes a much larger inductance, preventing the current from becoming discontinuous during this condition. During no load conditions the much larger inductance of the swinging choke 800a provides substantially greater impedance to the circulating currents that would otherwise flow from the output capacitance Cout (Figure 1) to the input capacitance Cin (Figure 1) on input terminal VIN (Figure 1). Thus, by utilizing the swinging choke 800a, the power converter 100 substantially reduces or eliminates losses caused by circulating currents and thus operates more efficiently at light (near-zero) and no load conditions without circuitry for sensing the zero-crossing point of swinging choke current and without shutting off the synchronous rectifier.
The swinging choke 800a may take a variety of forms. For example, the swinging choke may be constructed with an "E" core, as illustrated in Figures 3A, 3B, and 3C. The core of an "E" core swinging choke resembles two capital letter "E's" formed of metal and pressed against one another to form a core which is eventually wound with conductive wire.
Figure 8A illustrates a swinging choke core 800a, according to one illustrated embodiment. The swinging choke core 800a includes a first E-shaped choke member 802 and a complimentary second E-shaped choke member 804 opposed to the first E-shaped choke member. The E-shaped choke members 802, 804 may be coupled together by any suitable structures or substances. Typically one or more windings (not illustrated in Figures 8A-8C) are wound about the E-shaped choke members 802, 804.
The E-shaped members 802, 804 each have a pair of outer leg members 806a, 808a, 806a, 808b, respectively and an inner leg member 810a, 810b. Complimentary pairs of the outer leg members 806a, 806b, 808a, 808b form respective outer legs 806, 808, while the complimentary pair of intermediate leg members 810a, 810b form an intermediate leg 810. The intermediate leg members 810a, 810b may contact one another over a portion thereof. Complimentary outer leg members 806a, 806b, 808a, 808b have a respective gap 812a, 814a located between end portions thereof.
The gap(s) 812a, 814a between the complimentary pairs of outer leg members 806a, 808a, 806b, 808b determine(s) the inductance of the swinging choke 216. The gap 812a, 814a may include at least one step so that part of the gap 812a, 814a is a shorter distance than (i.e., smaller) the remainder of the gap 812a, 814a. The cross-section of the part of the gap having the shorter distance may be smaller than the cross-section of the remaining gap so that the impedance created by the smaller cross-section (the smaller gap, the higher the impedance) saturates quickly under medium and high load conditions.

Figure 8B illustrates a swinging choke core 800b, according to another illustrated embodiment. The swinging choke core 800b is similar in many respects to that illustrated in Figure 8A. Similar structures are identified with the same reference number as used in Figure 8A. Only significant differences are discussed, below.
The swinging choke core 800b differs from the swinging choke core 800 in that gap(s) 812b, 814b includes multiple steps between the end portions of the outer leg members 806a, 808a, 806b, 808b. The multiple steps define the inductance of the swinging choke 800b.
Figures 8C illustrates a swinging choke core 800c. The swinging choke core 800b is similar in many respects to that illustrated in Figures 8A
and 8B. Similar structures are identified with the same reference number as used in Figures 8A and 8B. Only significant differences are discussed, below.
The swinging choke core 800c differs from the swinging choke cores 800a and 800b in that the end portions of one or both of outer leg members 806a, 808a, 806b, 808b may be beveled relative to a plane passing between the E-shaped members 802, 804 to form a ramp such that the size and distance of the gap(s) 812c, 814c varies linearly as the surfaces are traversed along at least one path.
Accordingly, the inductance of the swinging choke 216 may vary as a function of current flow through the swinging choke 216.
The power converter 200 may include optional preload resistor 220. The preload resistor 220 may cause small amounts of current to flow during no load conditions, i.e., while the device 222 does not draw current.
The preload resistor 220 may have a sufficiently high resistance so as not to significantly impact the amount of current supplied to the device 222 during medium and high load conditions. The preload resistor 220 may contribute to additional inefficiencies. However, when combined with the swinging choke 216, the preload resistor 220 may contribute to a net decrease in power inefficiencies at light and no load conditions over existing approaches.

While Figures 8A-8C illustrated a gap 812a, 814a, 812b, 814b, 812c, 814c between end portions of each complimentary pair of outer leg members 806a, 808a, 806b, 808b, some embodiments may have a gap between only one pair of the outer leg members.
While each of Figures 8A-8C illustrate a swinging choke core 800a, 800b, 800c with an outer leg core configuration, other configurations may be employed. For example, a center post ground core configuration may be employed with a gap formed between the intermediate leg members 810a, 81 Ob, rather than between the outer leg members 806a, 808a, 806b, 808b.
The stepped or angled gap may be located between portions of complimentary pieces that form the intermediate leg 810.
Figure 9 shows a method 900 of operating the power converter 100 of Figure 1, according to one illustrated embodiment.
At 902, the CL/CS resistor network 118 (Figure 1) determines voltage at an output terminal. For example, the CL/CS resistor network 118 may determine the voltage at the output terminal +VOUT by comparing a reference voltage within the feedback circuit 208 to a voltage across a sense resistor that is coupled to the output terminal +VOUT. The current control amplifier 112 (Figure 1) provides a signal indicative of the sensed voltage to the gate drive 112. Additionally or alternatively, the CL/CS resistor network 118 may determine the current flowing into the output terminal +VOUT and provide a signal indicative of the determined current to the gate drive 112.
At 904, the gate drive 112 determines a switching cycle or frequency based on the voltage at output terminal. The gate drive 112 may receive a signal indicative of voltage at the output terminal +VOUT from the feedback circuit 208. The gate drive 112 may additionally or alternatively receive a signal indicative of the current flowing through the output terminal +VOUT from the feedback circuit 208. The gate drive 112 may determine, increase, or decrease the switching cycle (e.g., duty cycle) used to control active switches T1, T2. The switching cycle may be proportional to the regulated voltage at the output terminal +VOUT so that increases in switching cycle or frequency correspond to increases in the regulated voltage while decreases in switching frequency correspond to decreases in the regulated voltages. The frequencies used by the switching cycle may range from 280 kHz through 600 kHz, according to one embodiment.
At 906, during first portion of switching cycle, the gate drive 112 causes the high side active switch to electrically pass current from the input terminal to the output terminal through the swinging choke 800. For example, the gate drive 112 may drive (turn ON) the first active switch T1 to pass current from input terminal 202 to output terminal +VOUT through swinging choke 800.
During the first portion of the switching cycle, the current supplied to the output terminal +VOUT by the swinging choke 800 gradually increases.
At 908, during second portion of switching cycle, the gate drive 112 causes the low side active switch to electrically pass current from ground to the output terminal through the swinging choke 800. Gate drive 112 may drive (turn ON) the second active switch T2 to pass current from ground GND to the output terminal +VOUT through the swinging choke 800. During the second portion of the switching cycle the current supplied to the output terminal +VOUT
by the swinging choke 800 is gradually reduced.
By supplying a gradually increasing current in the first portion of the switching cycle and by supplying a gradually decreasing current in the second portion of the switching cycle to the output terminal +VOUT, the active swinging choke 800a supplies an average current that is sufficient to meet the current demands of the load.
Figure 5 shows an additional method 920 that may be performed as part of the method 900 of Figure 4.
At 922, the power converter 100 allows inductance of the swinging choke 800 to increase and decrease based on current demand of a load. The swinging choke 800 may increase its inductance as the load enters a light load or no load (no current demand) condition to prevent current from reversing through the swinging choke 800 and circulating back through first active switch T1. When the current demand of the load increases, the swinging choke 800 decreases its inductance to become more responsive to the fast transient load currents that are typical to digital loads.
Figure 10 shows an auxiliary power supply or very or ultra low input voltage bias voltage supply 106, according to one illustrated embodiment.
The auxiliary power supply or voltage bias voltage supply 106 may implement the auxiliary power supply and voltage reference generation block 106 (Figure 1) to supply, produce or generate regulated bias supply voltages or potentials VCC, VSS suitable for powering circuitry of a device at very or ultra low input voltages.
The auxiliary power supply or bias voltage supply 106 includes a boost converter circuit 1002, synchronization capacitor or capacitance Csync and a feedback circuit 1004 coupled to control the boost converter circuit 1002 based on a difference between an output voltage VOUT and a reference voltage VIN, the auxiliary power supply or bias voltage supply 106 capable of automatically synchronizing to a dynamic load. Primarily the gate drive buffer amplifies V1 + V2 of Figure 1.
The boost converter circuit 1002 includes an auxiliary transformer TAUx, which has a first winding 1006 and a second winding 1008 and a core 1010 on which windings forming the first winding 1006 and second winding 1008 may be wrapped. The first winding 1006 acts as an inductor in the boost converter topology, with a first pole (pin 1) coupled to an output pin, terminal or node 1012 and a second pole (pin 2) coupled to the input pin, terminal or node 1014. The boost converter circuit 1002 also includes a converter primary switch QAUX (e.g., transistor) operable in response to control signals from the feedback control circuit 1004 to selectively couple the first pole (pin 1) of the first winding 1006 to a ground reference or potential GND. The boost converter circuit 1002 includes an output diode DAUx serially coupled between the first pin of the auxiliary transformer TAUx and the output pin, terminal or node 1012.
The synchronizing capacitor or capacitance Csync may be electrically coupled in parallel with the output diode DAUx between a collector of the converter primary switch QAUx and the output pin, terminal or node 1012. An output capacitor CLoad may couple the output pin, terminal or node 1012 to a ground reference or potential GND.

The feedback circuit includes a summing device E, bipolar voltage-to-current converter A, control capacitor Ccontro,, unipolar voltage-to-current converter B, drive capacitor CDrive and drive resistor Rpf1Ve. The voltage-to-current converter A, and unipolar voltage-to-current converter B are each coupled to a ground reference or potential GND.
In operation, a difference between a reference voltage VREF and the output voltage VOUT is applied to the bipolar voltage-to-current converter A. This current is collected in a capacitor to create a time averaged control voltage or potential on the terminals of the control capacitor Ccontroh representing the required drive energy to maintain a desired output voltage VOUT. This control voltage is applied to the unipolar voltage-to-current converter B. The resulting current is collected and stored in the drive capacitor CDrive. The voltage on the drive capacitor CDr;ve begins to rise, and is transferred to a base of the converter primary switch Q via a drive resistor RDrive and the second winding 1008 of the auxiliary transformer TAUx. When the voltage on the base of the converter primary switch QAUx reaches the required base-to-emitter voltage (Vbe) threshold, base current will flow causing a greater amount of collector current to flow.
This collector current in converter primary switch QAUX flows through the first winding 1006 of auxiliary transformer TAUx and begins to develop a voltage across the first winding 1006. This voltage is reflected to the second winding 1008 causing an additional base voltage drive to the base of converter primary switch QAUX. The converter primary switch QAUX in turn develops an even greater collector current, and this positive feedback loop forces the converter primary switch QAUX to turn ON fully with the collector-to-emitter voltage equal to saturation voltage (i.e., Vice=Vsat)=
In response, the current in the first winding 1006 of auxiliary transformer T begins to ramp at this instant. The voltage developed across the second winding 1008 of the auxiliary transformer TAUx continues to move charge stored in the drive capacitor CDrive into the base of the converter primary switch QAUX. This continues as the current of the auxiliary transformer TAUx ramps, until the drive capacitor or capacitance CDf1Ve is sufficiently depleted and can no longer supply enough energy to sustain the required base current to meet the requirements of increasing demand of the ramping TAUx current in the collector of the converter primary switch QAUx.
At this point, the voltage across the first winding 1006 of auxiliary transformer TAUx begins to decrease, and this voltage change is reflected in the second winding 1008 causing a reduction in base drive current to the base of the converter first winding switch QAUX. This action further reinforces the turn OFF of the converter primary switch QAUx and thereby interrupts the current path through the first winding 1006 of the auxiliary transformer TAUX to the ground reference or potential GND.
In response, the auxiliary transformer output voltage will rise above the input voltage VIN until the auxiliary transformer TAUx can release stored magnetic energy as current through output diode D into the load capacitor VOUT load. After the total stored magnetic energy is transferred to the load, the voltage across the auxiliary transformer TAUx windings return to zero. During this drive cycle the voltage across the drive capacitor or capacitance CDr;Ve will have been driven negative. The voltage to the unipolar voltage-to-current converter B continues to supply DC current to the drive capacitor or capacitance CDr;Ve until the base current of the converter primary switch QAUx again begins to flow and the cycle repeats.
As the drive capacitor or capacitance CDrive is charging, if a large dynamic load current demand causes the output voltage VOUT to abruptly decrease, the synchronization capacitor or capacitance CSyn, will cause a small pulse voltage to be developed across the first winding 1006 of auxiliary transformer T. This voltage pulse will be reflected into the second winding to drive the base of converter primary switch QAUX positive. Thus, this initiates a cycle synchronized to a periodic load demand with proper selection of the load capacitance CLoad to allow some output voltage ripple.

Figure 11 shows the auxiliary power supply or very or ultra low input voltage bias voltage supply 106 of Figure 10 with the feedback circuit 1004 represented in more detail. Many of the components and configuration illustrated in Figure to are similar or even identical to those of Figure 10.
Hence, similar or identical components between these Figures will share common reference numbers, and in the interest of brevity only some of the significant differences will be discussed below.
The feedback circuit 1004 may be implemented using an integration amplifier U, to determine a time averaged difference between an output voltage VOUT and a reference voltage VREF. A positive pin or input of the integration amplifier U, is coupled to the reference voltage VREF via a reference resistor RREF. A negative pin or input of the integration amplifier U, is coupled to the output voltage VOUT via an output signal resistor Ros, and is also coupled to ground via a ground resistor RGND. An output of the integration amplifier U, is coupled to the unipolar voltage-to-current converter B. The output of the integration amplifier U, is also fed back to the negative pin or input of the integration amplifier U, via a feedback capacitor CFB and auxiliary feedback resistor RAUX FB.
The unipolar voltage-to-current converter B is implement by a voltage-to-current resistor Rv_c, voltage-to-current transistor Tv_c and voltage-to-current diode Dv-c. The voltage-to-current resistor Rv_c supplies a current to an emitter of the voltage-to-current transistor Tv_c generated by the voltage or potential of the output of integration amplifier U1. A base of the voltage-to-current transistor Tv_c is coupled to a ground reference or potential via the voltage-to-current diode Dv-c. A collector of the voltage-to-current transistor Tv-c is coupled to the second winding 1008 of the auxiliary transformer TAUx via the drive capacitor or capacitance CDr1Ve and the drive resistor RDrive.
Thus, the circuit of Figures 10 and 11 provide and simple elegant solution for generating supply bias voltage at higher levels than an input voltage, while implementing inherent synchronization with a dynamic load.

Figure 12 shows an auxiliary power supply or very or ultra low input voltage regulated bias voltage supply 106, according to one illustrated embodiment. The auxiliary power supply or voltage bias voltage supply 106 may implement the auxiliary power supply and voltage reference generation block 106 (Figure 1) to supply, produce or generate regulated bias supply voltages or potentials VCC, VSS suitable for powering circuitry of a device at very or ultra low input voltages.
The auxiliary power supply or regulated bias voltage supply 106 is coupled to an input pin, terminal or node 1202 to receive in input voltage or potential VIN and to a ground pin, terminal or node 1204 to receive a ground reference or potential GND. The auxiliary power supply or regulated bias voltage supply 106 has a first output pin, terminal or node 1206 to supply the bias voltage or potential VCC and a second output pin, terminal or node 1208 to supply the bias voltage or potential VSS.
The auxiliary power supply or regulated bias voltage supply 106 includes a boost converter 1210, charge pump circuit 1212, and feedback control circuit 1214.
The boost converter 1210 is configured to generate a main positive output voltage or potential VCC. The boost converter 1210 includes an auxiliary transformer TAUx, which has a first winding 1216 and a second winding 1218 and a core 1220 on which windings forming the first winding 1216 and second winding 1218 may be wrapped. The first winding 1216 acts as an inductor in the boost converter topology, with a first pole (pin 1) coupled to the output pin, terminal or node 1206 and a second pole (pin 2) coupled to the input pin, terminal or node 1202. The boost converter 1210 also includes a switch SAUX (e.g., transistor) operable in response to control signals from the feedback control circuit 1214 to selectively couple the first pole (pin 1) of the first winding 1216 to a ground reference GND. The boost converter 410 includes an output diode DAUX-OUT serially coupled to the first output pin, terminal or node 1206 to prevent current reversal. An output capacitor CAUX-OUT may be coupled between a ground reference GND and a node VOUTNCC between the output diode DAUX-OUT and the first output pin, terminal or node 1206 to provide output smoothing.
The charge pump circuit 1212 is configured to supply the negative output voltage or potential at the second output pin, terminal or node 1208, so may be denominated as the negative output voltage charge pump circuit. The charge pump circuit 1212 is coupled between a ground reference or potential GND and a node 1224 of the boost converter 1210 on a path to the ground reference or potential GND through the switch SAUX.
The feedback control circuit 1214 includes an error amplifier U1, supply voltage divider circuit 1226, current mirror circuit 1228 and drive/over voltage clamp circuit 1230.
The supply voltage divider circuit 1226 is formed of a pair of voltage divider resistors RD1, RD2, and coupled between an input line 1232 that carries the input voltage or potential VIN and a ground reference or potential GND. The error amplifier U1 receives a signal on a positive or non-inverting pin from the supply voltage divider circuit 1226 and receives a threshold signal VREF on a negative or inverting pin via a reference resistor RREF. The error amplifier U1 produces an output at an output pin, which is supplied to the voltage to current circuit 1228. The output of the error amplifier U1 is also fed back to the negative or inverting pin of the error amplifier U1 via a feedback capacitor CFB and feedback resistor RFB. The error amplifier U 1 receives supply voltages or potentials from a ground reference or potential GND and from the main positive supply bias voltage VCC of the boost converter 1210, at a node 1232 downstream or following the output diode DAUX-OUT.
The voltage to current circuit (V to 1) 1228 is coupled to receive the output of the error amplifier U1. The voltage to current circuit 1228 is also coupled to the input pin, terminal or node to receive the input voltage or potential VIN and the second pole (pin 2) of the first winding 1216. The voltage to current circuit is coupled to create current to a first pole (pin 3) of the second winding 1218 of the auxiliary transformer TAUX.

The drive/over voltage clamp circuit 1230 is coupled between the second pole (pin 4) of the second winding 1218 of the auxiliary transformer TAUx and the ground reference or potential GND. The drive/over voltage clamp circuit 1230 is coupled to provide control signals to control the switch SAUX, for example by supplying control signals to a gate thereof.
Figure 13 shows in more detail an implementation of the auxiliary power supply or very or ultra low input voltage regulated bias voltage supply 106 of Figure 12, according to one illustrated embodiment. As illustrated, the auxiliary power supply or very or ultra low input voltage bias voltage supply may employ less complex, and less costly discrete semiconductor components, chips resistors and capacitors, than employed by existing control circuitry.
Boost Converter Operation The boost converter 1210 (Figure 1) includes the auxiliary transformer TAUx, switch SAUX (Figure 1) in the form of a switching transistor Q32, VCC output diode CR34 and VCC output capacitor C30A. The boost converter 1210 generates or supplies the main output voltage or potential VCC
of the auxiliary power supply or voltage bias voltage supply 106.
The switching action of the boost converter 410 increases a positive output supply voltage or potential VCC to a level higher than the input voltage or potential VIN. The auxiliary power supply or bias voltage supply can operate at a very low input voltage or potential VIN, typically 1.5 to 2V, i.e., a voltage sufficient to power an operational amplifier (i.e., error amplifier) UA1.
The auxiliary transformer TAUx functions as a coupled inductor, which can be modeled as an ideal auxiliary transformer with a mutual inductance in parallel with the first winding 416, pin 1 to pin 2.
A switching cycle of the boost converter 1210 starts, assuming there is sufficient voltage on a drive capacitor C32 via current from a first mirror transistor Q30 of a pair of mirror transistors Q30, Q31 to turn ON the switching transistor Q32. The switching cycle begins with turn ON of the switching transistor Q32, during which the current in the mutual inductance of T1 increases linearly.
The first winding 416 and first winding 418 of the auxiliary transformer TAUx are magnetically coupled, thus any voltage drop created across the first winding 1216 will be reflected to the second winding 1218.
The first winding 1216 and second winding 1218 have a turns ratio. For a turns ratio of, for example 2:1, half of the voltage across the first winding 1216 will be reflected to the second winding 1218, from pin 3 to pin 4. The switching transistor Q32 is operable to selectively couple the first pole (pin 1) of the first winding 1216 to a ground reference GND.
The second winding 1218 transfers charge from the drive capacitor C32, thereby injecting current into a base of the switching transistor Q32 reinforcing the turn ON of the switching transistor Q32 (i.e., positive feedback). This drives the switching transistor Q32 hard into saturation and results in a negative voltage on drive capacitor C32. In response, charge current to the drive capacitor C32 decreases, and switching transistor Q32 turns OFF.
Once switching transistor Q32 turns OFF, the current in the mutual inductance of the auxiliary transformer TAUx continues to flow, decreasing linearly, through VCC output diode CR34, charging VCC output capacitor C30A and powering a load (not shown) coupled to receive the supply voltage or potential VCC. During the off time of the switching transistor Q32, the drive capacitor C32 charges again from the current source provide by the first voltage to current output Q30 to a level that again turns ON the switching transistor Q32 and the cycle repeats at a periodic rate. Stray capacitance across VCC output diode CR34 tends to cause the cycle to coincide with a dynamic load demand, forcing synchronization to occur. Thus, the parasitic capacitance across VCC output diode CR34, combined with substrate parasitic capacitance provides the synchronization capacitance Csyõ,_. In this case the VCC output diode CR34 may be implemented with a pair of diodes coupled in parallel with one another, thereby increasing this synchronization capacitance Csync.
The magnetizing current always falls to zero before the next switch cycle of the switching transistor Q32 and the boost converter 410 is always operating in the discontinuous current mode. For very light loads, the periodic switching can extend to very low rates.

Charge Pump The charge pump may be formed by a charge pump capacitor C34A, VSS output capacitor C34B and charge pump diodes CR32, CR33.
When the switching transistor Q32 turns OFF, the voltage at the first pole (pin 1) of the first winding 1216 of auxiliary transformer TAUx is equal to the positive bias or supply voltage or potential VCC plus the forward voltage drop Vd of the VCC output diode CR34 (VCC-Vd), charging the charge pump capacitor C34A through charge pump diode CR32 to approximately VCC.
When the switching transistor Q32 turns ON for the next on cycle, charge is transferred from charge pump capacitor C34A through VSS output diode CR33 charging the VSS output capacitor C34B toward a negative value. Current loading on the VSS output capacitor C34B will discharge the capacitor between charge cycles and reduce the average negative voltage. The average negative voltage on the VSS output capacitor C34B can be adjusted by selection of the capacitance values of the charge pump capacitor C34A and the VSS output capacitor C34B. The maximum unloaded negative value will track the peak positive supply voltage VCC to a max of approximately VCCpeak - Vicesat - Vdiode Bias Supply OVP

The bias supply may include an over voltage protection (OVP) circuit 1300 to shut the bias down if the supply voltage or potential VCC gets too high, or if the input voltage VIN gets too high. This OVP circuit may be formed by a network including a pair of OVP Zener diodes VR32, VR33, a pair of OVP resistors R30C, R30B, and an OVP transistor Q33. If the supply voltage or potential VCC or input voltage or potential VIN get too high (e.g., transient), Zener diode VR32 or Zener diode VR33 will conduct, turning ON
drive transistor Q33 which will short a base of the switching transistor 032 maintaining the switching transistor Q32 in an OFF or non-conducting state.
Voltage Loop Feedback and Bias Control The voltage feedback circuit 1214 may include an integration operational amplifier U1A to integrate the difference between the input voltage VIN and the reference threshold VREF over time, and associated resistors/capacitors. VCC voltage or potential is supplied to the positive power pin of the integration operational amplifier U1A and a ground reference or potential GND is supplied to a negative power pin of the integration operational amplifier UA1, providing power to the operational amplifier U1A. The supply voltage or potential VCC is divided by a ratio of resistances of a pair of VCC
divider resistors R38, R37, and coupled to the positive input pin of the integration operational amplifier U1A and compared to a threshold VREF
supplied at the negative input pin of the integration operational amplifier U1A.
A compensation network may be formed by compensation resistors R35, R36 and compensation capacitor C33, adjusted to provide an appropriate magnitude and phase frequency response in the voltage feedback control loop.
An output of the integration operational amplifier U1A controls the voltage to current circuit 1228. The voltage to current circuit 1228 may be formed by a resistor R34 and a pair of transistors Q31, 030. A base and a collector of the second mirror transistor 031 are commonly coupled, and a voltage drop across a second mirror resistor R32 is impressed across a first mirror resistor R31, assuming an emitter-to-base voltage of the second mirror transistor Q31 is equal to an emitter-to-base voltage of the first mirror transistor Q30. A current in a collector of the first mirror transistor Q30 is then proportional to a current in a collector of the second mirror transistor Q31, i.e., the current through operational amplifier output resistor R34 which is directly controlled by the output of the integration operational amplifier U1A. The collector the first mirror transistor Q30 is coupled to the first pole (pin 3) of the second winding 1218 and a reference or potential GND via a voltage divider formed by a pair of resistors R30, R30A, and a diode CR31.
The circuit polarity is configured to act as a negative feedback loop where if the output voltage or potential VCC drops, the voltage output of the integration operational amplifier U1A will drop, causing an output current from the collector of the voltage to current transistor Q30 to increase. This increase in collector current of the voltage to current transistor Q30 delivers more energy to drive capacitor C32, turning ON the switching transistor Q32 with more base charge available, thereby increasing the ON time of switching transistor Q32 to thereby deliver more energy to transistor Tv_c thereby completing the feedback path.
A feed forward voltage network may be formed by resistor R39 and capacitor C36 to feed-forward input voltage VIN from the input pin, terminal or note 1002. Such may advantageously decrease the response time of the boost converter 410 to changes in the input voltage VIN.
Figure 14 shows a method 1106 of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply 106 of Figures 1, 10-13, according to one illustrated embodiment.
At 1402, a converter switch increases a supply of current via to a first winding of an auxiliary transformer. Such may be in response to a charge of the drive capacitor increasing.
At 1404, in response to an increase current flow through first winding, the first winding reflects a corresponding voltage change to the second winding of the auxiliary transformer.
At 1406, in response to reflection of voltage change corresponding to increase current flow, the second winding increases a drive voltage to turn the converter switch full ON, as part of a positive feedback loop.

At 1408, the converter switch decreases a supply of current to the first winding of the auxiliary transformer. Such may be in response to a charge of the drive capacitor becoming depleted.
At 1410, in response to a decrease current flow through first winding, the first winding reflects a corresponding voltage change to the second winding of the auxiliary transformer.
At 1412, in response to reflection of voltage change corresponding to decrease current flow, the second winding decreases a drive voltage, to turn the converter switch OFF.
At 1414, a dynamic load current demand larger than a threshold is experienced.
At 1416, in response to dynamic load current demand larger than a threshold, a synchronization capacitance provides a voltage pulse to the first winding of the auxiliary transformer.
At 1418, the first winding reflects the voltage pulse to the second winding of the auxiliary transformer.
At 1420, the second winding of the auxiliary transformer applies the voltage pulse to turn converter switch ON.
At 1422, a drive charge pump coupled to first winding supplies a VSS supply potential to an output node.
Figure 15 shows a method 1500 of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply 106 of Figures 1, 10-13, according to one illustrated embodiment. The method 700 may be implemented as part of performing the method 1106 of Figure 14.
At 1502, an error circuit determines a difference between an output voltage and a reference voltage.
At 1504, the error circuit applies a signal to second winding of the auxiliary transformer based on determined difference to control the converter switch.
Figure 16 shows a method 1600 of operating the auxiliary power supply or very or ultra low input voltage bias voltage supply 106 of Figures 1, 10-13, according to one illustrated embodiment. The method 800 may be implemented as part of performing the method 1106 of Figure 14.
At 1602, an error circuit determines a time averaged difference of a sum of a VCC supply potential and a reference potential.
At 1604, the error circuit applies a signal to the second winding based on the determined time averaged difference to control the converter switch.
This structures and methods described herein allow generation of regulated bias supply voltages for a device using a complete, step up switch mode dc-dc power converter can generates multiple bias voltages include positive (+) and negative (-) bias voltages that are greater than an input voltage and suitable for powering internal circuitry of a device that operates at very or ultra low input voltages (e.g., < 2V). The structures and methods described herein are capable of generating bias voltages over a very wide temperature range and with a minimum number of parts. Traditional solutions incorporating linear regulator solutions as well as more complex circuitry solutions that provide regulated bias voltages are typically not able to operate at very or ultra low input voltages, are less efficient, and typically do not operate over as wide a temperature range.
Figure 17 shows an input control circuit 1700 which implements both the inrush control block 110 (Figure 1) and over voltage/under voltage monitor block 108 (Figure 1) to control a current flow on an input line 1702 between an input pin, terminal or node, an output pin, terminal or node, and an input or filter capacitor or capacitance Cin (e.g., bulk filter capacitor), according to one illustrated embodiment.
A primary function of the input control circuit 1700 is control of an inrush current that flows into the input capacitor or capacitance Cin at initial application of the input voltage or potential Vin, VIN COM, in order to maintain a defined current level. Secondary functions of the input control circuit 1700 include implementing enable functionality, under voltage lockout (UVLO) and/or over voltage lockout (OVLO) protection. The approaches described herein advantageously employ a signal that is a mirror or representation of actual input current to assess, monitor or otherwise reflect the inrush current to the input capacitor or capacitance Cin and control the same. The approaches described herein advantageously employ a signal that is inherently referenced to ground.
The input control circuit 1700 implements inrush current control via a switch SIN, a sense capacitor Csense, a clamp circuit 1708 and a current sense mirror circuit 1710.
The switch SIN is electrically coupled in series in the input line 1702 between the input pin, terminal or node 1704 and the output pin, terminal or node 1706. Hence, the switch SIN is interchangeably referred to herein and in the claims as series switch or series pass device. The switch SIN is operable in response to control signals to adjust or regulate a flow of current therethrough, on the input line 1702. For example, the switch SIN is not only operable to stop a flow of current, but may also linearly regulate the flow of current. The switch SIN may take a variety of forms, suitable for handling expected currents, voltages or power levels on the input line 1702. For example, the switch SIN may take the form of a metal oxide semiconductor field effect transistor (MOSFET), for instance a P-Channel MOSFET as illustrated in Figure 2.
The sense capacitor Csense is electrically coupled in parallel with the input capacitor Cin, between the input line 1702 and a ground reference GND via the current sense mirror circuit 1710. Thus, the same voltage appears across the two capacitors Csense, Cin. Consequently, the current that charges the sense capacitor Csense is proportional to the current that charges the input capacitor Cin. The charge current in either of the capacitors Csense, Cin can be described by the fundamental relation:
I=C*dv/dt.
For each of the capacitors Csense, Cin, the fundamental current (l) versus voltage (V) equation is:

I Csense=Csense*dv/dt lCin=Cin*dv/dt.

Given that the change in voltage or potential with respect to time (dv/dt) for the two capacitors Csense, Cin is the same, the relationship that defines the proportionality constant between the charge currents of the two capacitors Csense, Cin is:

lin=lsense *Cin/Csense.

From this relation it can be seen that the charge or inrush current in the input capacitor Cin can be controlled by sensing and controlling the charge current of the sense capacitor Csense. The ratio of capacitances of the input capacitor Cin and sense capacitor Csense (i.e., Cin/Csense) may take on a large variety of values, possibly with no minimum assuming low leakage capacitors are employed. In this respect, it is noted that any leakage in the sense capacitor Csense would form an error term, limiting the value of the sense capacitor Csense. In an example, input capacitor Cin may have a capacitance of about 220uF, while the sense capacitor Csense has a capacitance of about 0.018uF; a difference of more than 4 decades. It is further noted that the ratio Cin/Csense could be limited in the current sense mirror implementation illustrated in Figure 3.
The current sense mirror circuit 1710 is coupled to the sense capacitor Csense to sense the current in the sense capacitor Csense. The current sense mirror circuit 1710 mirrors or produces a signal that is indicative of or represents the sensed current.
The clamp circuit 1708 is coupled to control the series switch SIN.
For example, the clamp circuit 1708 may be coupled to supply control signals to a gate of the series switch SIN. As is made clear below, the clamp circuit is responsive to signals from various components of the inrush control circuitry 110, including the sense current mirror 1710. Thus, the clamp circuit 1708 may generate, produce or supply control signals to linearly regulate the flow of current through the series switch SIN to maintain a constant value based on the sensed current of the sense capacitor Csense.
The only prerequisite is that the series switch SIN be ON or CLOSED at the instant of application of the input voltage or potential Vin (i.e., turn ON). This ensures sufficient initial charge current in the sense capacitor Csense to provide a feedback input into the current sense mirror circuit 1710 to start the inrush control process. Once sufficient current in the sense capacitor Csense is present, the startup sequence continues with the current sense mirror circuit 1710 controlling the clamp circuit 1708 to continue holding a voltage or potential at a gate of the series switch SIN at a level that maintains a constant inrush charge current to the input capacitor or capacitance Cin.
The input control circuit 1700 optionally includes one or more of an over voltage lockout(OVLO) monitor circuit 1712 to implement OVLO
monitoring and control, Under voltage lockout (UVLO) monitor circuit 1714 to implement UVLO monitoring and control, and/or enable signal monitor circuit 1716 to implement enable signal monitoring and control. These circuits 1712, 1714, 1716 may be coupled to the clamp circuit 1708 to control the series switch SIN.
The OVLO monitor circuit 1712 is coupled to the input line 1702 and is operable to detect occurrences of over voltage conditions on the input line 1702. Thus, the OVLO monitor circuit 1712 may compare an actual voltage or potential on the input line 1702 to a threshold voltage or potential that is indicative to an over voltage condition. In response to detection of an over voltage condition, the OVLO monitor circuit 1712 provides a signal to the clamp circuit 1708, to cause the clamp circuit 1708 to cause the serial switch SIN
to turn OFF or OPEN, stopping the flow of current therethrough until the over voltage condition can be remedied.
The UVLO monitor circuit 1714 is coupled to the input line 1702 via an under voltage monitor resistor R1 and is operable to detect occurrences of over voltage conditions on the input line 1702. The UVLO monitor circuit 1714 may include a comparator UIN which compares the voltage or potential on the input line 1702 to a threshold voltage or potential VREF that is indicative to an under voltage condition. In response to detection of an under voltage condition, the UVLO monitor circuit 1714 provides a signal to the clamp circuit 1708, to cause the clamp circuit 1708 to cause the serial switch SIN to turn OFF

or OPEN, stopping the flow of current therethrough until the under voltage condition can be remedied.
The enable signal monitor circuit 1716 may receive an enable signal Enable which is indicative of one of two states (e.g., HIGH, LOW) which may be denominated respectively as enable and disable. The enable signal monitor circuit 1716 may apply the enable single to the clamp circuit 1708, for example via the comparator U. For example, the enable signal monitor circuit 1716 may apply the enable signal to a positive or non inverting pin of the comparator U. The state of the enable signal may be summed with the threshold voltage or potential VREF. Thus, an output of the comparator UIN
may not trigger the clamp circuit 1708 unless either: 1) the state of the enable signal is LOW (e.g., disable) or the input voltage or potential is below the threshold voltage or potential VREF (i.e., under voltage condition exists). As illustrated, the UVLO monitor circuit 1714 and enable signal monitor circuit 1716 may share components (e.g., comparator U), and/or be combined as an Enable/UVLO monitor circuit.
Thus, the clamp circuit 1708 responds to three independent signal inputs. The first input is from the Enable/ UVLO comparator U, which controls the series switch SIN to turn ON power to the output 1706 if the enable signal Enable is true or HIGH and if the input voltage or potential VIN is above the UVLO threshold for operation VREF. The second input is from the current sense mirror circuit 1710 which controls the series switch SIN to maintain a constant input charge current to the input or filter capacitor or capacitance Cin as described above. The third input is from the OVLO monitor circuit 1712 that turns OFF the series switch SIN at the instant the input voltage or potential VIN
increases above a predetermined level to protect the powered output circuitry.
Figure 3 shows the input control circuit 1700 of Figures 1 and 2 in even more detail, operating to control a current flow on the input line 1702 between the input pin, terminal or node 1704 and the output pin, terminal or node 1706, and the input or filter capacitor or capacitance C1A, according to one illustrated embodiment. As illustrated, the input control circuit 1700 may employ less complex, and less costly discrete semiconductor components, chips resistors and capacitors, than employed by existing control circuitry.
Inrush control The inrush control function may be implemented by a series switch such a series pass device or transistor QIN (e.g., P- channel MOSFET), a clamp circuit 1708 including a switch controlling transistor Q4 (e.g., PNP
transistor) coupled to control a gate-to-source voltage of the series pass device or transistor QIN, a sense capacitor or capacitance C3 and a current sense mirror circuit 1710 to sense current or charge in the sense capacitor or capacitance C3. As noted the series pass device or transistor QIN is couple in series in the input line 1702 and operable to regulate current therethrough. A
gate of the series pass device or transistor QIN is coupled to the input line via a capacitor C4 and to a voltage or potential supply source VSS through a supply resistor R9.
The clamp circuit 1708 initiates a start up sequence turn ON of the series pass device or transistor QIN based on a state of the enable signal Enable, and the UVLO and OVLO functions described below. Once series pass device or transistor QIN starts to turn ON, the sense capacitor or capacitance C3 and input or filter capacitor or capacitance CIA start to charge.
Any current passing through the sense capacitor or capacitance C3 will have to pass through a first mirror transistor QM2 and a first mirror resistor R11 coupled to a ground reference GND. Higher current through the first mirror resistor creates a larger voltage drop across the first mirror resistor R11, which is reflected to a second mirror resistor R8, thus increasing current through a second mirror transistor QM7. As current through the second mirror transistor QM7 increases, a voltage drop across R14 becomes sufficient to turn ON the switch controlling transistor Q4. The turning ON of the switch controlling transistor Q4 starts the turning OFF of the series pass device or transistor QIN.
The turning OFF of series pass device or transistor QIN adjusts (e.g., slows) the voltage change (dv/dt) across the sense capacitor or capacitance C3, and thus reduces the current change (di/dt) through the sense capacitor or capacitance C3 and the input or filter capacitor or capacitance C1A. This negative feedback will keep the series pass device or transistor QIN operating in the linear region, providing the desired voltage change (dv/dt) across the sense capacitor or capacitance C3 to provide negative feedback to the current mirror controlling the voltage change (dv/dt) across the sense capacitor or capacitance C3.
Since the sense capacitor or capacitance C3 and the input or filter capacitor or capacitance CIA are in parallel, control over the sense capacitor or capacitance C3 will also control the voltage change (dv/dt) and thus the current change (di/dt) through the input or filter capacitor or capacitance C1A.
A pair of trickle bias resistors R10, R15 provide initial trickle bias current for the mirror transistors QM2, QM7. A speedup diode CR4 and speedup resistor R3 provide a low impedance charge path to speed up the turn ON of the switch controlling transistor Q4. The speedup resistor R3 is typically a factor of 10 to 100 times smaller in resistance value than the OVLO resistor R14. OVLO resistors R12, R14 and Zener diode VR3 implement the OVLO
function as described below.

Over voltage Lockout The OVLO threshold voltage or potential is set above the desired operating voltage range of the powered circuitry. At an input voltage or potential VIN above the normal operating voltage range but just below the OVLO threshold, a base-emitter voltage of switch controlling transistor Q4 increases, slightly turning the switch controlling transistor Q4 ON, but not hard enough to short the gate of the series pass device or transistor Q. Further increases in the input voltage or potential VIN causes the current sense mirror circuit 1710 to draw more current, and will cause the OVLO Zener diode VR3 to conduct more. Both of these effects turn the switch controlling transistor Q4 ON harder. At the prescribed OVLO threshold, current through the OVLO
Zener diode VR3 will increase very rapidly, dropping more voltage across the OVLO resistors R14, R12. Once the voltage across a first one of the OVLO

resistors R14 is around 0.65V, depending on temperature, the voltage will cause the switch controlling transistor Q4 to turn ON, which will in cause the series pass device or transistor QIN to turn OFF, cutting off power to the output pin, terminal, or node 1706. Reducing the input voltage or potential VIN down to within the normal operating voltage range reduces a voltage across the first OVLO resistor R14, causing the switch controlling transistor Q4 to turn OFF, and allowing the series pass device or transistor QIN to turn ON, starting a startup sequence.

Enable The enable functionality or inhibit action is implemented via an enable/ULVO transistor Q3, enable/ULVO operational amplifier U2B, enable/ULVO resistors R4, R5, R7. With the enable pin or terminal 1720 floating or pulled HIGH, the enable/ULVO transistor Q3 is turned OFF setting a voltage or potential at a negative input or pin of the enable/ULVO operational amplifier U2B equal to the input voltage or potential VIN. The voltage or potential at a positive input or pin of the enable/ULVO operational amplifier will be equal to the reference voltage or potential VREF (e.g., 2.5V). With the negative input or pin of the enable/ULVO operational amplifier U2B higher than the positive input or pin thereof, the output of the enable/ULVO operational amplifier U2B will be LOW and not affect the status of series pass device or transistor QIN. The series pass device or transistor QIN is then controlled by the UVLO function during power ON startup or by the OVLO function during an input voltage or potential VIN over voltage condition.
Pulling the enable pin to LOW effectively ties the emitter of the enable/ULVO transistor Q3 to ground, causing the enable/ULVO transistor Q3 to turn ON and saturate. With the enable/ULVO transistor Q3 saturated, its collector voltage will be slightly lower than its base voltage. This causes an output of the enable/ULVO operational amplifier U2B to go HIGH, providing current through enable/ULVO diode CR3 to turn the mirror transistors QM2, QM7 ON hard enough to cause the switch controlling transistor Q4 to turn ON. With the switch controlling transistor Q4 ON, the gate-to-source voltage of the series pass element or transistor QIN is shorted, and the series pass element or transistor QIN will turn OFF, interrupting power flow.

Under voltage Lockout The threshold VREF of the UVLO circuit 1714 is set to be triggered by an input voltage or potential VIN less than a desired operating voltage. When the input voltage or potential VIN is at or below the UVLO
threshold VREF, the negative input or pin of the enable/ULVO operational amplifier U2B will be at a lower voltage than the threshold VREF and lower than a voltage or potential at the positive input or pin of the enable/ULVO
operational amplifier U2B. This causes output of the enable/ULVO operational amplifier U2B to go HIGH providing current through enable/ULVO diode CR3 to turn ON
the mirror transistors QM2, QM7 hard enough to cause the switch controlling transistor Q4 to turn ON. With the switch controlling transistor Q4 ON, the gate-to-source of the series pass device or transistor QIN is shorted, keeping the series pass device or transistor QIN OFF and interrupting power flow.
Increasing the input voltage or potential VIN to within a normal operating input voltage range results in the negative input of the enable/ULVO
operational amplifier U2B at a higher voltage than the threshold VREF, the voltage or potential at the positive input or pin of the enable/ULVO
operational amplifier U2B. This causes the output of the enable/ULVO operational amplifier U2B to go LOW causing the switch controlling transistor Q4 to turn OFF. With the switch controlling transistor Q4 OFF, the voltage on the gate of the series pass device or transistor QIN is pulled to negative supply voltage VSS, turning on the series pass device or transistor QiN, and starting a startup sequence.
Operation of the above described circuit functions is predicated on the presence of bias voltages or potentials, positive supply voltage or potential VCC and negative supply voltage or potential VSS at or below the UVLO
threshold VREF.

Figure 19 shows a flow diagram of a method 1900 of operating the input control circuit 110/108, 1700 of Figures 1, 17-18, according to one illustrated embodiment.
At 1902, an input line 1702 receives input current VIN at an input terminal, pin or node 1704. The input voltage or potential VIN may be the input voltage supplied to the power converter 100 (Figure 1) from some upstream component. For example, the input voltage or potential VIN may be supplied to the power converter from a rectifier, a DC/DC converter, an isolating converter stage, and/or a DC electrical power storage device such as an array of chemical battery cells or ultra-capacitors.
At 1904, the sense capacitor Csense (Figure 2), C3 (Figure 3) capacitively produces a signal proportional to input current by charging from the input current. At 1906, a current sense mirror circuit mirrors the signal proportional to input current.
At 1908, a switch SIN (Figure 17), series pass device or transistor (Figure 3) adjusts a flow of input current through the input line 1702 in response at least to the signal that is proportional to the input current.
At 1910, an OVLO monitor circuit 1712 monitors for an over voltage condition on the input line 1702. At 1912, the OVLO monitor circuit 1712 determines If an over voltage condition occurred. If an over voltage condition has occurred, then the OVLO monitor circuit provides a signal to a clamp circuit 1708 at 1914 that causes the switch SIN, series pass device or transistor QIN to stop a flow of input current through the input line 1702.
Control may then return to 402. If an over voltage condition has not occurred, control passes directly to 416.
At 1916, an UVLO monitor circuit 1714 monitors for occurrence of an under voltage condition on the input line 1702. At 1918, the UVLO monitor circuit 1714 determines whether an under voltage condition has occurred. If an under voltage condition has occurred, then the UVLO monitor circuit 1714 provides a signal to the clamp circuit 1708 at 1920 that causes the switch SIN, series pass device or transistor QIN to stop a flow of input current through the input line 1702. Control may then return to 1902. If an under voltage condition has not occurred, control passes directly to 1922.
At 1922, an enable circuit 1716 monitors an enable line ENABLE
for enable signals. At 1924 the enable circuit 1718, comparator UIN or operational amplifier U2B determines If the enable signal indicates a disable state. If the enable signal indicates a disabled state, then at 1926 the enable circuit 1716, comparator UIN or operational amplifier U2B provide a signal to the clamp circuit 1708 that causes the switch SIN, series pass device or transistor QIN to stop a flow of current in the input line 1702. Control may then return to 1902.
At 1928 the enable circuit 1718, comparator UIN or operational amplifier U2B determines If the enable signal indicates an enable state. If the enable signal indicates an enable state, then at 430 the enable circuit 1716, comparator UIN or operational amplifier U2B provides a signal to that causes the under voltage lockout circuit 1714 to function.
The method 1900 may repeat while the power converter 100 is operational, the oscillation circuit 114 continually generating, producing or supplying the oscillation ramp signal VRAMP. Typically, most of these operations or acts will be execute concurrently and fairly continuously by the circuitry.
Figure 20 shows a method 2000 of operating the input control circuit 110/108, 1700 of Figures 1, 17-18, according to one illustrated embodiment. The method 500 may be implemented as part of performing the method 1900 of Figure 19.
At 2002, a sense capacitor Csense coupled in parallel with an input or filter capacitor or capacitance CIN, C3 between input line 1702 and ground GND to be charged by input current is allowed to charge by an input current carried by the input line 1702.
At 2004, a signal is supplied from a clamp circuit 1708 to a switch SIN, series pass device or transistor QIN electrically coupled in series on input line 1702. The signal may cause the switch SIN, series pass device or transistor QIN to turn ON, allow current to pass on the input line 1702, or turn OFF and thereby preventing input current from being supplied to the input or filter capacitor or capacitance CIN, C3.
Figure 21 shows the oscillator 114, according to one illustrated embodiment.
The oscillator 114 includes a ramp resistor Rramp, timing capacitor Ct, comparator Uo, input voltage divider 204 and reset switch SR.
The oscillator 114 may include a buffer 131 to buffer an output signal VRAMP to provide drive capability. The input voltage divider 2104 is formed of two resistors Rdiv1, Rdiv2 coupled between the input voltage VSW and a ground GND. The input voltage divider 2104 produces a signal indicative of or proportional to the input voltage VSW. The comparator Uo is coupled to receive the signal indicative of the input voltage VSW from the input voltage divider 2104. The comparator Uo is also coupled to receive a signal from the timing capacitor Ct indicative of a voltage or electrical potential thereof.
The comparator Uo is further coupled a supply voltage or potential VCC and ground reference or potential GND. The oscillator 114 receives an input voltage or potential VSW at an input voltage input pin, terminal or node 2106. The oscillator 114 is guaranteed to start with application of the input voltage or potential VSW at the input voltage input pin, terminal or node 2106.
A basic timing sequence of the oscillator 114 includes charging of timing capacitor Ct toward the input voltage or potential VSW. Once the voltage of the timing capacitor Ct reaches the voltage of the input voltage divider 2104, the comparator Uo turns ON the reset switch SR, discharging the timing capacitor Ct. The basic timing sequence repeats at a periodic rate or natural or self oscillating frequency of the oscillator 114.
The oscillator 114 also includes synchronization circuitry including a synchronization capacitor Csync, synchronization resistors Rsyncl, Rsync2, and steering logic 208. The steering logic may include AND circuitry UA to implement an AND function or operation and OR circuitry Uc to implement a OR
function or operation. The synchronization circuitry may receive a synchronization input signal Sync In at a synchronization signal input pin, terminal or node 2114. A first one of the synchronization resistor Rsyncl is coupled between the input voltage input pin, terminal or node 2106 and the synchronization input pin, terminal or node 2114. A second one of the synchronization resistor Rsync2 is between ground and a node 2116 between the synchronization capacitor Csync and part of the OR circuitry Uc steering logic 208.
The synchronization input signal Sync In causes the oscillator 114 to synchronize a frequency of the oscillator 114 to a pulse frequency either below or above the self oscillating frequency of the oscillator 114 without synchronization. The oscillator 114 is capable of locking synchronization, for example with a pulse frequency up to 1 Megahertz. Thus, synchronization signal affects the basic timing sequence of the oscillator.
In particular, the AND circuitry UA and OR circuitry Uc are coupled to cause an early discharge of the timing capacitor Ct in response to the synchronization signal indicating that a higher frequency is required to synchronize (e.g., rising pulse edge), and to delay discharge of the timing capacitor Ct in response to the synchronization signal indicating that a lower frequency is required to synchronize (e.g., logic low). The logic is reflected in Table A, below.

Sync In VCT = Discharge Comment VSW? Ct?
0 0 0 Not ready for discharge.
0 1 0 Delay discharge to decrease frequency Rising 0 1 Early discharge to increase frequency 1 1 1 On time discharge, maintain frequency Table A

Figure 22 shows the oscillator 114, according to one illustrated embodiment. As illustrated, the oscillator 114 may employ less complex, and less costly discrete semiconductor components, chips resistors and capacitors, than employed by existing oscillators.
A capacitor C52 functions as the timing capacitor Ct (Figure 21) that is charged through series resistors R54 and R54A which are equivalent to Rramp. The voltage on capacitor C52 initially charges from ground, exponentially toward the input voltage or potential VSW. The comparator Uo (Figure 21) is formed by a differential pair of transistors (i.e., first comparator transistor Q51 and second comparator transistor Q52), with a base of the second comparator transistor Q52 acting as the non-inverting input and a base of the first comparator transistor Q51 acting as the inverting input. Emitters of the first and the second comparator transistors Q51, Q51 are coupled to a voltage or potential supply VCC via voltage supply resistor R58A and comparator resistor R53. The input voltage divider 204 (Figure 21) is formed by a pair of resistors R51, R52, which receive the input voltage or potential VSW
via resistor R50, and which set a comparison threshold on the base of the first comparator transistor 051. The basic timing of the oscillator is governed by the following equations:
Ts = R*C* In[ I-F / R(t) - F ]
Fs = 1/'Fs where:
I = initial capacitor voltage F = final capacitor voltage R(t) = comparator threshold.
If:
F=VSW
R(t) = K=VSW
1=0 Ts = R*C* ln[0-VSW/K-VSW-VSW) Ts = R*C* ln[1/1-K) Thus, frequency is not dependent on input voltage VSW.

The timing sequence for the oscillator 114 starts at application of the input voltage or potential VSW, with the timing capacitor C52 charging up to the comparator threshold, at which point the second comparator transistor Q52 turns OFF and the first transistor Q51 turns ON and starts conducting current.
This current generates a voltage across a resistor R55 large enough to charge a capacitor C51 via a control transistor Q50 and turn ON a reset or discharge controlling transistor Q54. The current used to charge capacitor C51 flows through the collector of the control transistor Q50 to develop a voltage across diode CR53 and control transistor Q50. This reduces the threshold voltage at the base terminal of transistor Q51 to enhance the transition. The reset or discharge transistor Q54 functions as a voltage clamp that discharges the capacitor C52 to close to zero volts, as this occurs, a discharge termination transistor Q55 removes any residual charge stored at the base node of the control transistor Q50 .
A diode CR50 level shifts resistor R55 up one diode junction, reducing the voltage across resistor R55 that is required to turn ON the control transistor Q50, and improving the speed of the overall circuit. Once capacitor C51 discharges through resistor R56 and reset transistor Q54 via a reset resistor R57, the reset transistor Q54 turns OFF, allowing the capacitor C52 to charge again, thereby starting a new timing sequence or cycle.
The buffer amplifier 131 is implemented an emitter follower buffer amplifier by a buffer transistor Q53 and buffer resistor R58, to provide a low source impedance driver capable of driving next stage circuitry. The buffer transistor Q53 is coupled between the buffer transistor Q53 and a ground. The buffer resistor R58 is coupled to a supply voltage or potential VCC and supply voltage resistor R58A, and a ground via a capacitor C53.

The oscillator circuit 114 implements a function whereby a slope of the voltage across capacitor C52 is modulated proportional to a change in the input voltage or potential VSW. In power supply converters, this type of feature is typically referred to as voltage feed-forward, and substantially improves the line regulation performance of the power converter and reduce changes in the output voltage or potential as a result of changes in the input voltage or potential VSW. A power converter without an oscillator that incorporates voltage feed-forward has degraded input line regulation performance since a change in input voltage or potential must propagate to the output of the converter before the feedback control loop can compensate for the input voltage change.
The desired functionality is implemented in the oscillator 114 by making the voltage threshold of the comparator (i.e., Q51, Q52) proportional to the input voltage or potential VSW by tying the resistor R51 of the voltage resistor divider to the input voltage or potential VSW of the power converter.
A
temperature compensation resistor R51A provides temperature compensation to the VSW derived voltage or potential.
A logic network comprised of synchronization logic resistors R59, R59A, synchronization logic diodes CR52, CR51 and synchronization logic capacitor C50 perform two functions. First, in the case where a frequency of the synchronization signal Sync In is higher than a natural or self frequency of the oscillator circuit 114, a rising pulse at the synchronize input pin, terminal or node 214 will capacitive couple enough charge through synchronization logic capacitor C50 and first synchronization logic diode CR51 to turn on the control transistor Q50 earlier than might be determined by the timing of the capacitor C52. This will terminate the timing charge sequence of the capacitor C52 early, effectively increasing the oscillator frequency of operation. Second, in the case where a frequency of the synchronization signal Sync In is lower than the natural frequency of the oscillator circuit, a low voltage of the pulse at the synchronize input pin, terminal or node 214 through the second synchronization logic diode CR52 will hold off or delay the reset (i.e., discharging) of the capacitor C52, effectively lowering the oscillator frequency of operation.
The illustrated oscillator circuit 114 may be capable of operation up to, for example 1 MHz. Such high speed operation is accomplished via use of a differential transistor pair topology, optimized to minimize all voltage transitions and advantageously employing a minimum number of components.
The above described oscillator designs implement slope modulation, self starting operation, synchronization, wide frequency and wide temperature range of operation. The oscillator design of Figure 22 incorporates all these features without the use of complex integrated circuits. Rather, the oscillator design implements all of the desired features with simple, low cost devices while maintaining the desired performance over wide temperature and operating conditions. Designs utilizing complex integrated circuits tend to be more costly, require substantially more parts, and do not appear capable of operating over as wide a frequency range and temperature range.
Figure 23 shows a flow diagram of a method 2300 of operating the oscillator 114 of Figures 1, 21-22, according to one illustrated embodiment.
At 2302, an oscillator circuit 114 receives an input voltage or potential signal VSW at an input voltage input pin, terminal or node 206. The input voltage or potential signal may be the input voltage or potential supplied to the power converter 100 (Figure 1) from some upstream component. For example, the input voltage or potential may be supplied to the power converter from a rectifier, a DC/DC converter, an isolating converter stage, and/or a DC
electrical power storage device such as an array of chemical battery cells or ultra-capacitors.
At 2304, the oscillator circuit 114 receives a synchronizing signal Sync In at a synchronization signal input pin, terminal or node 2114. For example, a synchronizing signal Sync In may come from another power converter coupled in parallel with the power converter 100 (Figure 1) to a common load and operating as either a master or a slave in a current sharing arrangement to supply current to the common load.

At 2306, a ramp timing capacitor Ct (Figure 21), C52 (Figure 22) is charged through a ramp timing resistance Rramp, R54, R54A using the voltage or potential input VSW.
At 2308, a voltage divider 2104 (Figure 21), R51, R52 (Figure 22) produces a discharge trigger reference voltage. The discharge trigger reference voltage may be proportional to a voltage or potential of the input voltage signal VSW.
At 2310, a comparator Uo determines whether a voltage of the ramp timing capacitor Ct (Figure 21), C52 (Figure 22) is equal to the discharge trigger reference voltage. As noted, a differential pair of transistors Q51, (Figure 22) may be advantageously employed to perform the comparison.
If the voltage of the ramp timing capacitor C52 is equal to the discharge trigger reference voltage, then at 2312 logic circuitry 208 (Figure 21) determines if a state of a synchronization signal Sync In indicates that frequency needs to be increased. As explained above, a logic network (Figure 22) comprised of synchronization logic resistors R59, R59A, synchronization logic diodes CR52, CR51 and synchronization logic capacitor C50 may advantageously implement the logic without the need for complicated integrated circuits.
If the synchronization signal Sync In indicates that the frequency needs to be increased, then discharging circuitry discharges the ramp timing capacitor Ct (Figure 21), C52 (Figure 22) at 2314. The discharging circuitry may include switch SR (Figure 21) coupled to ground or reset transistor Q54 (Figure 22) coupled to ground.
If the synchronization signal Sync In indicates that the frequency needs to be decreased, then discharging of the ramp timing capacitor is delayed at 2316. As explained above, such may be delay via a falling pulse applied to the control transistor Q50 (Figure 22) via synchronization logic diode CR52.
If the voltage of the ramp timing capacitor C52 is equal to the discharge trigger reference voltage, then at 2318 the logic circuitry determines whether the synchronization signal Sync In indicates that the frequency needs to be increased.
If the synchronization signal Sync In indicates that the frequency needs to be increased, then discharging circuitry discharges the ramp timing capacitor Ct (Figure 22), C52 (Figure 22) at 2320.
If the synchronization signal Sync In indicates that the frequency does not need to be increased, then at 422 the discharging circuitry does not discharge the ramp timing capacitor Ct (Figure 21), C52 (Figure 22).
At 2324, a buffer amplifier 131 buffers an output voltage signal VRAMP. As illustrated in Figure 22, the output voltage signal VRAMP may be buffered by an emitter follower buffer amplifier having a discrete buffer transistor Q53 and buffer resistor R58.
The method 2300 may repeat while the power converter 100 is operational, the oscillation circuit 114 continually generating, producing or supplying the oscillation ramp signal VRAMP.
Figure 24 shows a method 2400 of operating the oscillator 114 of Figures 1, 21-22, according to one illustrated embodiment. The method 2400 may be implemented as part of performing the method 2300 of Figure 23. In particular, the method 2400 specifies how the voltage at the ramp timing capacitor Ct (Figure 21), C52 (Figure 22) may be compared to the discharge trigger reference voltage.
At 2402, a discharge trigger reference voltage is supplied to a first comparator transistor Q51 of a differential pair of transistors. For example, the supply discharge trigger reference voltage from an input voltage divider R51, R52 (Figure 22) may be supplied to a base of the first comparator transistor Q51, which has an emitter commonly coupled with an emitter of a second comparator transistor Q52.
At 2404, a voltage across ramp timing capacitor Ct (Figure 21), C52 (Figure 22) is supplied to the second comparator transistor Q52 of the differential pair of transistors. For example, the ramp timing capacitor voltage or potential may be supplied to a base of the second comparator transistor Q52.
Figure 25 shows a method 2500 of operating the oscillator 114 of Figures 1, 21-22, according to one illustrated embodiment. The method 2500 may be implemented as part of performing the method 2300 of Figure 23. The method 2500 may determine whether to trigger discharging of the ramp timing capacitor Ct (Figure 21), C52 (Figure 22) when the value of the ramp timing capacitor voltage is equal to the discharge trigger reference voltage.
At 2502, a synchronization signal Sync In is supplied to a logic network (e.g., synchronization logic resistors R59, R59A, synchronization logic diodes CR52, CR51 and synchronization logic capacitor C50 of Figure 22).
At 2504, discharging of ramp timing capacitor Ct (Figure 21), C52 (Figure 22) is triggered via the first synchronization diode CR51 in response to a state of the synchronization signal indicating that frequency needs to be increased (e.g., rising edge of pulse of synchronization signal Sync In).
At 2506, discharging of ramp timing capacitor Ct (Figure 21), C52 (Figure 22) is suppressed via the second synchronization diode CR52 in response to a state of the synchronization signal indicating that frequency needs to be decreased (e.g., falling edge of pulse of synchronization signal Sync In). Such may be suppressed even though the normal discharging triggering condition of ramp timing capacitor voltage being equal to the discharge trigger reference voltage is satisfied.
Figure 26 shows a method 2600 of operating the oscillator 114 of Figures 1, 21-22, according to one illustrated embodiment. The method 2600 may be implemented as part of performing the method 2300 of Figure 23. For example, the method 2600 may be employed to produce, generate or supply a discharge trigger reference voltage that is proportional to a voltage or potential of the input voltage signal.
At 2602, an input voltage resistor divider network 2104 (Figure 21) R51, R52 (Figure 22) divides an input voltage signal VSW to produce a proportional signal.

At 2604, a temperature compensation resistor R51A compensates the divided input voltage signal for variations in temperature.
The described oscillator circuit 114 may provide an oscillating ramp signal where a slope of the ramp is modulated in response to an externally applied signal. Such may have linearity over a wide range of operating frequencies and/or temperatures. The described oscillator circuit may allow synchronization with an externally applied synchronization signal.
Such may be advantageously implemented using relatively simple and inexpensive components.
The described power converters 100 may provide a high-reliability, high-efficiency point of load converter, for example, for use with a 3.3 VDC input bus or a 5.0 VDC input bus. The power converters 100 include under voltage shutdown below 3.0 VDC and an over voltage shutdown above 6.0 VDC features to protect the powered system. The power converters 100 may have the flexibility to be set for any output voltage or potential within a specified range, for example from 0.64 VDC to 3.5 VDC without the need for any external components to achieve all specified performance levels. The power converters 100 may be capable of withstanding up to a 15 V transient for up to 1 second.
The described power converters 100 may have an accurate current overload feature to protect the power converter unit and load in critical fault conditions and improve system reliability. The described power converters 100 may also include a current share feature that allows multiple DC/DC power converters 100 to supply current to a single or common load, while maintaining a regulated voltage across the load. Total maximum output current in the share configuration is the sum of the maximum current provided by each individual power converter.
The specific values, such as specific voltages or potentials, used herein are purely illustrative, and are not meant to be in anyway limiting on the scope. Likewise, the arrangements and topologies are merely illustrative and other arrangements and topologies may be employed where consistent with the teachings herein. While specific circuit structures are disclosed, other arrangements that achieve similar functionality may be employed. The terms switched mode and switch mode are used interchangeable herein and in the claims.
The methods illustrated and described herein may include additional acts and/or may omit some acts. The methods illustrated and described herein may perform the acts in a different order. Some of the acts may be performed sequentially, while some acts may be performed concurrently with other acts. Some acts may be merged into a single act through the use of appropriate circuitry. For example, compensation and level shifting may be combined.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, including but not limited to commonly assigned U.S. patent applications:
Serial No. _/ , titled "POWER CONVERTER
APPARATUS AND METHOD WITH COMPENSATION FOR LIGHT LOAD
CONDITIONS" (Atty. Docket No. 480127.408);
Serial No. _/ , titled "SELF SYNCHRONIZING POWER
CONVERTER APPARATUS AND METHOD SUITABLE FOR AUXILIARY BIAS
FOR DYNAMIC LOAD APPLICATIONS" (Atty. Docket No. 480127.409);
Serial No. _/ , titled "INPUT CONTROL APPARATUS
AND METHOD WITH INRUSH CURRENT, UNDER AND OVER VOLTAGE
HANDLING" (Atty. Docket No. 480127.410);
Serial No. / , titled "POWER CONVERTER
APPARATUS AND METHOD WITH COMPENSATION FOR CURRENT
LIMIT/CURRENT SHARE OPERATION" (Atty. Docket No. 480127.411); and Serial No. / , titled "OSCILLATOR APPARATUS AND
METHOD WITH WIDE ADJUSTABLE FREQUENCY RANGE OSCILLATOR

APPARATUS AND METHOD WITH WIDE ADJUSTABLE FREQUENCY
RANGE" (Atty. Docket No. 480127.412);
all filed on July 18, 2011, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. A method of operating a first switch mode power converter having a synchronous buck converter circuit that includes a transformer having a swinging choke, a high side active switch operable to selectively coupled a portion of the transformer to an input terminal and a low side active switch operable to selectively coupled the portion of the transformer to a ground reference, the method comprising:
sensing an output current of the synchronous buck converter circuit with reference to the ground reference of the synchronous buck converter circuit over only a portion of a waveform of the output current;
compensating a sensed current signal that is proportional to the sensed output current at least for any variation in a duty cycle of a portion of the synchronous buck converter circuit of the first switch mode power converter;
averaging a signal that is at least proportional to a compensated sensed current signal to produce an averaged signal;
during a first portion of a cycle causing the high side active switch to electrically pass current from the input terminal to an output terminal through the swinging choke to vary an inductance of the swinging choke; and during a second portion of the cycle causing the low side active switch to electrically pass current through the swinging choke to the ground reference, wherein an inductance of the swinging choke varies over the cycle.

2. The method of claim 1, further comprising:
level shifting the compensated sensed current signal to produce a level shifted compensated sensed current signal, wherein averaging a signal that is at least proportional to the compensated sensed current signal includes averaging the level shifted compensated sensed current signal.

3. The method of claim 1 wherein sensing an output current with reference to a ground reference of the synchronous buck converter circuit over only a portion of a waveform of the output current includes sensing the output current with reference to the ground at the low side active switch.

4. The method of claim 1 wherein the swinging choke comprises a first core piece and a second core piece and at least one winding, a portion of the first core piece separated from a portion of the second core piece by a stepped gap therebetween.

5. The method of claim 1, further comprising:
determining a compensation signal that is a direct function of the duty cycle of the portion of the synchronous buck converter circuit;
scaling the compensation signal; and wherein compensating a sensed current signal that is proportional to the sensed output current at least for any variation in a duty cycle of the synchronous buck converter circuit includes summing a scaled compensation signal with the sensed current signal that is at least proportional to the sensed output current.

6. The method of claim 5 wherein the duty cycle is the duty cycle of a high side switch of the circuit and scaling the compensation signal includes scaling the compensation signal to account for a difference between the duty cycle of the high side switch and a low side switch duty cycle of the low side switch of the synchronous buck converter circuit.

7. The method of claim 1, further comprising:
sensing an output voltage or potential of the synchronous buck converter circuit;
producing a voltage error signal indicative of an error between the sensed voltage and a reference voltage; and controlling the synchronous buck converter circuit based at least in part on the voltage error signal.

8. The method of claim 1, further comprising:
capacitively producing a signal proportional to an input current;
mirroring the signal proportional to input current; and adjusting a flow of the input current in response at least to the signal that is proportional to the input current to control an inrush current.

9. The method of claim 1 wherein capacitively producing a signal proportional to input current includes allowing a sense capacitor coupled in parallel with an input filter capacitor between an input line and a ground to be charged by the input current and adjusting a flow of the input current includes supplying a signal from a clamp circuit to a series pass device electrically coupled in series in an input line between the input terminal and the high side active switch.

10. The method of claim 9, further comprising:
detecting at least one of an over voltage condition or an under voltage condition on the input line; and in response to detecting at least one of the over voltage condition or the under voltage condition on the input line providing a signal to the clamp circuit that causes the series pass device to stop the flow of the input current.

11. The method of claim 9, further comprising:
detecting an enable signal indicative of a selected one of two states;
in response to detecting the enable single of a first one of the two states providing a signal that causes the series pass device to stop the flow of the input current; and in response to detecting the enable single of a second one of the two states providing a signal that causes an under voltage lockout monitor circuit to function.

12. The method of claim 9 wherein the power converter includes an auxiliary voltage supply to supply a VCC supply potential and a VSS supply potential, the auxiliary voltage supply comprising an auxiliary transformer having at least a primary, a secondary and a core; an auxiliary converter switch operable to selectively couple the primary to a ground reference node; a drive capacitance coupled to drive the converter switch; and a synchronization capacitance, the method further comprising:
increasing a supply of current via the auxiliary converter switch to the primary of the auxiliary transformer;
in response to an increase in current flow through the primary via the auxiliary converter switch, reflecting a corresponding voltage change by the primary to the secondary;
increasing a drive voltage to turn the auxiliary converter switch full ON
in response to the reflection of the voltage change corresponding to the increase in current flow through the primary;
decreasing the supply of current via the auxiliary converter switch to the primary of the auxiliary transformer;
in response to the decrease in current flow through the primary via the auxiliary converter switch, reflecting a corresponding voltage change by the primary to the secondary;
decreasing a drive voltage to turn the auxiliary converter switch OFF in response to the reflection of the voltage change corresponding to the decrease in current flow through the primary;
in response to a dynamic load current demand larger than a threshold, providing a voltage pulse to the primary by the synchronization capacitance;
reflecting the voltage pulse by the primary to the secondary; and applying the voltage pulse via the secondary to turn the auxiliary converter switch ON to synchronize a cycle of the bias voltage supply.

13. The method of claim 12, further comprising:
determining a time averaged difference of a sum of the VCC supply potential and a reference potential; and applying a signal to the secondary based on the determined time averaged difference.

14. The method of claim 12, further comprising:
driving a charge pump coupled to the primary of the auxiliary transformer to supply the VSS supply potential.

15. The method of claim 9, further comprising:
receiving an input voltage signal at the input terminal;
receiving a synchronizing signal at a synchronizing signal input terminal;
charging a ramp timing capacitor via the input voltage signal through a ramp timing resistance;
producing a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal;
in response to a value of a voltage across the ramp timing capacitor being equal to the discharge trigger reference voltage, discharging the ramp timing capacitor if a state of the synchronization signal indicates synchronization and delaying discharging of the ramp timing capacitor if the state of the synchronization signal does not indicate synchronization; and in response to the state of the synchronization signal indicating synchronization while the voltage across the ramp timing capacitor is less than the discharge trigger reference voltage, discharging the ramp timing capacitor.

16. The method of claim 15 wherein comparing the voltage across the ramp timing capacitor to the discharge trigger reference voltage includes supplying the discharge trigger reference voltage to a first transistor of a differential pair of transistors and supplying the voltage across the ramp timing capacitor to a second transistor of the differential pair of transistors.

17. The method of claim 16, further comprising:
determining whether to trigger discharging of the ramp timing capacitor when the value of a voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage.

18. The method of claim 17 wherein determining whether to trigger discharging of the ramp timing capacitor when the value of a voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage includes supplying the synchronization signal to a logic network comprising a synchronization capacitor, a first synchronization diode and a second synchronization diode, triggering the discharging of the ramp timing capacitor via the first synchronization diode in response to a first synchronization state and suppressing triggering of the discharging of the ramp timing capacitor via the second synchronization diode in response to a second synchronization state.

19. The method of claim 15, further comprising:
buffering an output voltage signal via an emitter follower buffer amplifier having a discrete transistor and resistor.

20. A first switch mode power converter, comprising:
a converter circuit including at least one inductor wound on a swinging choke and at least a first active switch;
an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current;
a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the first active switch of the converter circuit;

a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal;
and a drive controller coupled to the current control amplifier to receive the averaged signal and is coupled to drive at least the first active switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier.

21. The first switch mode power converter of claim 20 wherein the compensation circuit level shifts the compensated sensed current signal, and the current control amplifier is coupled to receive a level shifted compensated sensed current signal from the compensation circuit.

22. The first switch mode power converter of claim 20 wherein the first active switch is a high side switch and the converter circuit includes at least a second active switch which is a low side switch, and wherein the output current sensor senses the output current with reference to the ground on a low side of the low side active switch.

23. The first switch mode power converter of claim 20 wherein the compensation circuit is coupled to receive a signal indicative of one minus a duty cycle of the high side switch and determines a compensation signal that is a direct function of one minus the duty cycle of the high side switch, scales the compensation signal, and sums the scaled compensation signal with the sensed current signal.

24. The first switch mode power converter of claim 23 wherein the compensation circuit scales the compensation signal to account for a voltage level offset.

25. The first switch mode power converter of claim 20, further comprising:
a voltage error amplifier coupled to receive a signal indicative of an output voltage of the converter circuit and a signal indicative of at least a reference voltage, the voltage error amplifier operable to provide a voltage error signal indicative of an error between the output voltage and the reference voltage to the current control amplifier.

26. The first switch mode power converter of claim 25 wherein the compensation circuit includes a switch that selectively couples an input of the current control amplifier between an output of the voltage error amplifier and a shared line that is coupleable to receive a voltage input from a second switch mode power converter to operate the first and the second switch mode power converters in a current sharing mode to supply current in parallel to a common load.

27. The first switch mode power converter of claim 20 wherein the compensation circuit includes a common emitter stage that drives a shared line when configured as a master that is able to supply a voltage output from the first switch mode power converter through a share pin to operate a second switch mode power converter configured as a slave through a slave pin thereof in a current sharing mode to supply a common load.

28. The first switch mode power converter of claim 20, further comprising:
a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line;
a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current that is charging the input filter capacitor;

a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line.

29. The first switch mode power converter of claim 28 wherein the current sense mirror includes a first mirror transistor coupled to the ground reference through a first mirror resistor and a second mirror transistor coupled to the ground reference through a second mirror resistor, a base of the first mirror transistor and a base of the second mirror transistor commonly coupled to the sense capacitor to maintain a constant inrush charge current to the input filter capacitor.

30. The first switch mode power converter of claim 29, further comprising.
a pair of trickle bias resistors electrically coupled between the input line and a source of the first mirror transistor of the current sense mirror.

31. The first switch mode power converter of claim 28, further comprising:
an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

32. The first switch mode power converter of claim 31 wherein the over voltage lockout monitor circuit includes a pair of over voltage lockout resistors coupled as a voltage divider between the input line and the ground reference via an over voltage lockout Zener diode which is coupled to drive a switch controlling transistor which is in turn coupled to control the series switch.

33. The first switch mode power converter of claim 32 wherein the over voltage lockout monitor circuit further includes a low impedance charge path formed by a speedup diode and a speedup resistor electrically coupled between the input line and the base of the transistor.

34. The first switch mode power converter of claim 28, further comprising:
an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

35. The first switch mode power converter of claim 34 wherein the under voltage lockout monitor circuit includes an under voltage lockout comparator that has a first input and a second input, the first input coupled to the input line via a first under voltage lockout resistor and the second input coupled to a voltage reference source via a second under voltage lockout resistor.

36. The first switch mode power converter of claim 35, further comprising:
an enable monitor circuit operable in response to an enable single to provide control signals to cause the series switch to stop the flow of the input current along the input line.

37. The first switch mode power converter of claim 28, further comprising:
an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit;
an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit;
an enable monitor circuit operable in response to an enable single to provide control signals to the clamp circuit indicative of a disable state, and wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit, the under voltage lockout monitor circuit, and the enable monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line in response to a signal indicative of the over voltage condition, the under voltage condition, or a disable state.

38. The first switch mode power converter of claim 28 wherein the sense capacitor has a capacitance that is less than a capacitance of the input filter.

39. The first switch mode power converter of claim 28, further comprising: an auxiliary bias voltage supply to supply a VCC supply potential and a VSS supply potential, the auxiliary bias voltage supply comprising:
an auxiliary transformer having at least a primary, a secondary and a core, the primary coupled at a first node to receive an input at a first input potential and coupled at a second node to provide a first output potential and a second output potential with an output voltage which is higher than an input voltage supplied to the first switch mode power converter, and also including an auxiliary converter switch operable to selectively couple the second node of the primary to a ground reference node;

an error circuit coupled to control the auxiliary converter switch through the secondary of the auxiliary transformer based at least in part on a difference between the first output potential and a reference potential; and a synchronization capacitance electrically coupled in parallel with the diode between the primary and the VCC output node that in response to a dynamic load condition provides a signal that is reflected by the primary across the auxiliary transformer to the secondary to drive the auxiliary converter switch to synchronize operation with a periodic load demand.

40. The first switch mode power converter of claim 39 wherein the synchronization capacitance of the auxiliary bias voltage supply is supplied at least in part by a parasitic capacitance of an output diode electrically coupled between the second node of the primary and a VCC output node and at least in part by a substrate capacitive coupling.

41. The first switch mode power converter of claim 39 wherein the error circuit of the auxiliary bias voltage supply includes an error amplifier that sums the first output potential and the reference potential and produces a time average of a difference between the first output potential and the reference potential.

42. The first switch mode power converter of claim 41 wherein the error circuit of the auxiliary bias voltage supply includes a current mirror coupled to reflect an output of the error amplifier to the secondary of the auxiliary transformer.

43. The first switch mode power converter of claim 39 wherein the auxiliary bias voltage supply further comprises:
a charge pump coupled to the second node of the primary of the auxiliary transformer to supply the second output potential.

44. The first switch mode power converter of claim 39 wherein the auxiliary bias voltage supply further comprises:
an over voltage clamp circuit coupled to turn OFF the auxiliary converter switch in response to a transient condition in at least one of the first input potential or the first output potential.

45. The first switch mode power converter of claim 28, further comprising an oscillator, the oscillator comprising:
a voltage input terminal to receive an input voltage signal;
a synchronizing signal input terminal to receive a synchronizing signal;
a ramp timing resistance;
a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance;
an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal;
a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage; and a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor.

46. The first switch mode power converter of claim 45 wherein the input voltage resistor divider network of the oscillator includes a first divider resistor, a second divider resistor, and a temperature compensation resistor to compensate the discharge trigger reference voltage for temperature variation, the input voltage resistor network coupled to provide the discharge trigger reference voltage the comparator.

47. The first switch mode power converter of claim 46 wherein the comparator of the oscillator comprises a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors, with a base of the first comparator transistor coupled as an inverting input to the input voltage resistor divider network to receive the discharge trigger reference voltage and a base of the second comparator transistor coupled as a non-inverting input to the ramp timing capacitor to receive the voltage across the ramp timing capacitor.

48. The first switch mode power converter of claim 45 wherein the comparator of the oscillator comprises a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors.

49. The first switch mode power converter of claim 45 wherein the oscillator further comprises:
a control transistor;
a discharge controlling capacitor;
a discharge termination transistor; and a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor to a ground reference node.

50. The first switch mode power converter of claim 49 wherein the logic circuit of the oscillator includes: a synchronization capacitor coupled to the synchronization input terminal to receive the synchronization signal, a first diode coupled to cause the control transistor to be in a first state in response to a first state of the synchronization signal and a second diode coupled to the control transistor to cause the control transistor to be in a second state in response to a second state of the synchronization signal.

51. The first switch mode power converter of claim 50 wherein the oscillator further comprises:
a level shifting diode electrically coupling a control transistor resistor to a ground to level shift the control transistor resistor reducing a voltage required to turn on the control transistor.

52. The first switch mode power converter of claim 45 wherein the oscillator further comprises:
a buffer transistor; and a buffer resistor, the buffer transistor and buffer resistor coupled to form an emitter follower buffer amplifier between a voltage supply and a ground to provide a low source impedance driver.

53. A switch mode power converter, comprising:
a converter circuit comprising:
at least one inductor and at least one converter switch operable to selectively coupled the at least one inductor to a ground reference and a drive controller coupled to control the at least one converter switch;
an auxiliary voltage supply to supply a VCC supply potential and a VSS
supply potential comprising:
an auxiliary transformer having at least a primary, a secondary and a core;
an auxiliary converter switch operable to selectively couple the primary of the auxiliary transformer to a ground reference;
a drive capacitance coupled to drive the auxiliary converter switch; and a synchronization capacitance, wherein the auxiliary transformer, the auxiliary converter switch and the drive capacitance are coupled in a positive feedback loop such that as a current flow through the primary via the auxiliary converter switch increases, the primary reflects a corresponding voltage change to the secondary that increases a drive voltage to turn the auxiliary converter switch full ON and as current flow through the primary via the auxiliary converter switch decreases, the primary reflects a corresponding voltage change to the secondary that decreases the drive voltage to turn the auxiliary converter switch full OFF; and wherein the auxiliary transformer, the auxiliary converter switch and the synchronization capacitance are coupled such that in response to a dynamic load current demand larger than a threshold the primary reflects a voltage pulse to the secondary to turn the auxiliary converter switch ON to synchronize a cycle of the bias voltage supply; and an oscillator comprising:
a voltage input terminal to receive an input voltage signal;
a synchronizing signal input terminal to receive a synchronizing signal;
a ramp timing resistance;
a ramp timing capacitor which is charged by the input voltage signal through the ramp timing resistance;
an input voltage resistor divider network coupled to the voltage input terminal and which produces a discharge trigger reference voltage that is proportional to a voltage of the input voltage signal;
a comparator that compares a voltage across the ramp timing capacitor to the discharge trigger reference voltage; and a logic circuit that in response to a first state of a synchronization signal, discharges the ramp timing capacitor and that in response to a second state of the synchronization signal when the value of the voltage across the ramp timing capacitor is equal to the discharge trigger reference voltage, delays a discharging of the ramp timing capacitor.

54. The switch mode power converter of claim 53 wherein the synchronization capacitance of the auxiliary voltage supply is supplied at least in part by a parasitic capacitance of an output diode electrically coupled between the primary of the auxiliary transformer and a VCC output node and is supplied at least in part by a parasitic substrate capacitive coupling.

55. The switch mode power converter of claim 53 wherein the auxiliary voltage supply of claim 12, further comprises:
an error circuit coupled to control the auxiliary converter switch through the secondary of the auxiliary transformer based at least in part on a difference between an output voltage and a reference voltage.

56. The switch mode power converter of claim 55 wherein the error circuit of the auxiliary voltage supply produces a time averaged difference of the sum of the VCC supply potential and a reference potential.

57. The switch mode power converter of claim 53 wherein the comparator of the oscillator comprises a first comparator transistor and a second comparator transistor coupled as a differential pair of transistors, with a base of the first comparator transistor coupled as an inverting input to the input voltage resistor divider network to receive the discharge trigger reference voltage and a base of the second comparator transistor coupled as a non-inverting input to the ramp timing capacitor to receive the voltage across the ramp timing capacitor.

58. The switch mode power converter of claim 53 wherein the oscillator further comprises:
a control transistor;
a discharge controlling capacitor;
a discharge termination transistor; and a discharge controlling transistor, the control transistor responsive to at least an output of the comparator to selectively charge the discharge controlling capacitor from the voltage input terminal, the discharge controlling capacitor coupled to selectively cause the discharge controlling transistor and the discharge termination transistor to discharge the ramp timing capacitor.

59. The switch mode power converter of claim 58 wherein the logic circuit of the oscillator includes: a synchronization capacitor coupled to the synchronization input terminal to receive the synchronization signal, a first diode coupled to cause the control transistor to be in a first state in response to a first state of the synchronization signal and a second diode coupled to the control transistor to cause the control transistor to be in a second state in response to a second state of the synchronization signal.

60. The switch mode power converter of claim 59 wherein the oscillator further comprises:
a level shifting diode electrically coupling a control transistor resistor to a ground to level shift the control transistor resistor reducing a voltage required to turn on the control transistor.

61. The switch mode power converter of claim 53, further comprising:
an input control circuit that controls inrush current, the input control circuit comprising:
a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line;
a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current;
a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line.

62. The switch mode power converter of claim 61 wherein the current sense mirror includes a first mirror transistor coupled to the ground reference through a first mirror resistor and a second mirror transistor coupled to the ground reference through a second mirror resistor, a base of the first mirror transistor and a base of the second mirror transistor commonly coupled to the sense capacitor to maintain a constant inrush charge current to the input filter capacitor.

63. The switch mode power converter of claim 61 wherein the input control circuit further comprises:
an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

64. The switch mode power converter of claim 61 wherein the input control circuit further comprises:
an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

65. The switch mode power converter of claim 53 further comprising:
an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current;

a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the first active switch of the converter circuit;
a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal;
and wherein the drive controller is coupled to the current control amplifier to receive the averaged signal and is coupled to drive at least the first active switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier.

66. The switch mode power converter of claim 65 wherein the compensation circuit level shifts the compensated sensed current signal, and the current control amplifier is coupled to receive a level shifted compensated sensed current signal from the compensation circuit.

67. The switch mode power converter of claim 65 wherein the at least one converter switch includes a high side switch and a low side switch, and wherein the output current sensor senses the output current with reference to a ground coupling of the low side active switch.

68. The switch mode power converter of claim 53 wherein the at least one inductor includes a primary associated with a swinging choke.

69. A switch mode power converter, comprising:
a converter circuit including at least one inductor and at least one converter switch;
an output current sensor that senses an output current of the converter circuit with reference to a ground of the converter circuit over only a portion of a waveform of the output current;

a compensation circuit coupled to receive a sensed current signal that is proportional to the sensed output current from the output current sensor and to compensate the sensed current signal at least for any variation in a duty cycle of the converter circuit;
a current control amplifier that averages the signal that is at least proportional to a compensated sensed current signal to produce an averaged signal;
and a drive controller coupled to the current control amplifier to receive the averaged signal and is coupled to drive the at least one converter switch of the converter circuit based at least in part on the averaged signal produced by the current control amplifier;
a series switch electrically coupled in series on an input line and operable in response to control signals to adjust a flow of an input current along the input line to the at least one inductor of the converter circuit;
a sense capacitor electrically coupled in parallel with an input filter capacitor between the input line and a ground reference to develop a signal that is proportional to the input current;
a current sense mirror electrically coupled to the sense capacitor to receive the signal that is proportional to the input current; and a clamp circuit responsive at least to the current sense mirror to provide the control signals to the series switch to cause the series switch to adjust the flow of the input current along the input line.

70. The switch mode power converter of claim 69, further comprising:
an over voltage lockout monitor circuit operable to detect an over voltage condition on the input line and coupled to supply a signal indicative of the over voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the over voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

71. The switch mode power converter of claim 69, further comprising:
an under voltage lockout monitor circuit operable to detect an under voltage condition on the input line and coupled to supply a signal indicative of the under voltage condition to the clamp circuit, wherein the clamp circuit is further responsive at least to the under voltage lockout monitor circuit to provide control signals to the series switch to cause the series switch to stop the flow of the input current along the input line.

72. The switch mode power converter of claim 69 wherein the compensation circuit level shifts the compensated sensed current signal, and the current control amplifier is coupled to receive a level shifted compensated sensed current signal from the compensation circuit.

73. The switch mode power converter of claim 69 wherein the compensation circuit is coupled to receive a signal indicative of a duty cycle of a high side switch and determines a compensation signal that is a direct function of the duty cycle of the high side switch, scales the compensation signal, and sums the scaled compensation signal with the sensed current signal.