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CA2391480A1 - Single chip cmos transmitter/receiver and method of using same - Google Patents

Single chip cmos transmitter/receiver and method of using same Download PDF

Info

Publication number
CA2391480A1
CA2391480A1 CA002391480A CA2391480A CA2391480A1 CA 2391480 A1 CA2391480 A1 CA 2391480A1 CA 002391480 A CA002391480 A CA 002391480A CA 2391480 A CA2391480 A CA 2391480A CA 2391480 A1 CA2391480 A1 CA 2391480A1
Authority
CA
Canada
Prior art keywords
signals
carrier frequency
frequency
channel signal
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002391480A
Other languages
French (fr)
Other versions
CA2391480C (en
Inventor
Kyeongho Lee
Deog-Kyoon Jeong
Joonbae Park
Wonchan Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GCT Semiconductor Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority claimed from PCT/US2000/031065 external-priority patent/WO2001035529A2/en
Publication of CA2391480A1 publication Critical patent/CA2391480A1/en
Application granted granted Critical
Publication of CA2391480C publication Critical patent/CA2391480C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/16Networks for phase shifting
    • H03H11/22Networks for phase shifting providing two or more phase shifted output signals, e.g. n-phase output
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/26Circuits for superheterodyne receivers
    • H04B1/28Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40Circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/372Noise reduction and elimination in amplifier
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H2011/0494Complex filters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Transceivers (AREA)

Abstract

The RF communication system includes an antenna that receives/transmits RF
signals, a PLL (730) that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having a carrier frequency, a demodulation-mixer (720) that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification (740, 750) that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit (770 A) for converting the RF
signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer (720) with greater amplitude or power.
CA002391480A 1999-11-12 2000-11-13 Single chip cmos transmitter/receiver and method of using same Expired - Fee Related CA2391480C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US16487499P 1999-11-12 1999-11-12
US60/164,874 1999-11-12
US1100A 2000-11-06 2000-11-06
USGCT-011 2000-11-06
PCT/US2000/031065 WO2001035529A2 (en) 1999-11-12 2000-11-13 Single chip cmos transmitter/receiver and method of using same

Publications (2)

Publication Number Publication Date
CA2391480A1 true CA2391480A1 (en) 2001-05-17
CA2391480C CA2391480C (en) 2009-10-06

Family

ID=26667125

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002391480A Expired - Fee Related CA2391480C (en) 1999-11-12 2000-11-13 Single chip cmos transmitter/receiver and method of using same

Country Status (4)

Country Link
CN (1) CN100420246C (en)
AU (1) AU767508B2 (en)
CA (1) CA2391480C (en)
HK (1) HK1054825A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8351490B2 (en) 2007-01-26 2013-01-08 Agency For Science, Technology And Research Radio frequency identification transceiver

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4647361B2 (en) 2005-03-29 2011-03-09 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
CN101447766B (en) * 2007-11-27 2012-08-01 立锜科技股份有限公司 Single-output operational amplifier be capable of eliminating excursion and method thereof
CN102790596B (en) * 2011-05-20 2014-10-29 杭州中科微电子有限公司 Automatic gain control amplifier for canceling direct current offset
US9219410B2 (en) * 2012-09-14 2015-12-22 Analog Devices, Inc. Charge pump supply with clock phase interpolation
CN103036588B (en) * 2012-12-05 2014-11-05 中国科学院上海微系统与信息技术研究所 Ultra-low power consumption transceiver used for short-distance wireless-connection and wireless-node of internet of things
US9300297B2 (en) * 2013-11-05 2016-03-29 Qualcomm Incorporated Reference-voltage-less pseudo-differential input circuitry
US9509268B2 (en) * 2014-11-04 2016-11-29 Mediatek Inc. Signal amplifying system, AC signal generating circuit, amplifying gain acquiring method, and AC signal generating method
US9692471B2 (en) * 2015-01-21 2017-06-27 Mediatek Singapore Pte. Ltd. Wireless receiver with high linearity
CN105099488A (en) * 2015-07-20 2015-11-25 联想(北京)有限公司 Radio-frequency circuit
CN106788511B (en) * 2016-12-30 2019-07-23 北京时代民芯科技有限公司 A kind of wideband radio receiver
KR102557997B1 (en) * 2017-12-05 2023-07-21 삼성전자주식회사 Radio frequency integrated chip(rfic) tranceiving signals by using carrier aggregation and wireless communication device comprising the same
KR102527676B1 (en) * 2018-07-13 2023-05-03 삼성전자주식회사 Phase locked loop circuit
CN112865154B (en) * 2021-03-08 2024-04-12 阳光电源股份有限公司 Energy storage system and battery cluster balance control method thereof
CN113507295B (en) * 2021-09-13 2021-11-19 成都明夷电子科技有限公司 Application method of fully-integrated broadband configurable front end based on SOI CMOS process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0785640B1 (en) * 1996-01-17 2002-11-06 Nokia Corporation Method for extending the RSSI range and radio transceiver operating in accordance with this method
JPH10117127A (en) * 1996-10-11 1998-05-06 Toshiba Corp Logic storage circuit and logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8351490B2 (en) 2007-01-26 2013-01-08 Agency For Science, Technology And Research Radio frequency identification transceiver

Also Published As

Publication number Publication date
CN1411651A (en) 2003-04-16
CN100420246C (en) 2008-09-17
AU767508B2 (en) 2003-11-13
CA2391480C (en) 2009-10-06
HK1054825A1 (en) 2003-12-12
AU1600501A (en) 2001-06-06

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MKLA Lapsed