CA2007644A1 - Methode de controle a bus communs - Google Patents
Methode de controle a bus communsInfo
- Publication number
- CA2007644A1 CA2007644A1 CA2007644A CA2007644A CA2007644A1 CA 2007644 A1 CA2007644 A1 CA 2007644A1 CA 2007644 A CA2007644 A CA 2007644A CA 2007644 A CA2007644 A CA 2007644A CA 2007644 A1 CA2007644 A1 CA 2007644A1
- Authority
- CA
- Canada
- Prior art keywords
- unit
- buses
- delay
- data
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 abstract 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP618789 | 1989-01-13 | ||
JP6187/`89 | 1989-01-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2007644A1 true CA2007644A1 (fr) | 1990-07-13 |
CA2007644C CA2007644C (fr) | 1996-09-10 |
Family
ID=11631554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002007644A Expired - Fee Related CA2007644C (fr) | 1989-01-13 | 1990-01-12 | Methode de controle a bus communs |
Country Status (3)
Country | Link |
---|---|
US (1) | US5123100A (fr) |
AU (1) | AU620197B2 (fr) |
CA (1) | CA2007644C (fr) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
US6751696B2 (en) * | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
CA2091093C (fr) * | 1992-03-06 | 1999-07-06 | Peter C. Di Giulio | Reseau de communication commande par l'evenement |
US5418934A (en) * | 1993-09-30 | 1995-05-23 | Intel Corporation | Synchronizing chained distributed digital chronometers by the use of an echo signal |
US5502437A (en) * | 1994-04-25 | 1996-03-26 | Motorola, Inc. | Receiver isolation scheme |
US5923667A (en) * | 1996-06-28 | 1999-07-13 | International Business Machines Corporation | System and method for creating N-times bandwidth from N separate physical lines |
US6115769A (en) * | 1996-06-28 | 2000-09-05 | Lsi Logic Corporation | Method and apparatus for providing precise circuit delays |
US6294937B1 (en) | 1999-05-25 | 2001-09-25 | Lsi Logic Corporation | Method and apparatus for self correcting parallel I/O circuitry |
US6557066B1 (en) | 1999-05-25 | 2003-04-29 | Lsi Logic Corporation | Method and apparatus for data dependent, dual level output driver |
DE10324001A1 (de) * | 2003-05-27 | 2004-12-30 | Bohr, Ingo, Dipl.-Ing. (FH) | Verfahren zur Steigerung von entweder Transfer-Leistung oder maximaler Leitungslänge bei einem Bussystem in einem Lenk-Flugkörper-System |
FR2950174B1 (fr) * | 2009-09-16 | 2011-11-18 | Sierra Wireless Inc | Dispositif de synchronisation d'un noeud esclave a synchroniser dans un cycle de transmission de donnees d'un bus de communication et systeme electronique correspondant. |
CN102843266A (zh) * | 2011-06-22 | 2012-12-26 | 比亚迪股份有限公司 | 一种can网络数据发送方法 |
JP6176162B2 (ja) * | 2014-03-19 | 2017-08-09 | 株式会社デンソー | データ処理装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5463634A (en) * | 1977-10-03 | 1979-05-22 | Nec Corp | Bus controller |
JPS5597625A (en) * | 1979-01-17 | 1980-07-25 | Fanuc Ltd | Bus connection system |
US4229792A (en) * | 1979-04-09 | 1980-10-21 | Honeywell Inc. | Bus allocation synchronization system |
US4373183A (en) * | 1980-08-20 | 1983-02-08 | Ibm Corporation | Bus interface units sharing a common bus using distributed control for allocation of the bus |
IT1129371B (it) * | 1980-11-06 | 1986-06-04 | Cselt Centro Studi Lab Telecom | Commutatore di messaggi a struttura distribuita su canale ad accesso casuale per colloquio a messaggi tra unita elaborative |
US4562533A (en) * | 1981-12-03 | 1985-12-31 | Ncr Corporation | Data communications system to system adapter |
SE430740B (sv) * | 1982-04-26 | 1983-12-05 | Ellemtel Utvecklings Ab | Anordning for synkronisering av overforing av information pa en enkelriktad buss |
JPS59149447A (ja) * | 1983-02-17 | 1984-08-27 | Nec Corp | フレ−ム同期方式 |
US4660169A (en) * | 1983-07-05 | 1987-04-21 | International Business Machines Corporation | Access control to a shared resource in an asynchronous system |
DE3374238D1 (en) * | 1983-07-08 | 1987-12-03 | Ibm | A synchronisation mechanism for a multiprocessing system |
US4661905A (en) * | 1983-09-22 | 1987-04-28 | Digital Equipment Corporation | Bus-control mechanism |
US4669056A (en) * | 1984-07-31 | 1987-05-26 | International Business Machines Corporation | Data processing system with a plurality of processors accessing a common bus to interleaved storage |
JPS6262697A (ja) * | 1985-09-13 | 1987-03-19 | Toshiba Corp | デ−タ送信制御方式 |
-
1990
- 1990-01-10 US US07/462,816 patent/US5123100A/en not_active Expired - Fee Related
- 1990-01-12 CA CA002007644A patent/CA2007644C/fr not_active Expired - Fee Related
- 1990-01-12 AU AU47932/90A patent/AU620197B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
CA2007644C (fr) | 1996-09-10 |
AU4793290A (en) | 1990-07-19 |
AU620197B2 (en) | 1992-02-13 |
US5123100A (en) | 1992-06-16 |
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JPS6481426A (en) | Star lan |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |