CA2004096A1 - Successive approximation register - Google Patents

Abstract

ABSTRACT
A successive-approximation register (SAR) has a single shift register for processing, that is presetting and selectively resetting, a number of bits. The single shift register is arranged to provide bit selection for processing the bits and also to provide desired result accumulation in the processed bits.
Further, the single shift register comprises an array of stages, the stages including a first stage, a last stage and a number of active stages equal to the number of bits of digital output (Figure 3).
Conveniently, the SAR adopts a "One-bits to Right"
test implemented by a Manchester Carry Chain in the opposite direction to the shift direction.

Description

g~i ~-Lg ~ 11710 ~ h~ pre~erl~ inve~IItion r~lAte~ ~on~lly 'c~ th~
~t~ld o~ itAl-tO-~naloyufl ~DA~) nnd Analogue-tQ-Dlgital ~DC) Conv~o~ 50ro partlcul~ly, the .~n~r~ntion relat~u to ~ ~u~ 81ve-Approx~tlon ~gl~ter ~R) ~r u~ ln such ~or~ y~
Most ~p~ ally, tha lnv~ntion rel~t~ to a me~hod o~ ~plementlnq uch S~RI u~ ng ~ single regl~er only,, t~ pro~ ~e both th~ ~ddr~olng and d~.t~ or3g~
~unet~on~ (a~ ~o~ ull~ ho~el~ter de~crlb~ roqul~i~g slg~$~1Q~ntly 1~ elec~ron~ ciroultry th~n ks~o~n prlor a~t de3~igns .

~ n ~lectronic ~:n~trumerl~tloll ~y6tem~, it ~requ~n~ly neo~ y to a~ t an analogue v~lu~
c~n~lnu~u~ly v~ryis~g ele~l:rl~ nRl) ~nd t~ tr~n~orm th valu~ o~ ~h~t ~gnal lnto a di~it~l repr~nt~t:l~n for 3ub~0~u~nt pro~slng .
&u~h ~ dl~ l repr~elnt~tlon 1~ ~ommonly m~da a~ ~
binary fra~lon o~ so~e kno~ e~en~e" v~lu~, th4t ~B the "~uanti'cy" ~6 r~pre~er~t~l A3 a N-bi'c ~ary nu~s, who~e ~alue X d*not~ cluJnt~t5t ~hu~
Quantl ty ~ Re ~e re~e x ( X~2~ ), where the v~lue X m~y r~ng~ ~ro~ 2e~0 to 2~
Th~ ~ no~tiorA ~n~y r~p~e~nt re~l qui~nt~ol3 $rom 2~ro to ~ t l~ th~n the ~h~en ~ferenc~ value. For ~x~mple, lS ~h~ ~of~rence v~lue i~ chD~en a~ 10.24Y (i.e.
21 X 0.01V~, as~ the digital repreaent~tion i~ ~ lQ bit~, we may repFe~ent volta~e5 ~rom zerD ~o 10.2~V, t~ wi~hin ~n ~ccuracy o~ 0 . OlV~
M~ny te~hniques fc~r ~xecuting Analo~ue-to-l~igit~
con~ ion h~ been descr~ bed in ~uch st3nd~rd text~ a~
'sipolar ~nd MOS An2~10g Integ~ted Circlsit Es~ign" ~G~bane ., John ~i~ey, lgB4)~ ~he present inventlos~ f ~p~cif~
~pplloatlon to converter~ loying the ~o-c~lled n~uco~s~v~ Approxi~atlcn" m~ho~, wh~ ch ~ kDown.

21~ 9~

~ teehnique ~ legic de6i~n pr~eti~ed ln V~ry L~rge-Se~l~ Int~ tlorl (~vLSI) elr~u~ts, 14 the ~o-eall~d "dyn~m1c" t~ehniqu~ ~ s~e, lnt~r alil ~, M~ad and eonway, nIntrodut:t~on t~o trL~;I ByJ3~ r Add1~ n~ y, l9BO).
This ~h~m~ reli~s upon th~ ~horto~er~ ~torage o~
lnformation a6 el~e~c~ie~l el~argels ln ~tr~y wi~lng e~pacltanc~. Adroitly used, this ~othod e~n r~sul~ in conslderabla red~let~on~ ~n oireuit complexity and pcaw~r consUmption. It~ dl~dv~nt~ge iB that th~ elect~lcal ~h~rge~ w~ wly "leakl~due to l~per~e~ ul~tior~), ultlng ln lo~ of the ~tor~d ln~rm~t~on. It iB
thero~or~ ~ ch~ra~tarlRtic o~ ~yn~ ircult~ to re~ h, th~t 1~ ~y ln~o~a~ion ~o stor~d, mus~ be p~rlod~o~lly read out and r~-writ an, to maln~n the ~h~rg~.
Accordlng to a ~nown SUC~BB1Y~ ~pproxl~ntion ~thod o conver~ion, th~r~ ~6 provi~d at l~t a Succe~tve-Approx~ma~ion R~gis~er ~SAR), ~ Digi~ o-Analogu~ Conv~rt~r ~DAC), a Comp~rat~r, and ~om~ ~orm of~equen~ing o~ ~ontrol loglc~ or a~ ho~n in ~igur~ 1.
~ he D~C ~ adapt~d to de~lop ~n a~alogue ou~pu~, etau~l to the R~fer~ncc ~rol~ge, multiplled ~y the bln~y ~rActlo~ ~tore~ in the ~, a~ ~s~rlbed above. P~n~
~thod~ o~ achi ~ving this are known, ~r ~xampl~ th~
llQd ~R,~'2~ L~dder" snsth~d, a~ tra~d irl Figu~ 2.
As ~3y b~ seon, the circuld ~osrpri~e~ ~n a~rrA~ o~ ~wit~he~
~dapt~ to ~wit~h b~two~s~ Grour~ and th~ once ~oltag~, ~n~ an array o~ ~a~st~nce~, bein~ al~err~t21y o~ ~ome v~lue (R), ~nd twice thRt ~ralu~ ~2R). ~y ~ultably ~etting the ~everal ~witche~, voltAge~ betw~en ~r~ ~G~ound3 a~d R~ferenc~ may be d~velope~ a'c the output. ~n a pra~tical ~DC,, the ~veral 6witche~ are ad~pted ~o b~ ~on~roll~d by the ~ev~ral bits o~ the BAR.
Thia output vDlt~g~ pplied to the Comp~ra~or j which de~lop~ a lo~c~ oel~ ~ru~F~l~e) ou~put, ~ndie~lng ~sheth~r the DA~ output ~ a hlgher o~ lower than thæ un3crown ~nalogue ~nput. Thi~ logic~l o~ltput 1~ u~ by the Co~trol Logic ~o ad~u~t th~ b~ nary ~umbor held in the 8AR, ~o ~ to brin~ th~ D~C output ~a clo~ as po55ible to , . 1 . .. _ . . . ... .

~0~396 ~3--~he ope~ting p~ne~ ple i~ ~:yp~ ~lly ~ ~ollow~ s Th~ Control ~gt ~ ba~ln~ by ~tting ~11 the 8 bl~ ~o ~ro~ The ~o~t ~i~ni. 1~nt .~ b~ th~n pr~6ct to One, and the Co~p~rato~ output i~ tost~ If tho ~C
output ~ und to b~ h~qh~r th~n ~h~ unks~c~wn lnp~t, th~ ~AR
bl~ is ~lqa~ed o~ re~et b~ck t~ ~ero, oSha~wl~e i~: s~ins 81!t 1~ On~. ~he Corl~rol Lo~1~ then p~:OJl;~tB the next lo~r ~igni~ica~ce S~R b~ d pro~e*d~ ~$~m~1~rly/ Utlt~l h t~ h~v~ n pro~
~ onve~lently, a ~:~v~ R blt :L~ pra~t to One, l31mult~n~ou~1y wlth the ~olec7t~e ~ettl~g o~ its pred~e~r .
Wh~n ~hi~ proce~s iæ ~o~pl~e, ~ e~uired d~glt~l r~pr~ntatlon of t~ unknow~ lnput 1~ held in the 8A~ bit~
~he soq-~l rement ~o malnt~ the S~¢ outpu~ ~o~ ext~ndad p~ri~d~ l~e u~ually proclude$ th~ ue~ o~ Dyr~m~c ~oglc ~a~ af~edos~rlbed) in pr~ AR desi~n~.
~ h~ te~nlquo ls wld~ly u~d in pr~ctic~l dev~c~.
I~ wi~ p~r~n~ th~ le~ two ~2~ta ~'co~ag~
~e~ Ar~ re~ul~d namely, thh SAR bit~ the~scl~ nd ~ome fur~h~ mean~ sumed ln thæ abo~e exhmple to ~ ~ont~ined w~t~n t~e Conts~l ~og~) to keep tr~ck o~ whlch S~ bi~ 1 ~u~rRnt~y b~ng proc~ad.
Pr~ctic~l ~y~ h~v~ ul~ d ei~he~ z~ counte~ or ~hl~ r~glst~t circuit l to pe~orm ~h~ tt~r ~blt ~ddre~ g~ ~nc~on, ~n ~x~mplc o~ th~ $hlft-~gi~t~r t~chnique m~y be ~ound ~I~ the 74LB502 SP~R int~g~at~d cirC~att ~Fa~rchild ~miconductor, tno.), wh~ op~at;ion 1 de~rib~ n the m~nuf~cturer'~ d~t~ sh~et~.
I~ will b~ ap~eci~Lt~d th~t, wh~n two ~h~ :Et r~ist~ are uA~d, t:h~ seco~ld ~dd~ in~) r~gl~tar co~eumes ~ &~ r a~ount o~ el~ctroni~ c~rcu~ry ~ar~2~ ~o th~ actual ~AR r~ t~r l~olf. Courl~r-~als~d 5yl;i~
~o~ume a ~ a3~0unt o~ extra c~r~uit~y ~or the xe~u~site Count~r an~ D~eode~. ~erotQ~ore, it h~ not p~ov~d po~ o ~limlna~s thl6 extra ~ rcu~try. Cl~axly ~u~h elimlnation would be do~i~abl~, lea~ng ~o ~ t~r ;~00 ~)9G

Th~re ~re num~rou~ pxio~ ar~ pertninln~ to SAR
d~sl gn ~nd to P.nalo~u~-to-Dl~ital coTlv~ n ~nd p~rticul~ly orien~ g towa~d ~mprovlny the ~peed o~
op~ratl~n o~ the ~R rather than ~eeklng to redu~e th~
cirou~t ~omploxl~y. Some kn~wn prior ~rt ~re US 4527148, U5 47~4750, 1:~2S~54~, EP 25 Other~, for 2xampl21 U~ 4654584, r~l~t~ to varlou~
~orm~ a~ Analogue-to-~gital Con~r~rter~ r~ther t~lan to the n~l ~uncl:ios~ g o SAR.
~ n U~ 46g8018, th~ p~obl~ o~ ~AR de8~gn i8 ~ddr~sad. ~owev~r, lt dlsclo~ and requlras ~ep~ta ~hi~t Ro~l~ter ~ HR2, ~R3, 8~R4 ~ ~nd 8AR ~torage ce~ll6 ~ ) rsthe~ than a ~ yle stor~ cell to par~orm bo~h ~unction~ o~ bit ~dd~ssin~ e~nd accumul~t~ng th~
re~u~t. Furth~r~ tho use o~ ~eparatR ~hi~t R~ t~ and SA~
lAtch~# n~c~ a~e~ ~dd~ti~n~l ~er~al sl~nal p~th~3 tB ~n U~ 4~aOl8 ) be~wecn ~u~ce~ve stage~ ~
Fur~he~ore, th~ op~ratlon o~ ~he ~AR la~oh t~) r~qu~r~ th~t th~ ~trlng o~ ~o~r~t tr~n61~tor~ ~52, 54/
5~) h~ve ~ t~r ol~ctrical conduc~iv~ty th~n ~h~ latch t~nsi~tor~ ( lnvert~ ~ 38 ~ . ~ Thi~ ~rran~em~nt o~
diff~renti~lly eondu~tive transl~tors ~ay p~relude fabr~tion o~ cireui~ ae~ording to A form of e~miconducto~
chip ~ lgrl on ~o e~ d "G~teArr~" d~-rlces, ch~r2-oter~d by a ~ultitude o~ trans~stdr~ all o~ ~ standafd slse, thu~
abl~ to o~ low d~sl~n ~nd ~et-up cost~. T~ ~nod' ~y ~uch cir~uit arrang~ment ~:o al~ the r~guirem~nt ~or di~fer~ntl~lly eorl~luetive t~an~istors, ~ignl ic~ntly more trans~tor~ m~ rQ~u~ rsd ~or th~ modifiad design.
V6 444119~ i8 intend~à to in~rea~e {~h~ op~ ting ~pe2d of &A}t u6ing bo~h edye4 ~ the clock ~i~n~ wo latch elem~t~ per blt of ~he SAR are discloe~.
Os~EC~ O~ T~ NT~O~
n o}~ t o~ th~ pre~ent invent~Qn to ~llovi~te ~ne or all o~ the ~sadv~atag~ o~ the pr~ o~ art an~ to ~l~plify the ~esign of SA~.
It i~ a ~urth~r obj~ct of th~ pres~nt invent-i~n to provide a me~hod o:E ~mp~ementiny 2~ 6)9 SAR ~nd àt:B addr~Bing ~eun~ti~n, wlthln ~ ~tngl~ ~hlt r~ t~, th~r~ util~ ~ing a~proxim~t~ly h~lf the c~uitry d by prlor Art devlc~.
It i~ a ~urth~r ob~ec~ o~ the pre~er~t lnv~n~ion pro~id~ a ~ n~ whQr~by ~ch a ~oglster f~ tlon~d ~
de3~b~d abov~ y con~en~ontly he f~bricate~ p~cially on ~ary LArg~ le In~rati3n (~r~SI) chip~.
It i~ 3 ~u~ther ~je~t o~ the pr~n'c inv~ntion to provld~ ~ R~ ter a~g de crib~d ~bove Surth~r lnco~porating ~elf-r~fr~h ~e~tu~e8, ~heroby per~tirlg lt~ lmpl~menta~ion u~ing ~o-c~lled "dynami~ l~gl~" ~as h~reinb~fore de~c~ib~d), ~nd p~itting ~u~th~r reduction~ in ch~p-~rea ~n~ operat ing powor r~r:Jui rom~nt~ .
It ~ urth~r ob~e~t o~P th~ pre~ent lnv~nt~ ~n to ~r~vitl~ ~ R~ t~r a~ de~rlbed ~4~ eln~ capable o~
~Ea~rlcAt~on u~ng t~Rn~ r~ ~11 o~ ;in~le ~anda~:d 8i~, 80 ~ atl~ the r~&li~tlon the~eof or~ GA~e Arr~y d~ ce s .
~3~
In the: ~ollowln~ de~cription, lt will be ~u~n~d t~nRt th~. S~R ~hl~ts ~r~m la~t 'co riyht. I'hls w~ ply that th~ 12~tD~o~t bit i~ the mo~:t 6ign~ ~icant, an~ th~
righ~m~t th~ le~t ~i gnl~cant. N~turally, th~ c~nv~:8~
arr~ny~m~nt 16 egu~lly fe~lble, Q~ would be l~nder~tood ~r 'ch~ ~k~ lled addr~s~e and ~hu6 ~1BO fsll~ w~hin ~ho 8COp~
o~! the pr~Bnt in~rention.
~ lkewi~e, ~h~ lo~lc structur~ herein ~scri~e~ ~r~
cap~bl~ o~ m~ny ~orme o~ pr~o~c~l Qmbodl~ont ~n el~tror~c ~i~cultry, a~ would b~ und~rstood by th~ sklll~d lI~ ~he art. ~uch ~ltern~tive e~nbod~ t~, ~uch ~ ~ar~ou~ form~ of ~OS, bi--~olar, dl~cr~te or o~h~rs ~lso ~11 wlthin the ~copo o the prasen'c inven~lon. Accordingly, the p~afarred embodiment d~scr~bed he~einafter, wh~ Ch hssurn~ ~
Compïem~ntary Metal O~ld~ Semlcondu~tor ~ CMO~ bricatlt~n pro~ , i8 Ito b~ r~g~rded as exes~plary onl~

--s~
~ he p~s~nt inven~lon p~s~v~slos a ~u~ee~lve-~pprDxlm~tios~ r~gi~t~r ~S~ h~ ng a ~ingla ~hli'c regi~t~ o~ pro~e~tn~, th~t il; p~otgln~ ~nd eelec~vely ~ tti~g, ~ nuh~b~r o~ btt~, whor~n ~s$d s~ngl~
~;h~t ~egl~r i~ r~ng~d to provida bit ~lttctlo~ ~o~
p~o~e~ing th~ bit~ ~nd ~l~o to p~ovlde d~s~ ult u~lation ~ n tha p~oc~ d 1: $t6 .
~ hQ pr~ent lnv~ntlon sn~y ~OVltlB a 21AR wha~
p~o~ n~ of a giv~n hit i~ ~rr~nged to ~t~rt ~i~ultar~eou~ly,on tho ~me ~lo~k ~ign~l, wlth the eomplet~on D~ pro~sslng it~ edla~e ~e~ed~n~ b~t ~n~ th~ px~$~t~1n~
o~ the givan blt i~ ~f~ng~d to oocur ~imul~4n~0u~1y, oll the s~me ~lock g~ gn~l, with tho ~ele~:lYe reset~in-3 o~ ~ t~
l~dlate pr~ediTlg bit.
Con~ tly, .proc~s~d~it ~ cogni~d ~y ha~ng At logl~t one ~;et b~t ~n th~ ~hi ~ dl~ct~otl, ~he l~it belng proçes~ed . i~ ~ooo~nl~ed by hz~iny r~o s~t ~it ln l:he 6hi~t di~c~ion an~ t~f a 8et bit, ~n unproee~ed blt iP.
recog~ d by having no lie~ b~t lrl ~;ho ~hi~t dl~t~on and ~ lt~al~ n~t a ~ bit, an~: ~h~ nsxt bit tQ be pro~sB~
r~Dgnlsed by h~ving nv ~et bit ln the shl~ dlr~ctlon ~n~
h~vlng ~n ~djac~nt a~t bi~ in thP~ OppDl~te diroctlon to thle shlft dlr~ction ~nd ~ ltsel~ rlot ~ ~et ~it.
In practl~0, th~ ~tatus ~e~t~g~ltlor~ o~ ~lts ~
per~Drmed by Zl Marl~ho~tor) C~r~y ~han~ Isa~ ~ha$r~ . belng ~r~anged ~o pa~ o~matior in the opp~ dire~ti~n to the shi~t di~ction.
~ e ~re~ent ~ nventlon may al80 provide 2 ti~
whe~ei~ ~he sh~t ~eqicte~ ~om~ es an a~ay o ~gea ~nd the ~tages irlclud~ ~ ~lrst ~t~g~l, a la~t ~ge and a ~nber ~ctlve ~t~ge~ equ~l ~o th~ num~ o~ bit~ of d~gltal output .
Pr~f~r~bly, th~ fit ~tage ~s adapted ~o p~ov$de an output for presetting the ~ctive 6tage8, ~nd th3 last ~ta~e i~ adapted to ~r~vide an output for controlling th~
bil: ~elect~ on ~or proces~1ng the ~c~lve 4tage~ .

2~ 9~i --6A~
Fllrther, e~t!h a;:ti~e 3tag~ y co~pr~se ~ ~torsg~
~*11 cr ~ ar~ng ~ucc~3iVæ ~ f ~.he ~ s~d ~i~ital 8Utp7.1~
.~ and ~itc:he~ ~r ~ cti~e p~nc:s~inSI of d3l~ca iE~r ~ai~ ~or~ga cell, ~nd ~aGh ~itch may ~ i~pl~en~ in C~O~

9~

Th~ ,R ln ~e~ordan~e w~th the p~ nt inv~ntion may 1~ l~pl~m~nt~d i~ , MoS or Gat~ ~rray ~evlc~.
~XQ~ o~ Tl~E ~ WINGS
Pr~e~r~d l3lAbodlments of the pr~ent lnv~ntion wlll nosr b~ d~cri~ h ~arence to the ~c~omp~ny~n~
draw~ny~, whar~
Fl~ur~ 1 ~how~ ~ prior art ADC u~lng an SA~
Flgu~0 2 ~howQ ~ prlor art Rf2R l~dd~r DAC~
Fi~ure ~ show6 a SAR ~or~lng ~o the pr~ont nv~n~i on .
Flgu~e~ 4A an~ 4B ~how ~wltch loglc de~ n~
1n~P1Q~n~n~1n9 th~ pros~nt lnver~tlon.
Fl~u~e~ ~, 4D ~I~d 4E ~how ~chem~tic~lly ths dl~ r~n~ g~ o~ F~u~e 3 in CMOS.
~ i~u~ 5 sh~w~ prior art EatAt~C and dynam:l~ storaye Figu~ 6 ~how~ an actl~ st~ge ~d~pt~d ~or r~pld initiali~tlor~ ~
Fl~o 7 show~ an ~ctiv~ stage ad~pt~?d ~or ~arlal ~utp~t ~
Flgur~ ows tho r~lt~ o~ a PS~ic~ Rlmulhtlon o 5- blt ADC h~vin~ ~ho ~AR c~ the pre~n~ in~entlon.
o~ THE T N~ENT I 0~
~ SAR ~Gcordin~ to the inv~`tion compri~e5 R ~h~t regl~ter ~d ~egl~ter co~prls~slg n plurAllty o~ !13t~g~EI, aaoh ~t~g~ ~o~nprlslng ~ ~tcra~e c~ n~ addltlonal loglo ~uncti~n~ he~ein~ker d~-qcribed. Con~ ientl~ thQr~
w~ 11 be prov~ d~d a~ mE-ny ~tage6 as ~rc the nu~ar o~
re~ulreld blt~ (N) in t~ re~ulting dlgltal ~value ~ 10, ln thR exampl~ clted ~bove ) . ~he~e 6tdg~s are ~onn~te!d in a .~ri~s ~hain, ao that in~ormati.on may b~ cau~ed to mo~re from t~ righ~ along th~ cha~n, The~e ~r~ ~dditionally pro~ided a~cordln~ ta th~ ~nv~ntion, dunu~y ~ir~t and laat ~t~g~, whi~h d~ the en~ of the cho.in, ~a~d ~lr~t ~n~
1~3t etag~ themselve6 r~Qt ~ontributing to the diglt~l DUtp~Jt value.

_~_ Th~ gen~al hrr~n~ement o~ th~ pre~es~t inv~ n i~
lllu~tr~tod ~n P1gU~ 3. The CIOCK ~ignal oelu~ 2ach ~t~g~
to ~q~u~ a noW ~t~ valu~. ~h~ C~MP lnput 1~ tho output D3 th~ compara~or ~o~ P~gu~ nd indi~t~s s~h~lth~r ~h~
~urr~n~ S~R v~lu~ i8 ~bove or bolDw th~t re~ul~d. Tha RE~ input lb usQd to lnit~lly sal: ~11 8AR bit~ to ~o ( ~h~ U~1x ~l~notin~ th~t the ~ nal 1~ A~t~ve~ W) ~
d~rlbed above, op~ratloz2 ~a~tn~ ~y ~ ting all ~ora~o c~ o ~o, }:y s~mult~neous ~p~lication o~ RE~ET\
C~O~ gs~
Unce th~ P~E~ET\ ~l~n~l 16 d~a~t~v~d, the }l~Xt C~C~ will ~au~o the ~irs~ g~ ~o ~mlt ~ 13~1~al One sign~ or th~ one CI/OCEt ev~nt ~nly~. Thi~ On~ will ~hl~t lnto th~ st a~t~ve ~te~ pre~t~i.n~ ~h~ ~oBt ~gn~f ~ cant ~it ~o On~, ns de~rib~d above . ~h~ comparator pre~nts ~ recult on ~he C~M~ lan~, and the CI.OCX i~
~o-Applie~ ~ ~hi~ eau~es th~ r ex~ ~t~ to tha right l:o b~
pr~Qt ~ On~ ~ ~lmult~neouely the curr~nt actlve ~t~ge will be ~s~t ~o Z~ro ~ th~ o~mpisr~r indlc~t~ th~ the SAR
val~le i~ to~ hlyh.
Sub8~que~t CLOCX~ w~ peat this proce~ on ~ch SA~ bit in tu~, untll the 6hi~t~d One bit ~aches th~ la~t ~'cag~. Thi~ ag~ ls ~ de~gned tha~ ance B~t t~ On~, it rem~ se~ ~until the noxt RBS~T\), and ~D pr~d~ a Con~siorl ~omplete outpu~ ~lynal.
~ rh~ ~ nventlon 18 embodied in the ~ n o~ the logie wlthin ~eh sa~d ~t~ge, ~d logi~ being ad~ptod t~
r~o~nl~e whon lt~ stage $~ due to pre~t to On~ or to 89~ ti~ly reset ~o Z~ro by CC~P, and when its ~t~ not permitt~d to chang0. ~hi~ perm$t~ ~ slngle ar~y o:E ~t~,ge~
buth to pro~ lts ow~ ~ddY~aslng, ~nd to accumul~te tha r~ul red output data .
The lnvon~lon Etem~ rom t~ o~rvatlon th~t, on~e ~ny ~ n ~t~ge ~ ees~ evaluated ( i ~ e ~ pre~et nnd ~eïoctiv~ly ~et), there will alw~ys be ~t 1~6t one ~t~ge ~o i'cl; r~ ght h~ldlng a On~-bi~. 6uch a blt may not ch~nga it~ ~ra~ue aq~in until the ~sxt RE~E~. Thu~, a proc~ure may b~ ~oll~w~d to prQ~et ~h~ n~x~ ~tage to One-bit ~imult~n~Du61y with ~h~ ctlve r~ettlng t:h~ One-bi'c of the g~v~n ~ta~ Llk~w~ se a~ny okh~ 8~ h~vtrlg no One-~its to 1~ rl~he, ~nd ~t~ ~mmedi~t~ et n~ighbou~ o ~ol~irsg Zsro, i~ no~ yet to be ~v~lua~ nd h~rlce ~llso sho~ld n~t che~ng~.
At th~ rl~htmo~t ~ bit $t~ge in th~ ch~ , the ~oll~wlng ~ul~ h~ s the n~xt st~e to the ~lght ~hall ~om~ ~et to One ~ wh~ 1~ the p~s~nt ~t~ge ~t~lf ~h~ ele~v~ly roll~t to 2e~ ha~ th~ ~omp~rator ~;ho~r~ th~ e~ valuo l~8 hl gh .

-1~

X I ~ I X ~ I ~t~
X I 1 I X 1 I kit ~r el:
N ¦ ¦ O i X O ¦ N~t ~t: t~ lX 106t N ~ ¦ X 1 ¦ P~t b~
N I iC ~ GW 1 ¦ ~ ~t ' ~ h~ "One-bitx to Ri~ht~ te~ ay ~onYeni~ntly be lmpl~nted uls~ng th~P ~o-callod "M~nch~t~r C:arry Ch~ln", whl~h i~ com~only usad to det~rmln~ wh~n nll E~.~ blt~
~n a c:~unt~r ~re e~Gt to One (~ee, l~t~r ~lla, M~ad & Conw~y, nIntro~uc~ion to ~r~S~ Sy~t~ms", ~dis~on-l~le~l~sy, 1~8~). The C:e ~0~4p~:~E3BS ~ t~ way ~wltch, or mlsJ,tiplsxe~, a~o~lA~d wlth eaoh st~e/ b~lng ~d~pt~d to p~ a ~igr~al ~r~ thc p~e~cedlng ~t~ wh~n th~ cur~ont ~t~ge holds ~
~o, and t~ ~onncct lnste~d to a con.~t~I~t ~ero or Orle) ~han th~ current ~tag~ h~l~s ~ One.
In the pr~nt ca~, we re~ulre to d~t3c'c ~ On~3 ~mong thts ~ bit~, ~nd the carr~ ha~ 8 th~r~ore connelcted in th~ r~er~ dircc~aon to th~ u~ual, ~ ing th~
c~ry a~ln~t th~ ~ir~ction o~ regi~ shl~t. ~h0 ~t~t o th~ carr~ ~h~in i~ p~ovided by the ~a~t staS~, which 18 ~provld3d wl l:h ~p~Al logic l~o~ thio pU~pO81!! .

X~O~,L09~i ~as~ s x . I x i oI ~ I X I o . ~ 1 1 1 1 ~ X 1, 1 . I o I o I o ' o I o I o I o 1 1 I o I ~ I ~.
Q1 1~ ~. I 1 6) 9 ~

R~f~rrln~ igur~ 4~ ~nd 4~, switch 1Pg1 de~l~n~ impl~ n~ing th~ ~On~bits to ~qht" te~t and ~h~
"~an~h~ter C~ry Chain" ~or th~ ~c~lv~ ~tage ~r~ ~hown.
~ch ~wi~6h l~ t~ b~ ~t t~ the "~" pl:~51t~ on if lt~ lnput ha~ thç~ lue O ~lo~) or N ~nd to the "l" p~æ~tlon if lt~
~npu~ ha~ th~ v~lu~ 1 ~ hlgh ~ or y, ~ rhe "~n~-b~ tc P~ight" 1:~3Bt 18 on~r~lled by a "O~e-bl~ t~ Ri~ht" ~ltch ~nd ~ "~R~S~N~ ~TA~ CtP~ T~S~
ST~T~" ~witch, ~ will bs ~on t;h~t wh~ thfl ON~-B~TS TO
~G~ h~ th~ v~lue 1 ~Yj, ~EXT ~T~TI~ OF ~I3 ST~E t~3ces th~ v~lue o~ it8 ~aE8~N~ STATE. Wh~n th~ ON~ S TO ~SG~
ha~ ~h~ o~po~lte ~ralue O lN), N~x~r s~rE O~ T~IS STAG~ k~2~
~ither the ~r~lu~ o~ ~h~ Nl~ lBOU~ ~T L~FT or th~ COIt~PAR~OR
~utput d~p~n~ing on ~h~ ~r~lua o~ it~ PRESEN~ ~T~TE.
The ~'M~h~t~r C~r~y Ch~n" i~ controll~d by "P~S~NT BTAT~ TE~I~ STA~" awitch, It wlll be s~n that wh~n . h~ PRES~ TA~E OF THIS STP.~F ha~ ~h~ v~lu~ O, the ~n~ FROM N}SXT 5~AG~ will be carrled ~O PR~VIOU~ A~.
Oth~rwi~e, th~ ~ignal ie no~ car~i~d ~nd the }~E~ gnal n~t~nt~ will be ~arried TO P~EVIOU~ ~T~E.
One embodi~en~ o th~ pre~n~ lnv~n~on wlll be d~ ibed wi~h ~ar~n~e ~ CMO~ YLS~ brica~ion proces~.
~x~nplary clrcu~ t ~orm~ ~re shows~ ~ n ~iguro6 4C, 4~ and 4 Fi~u~ AC ~ ~ a ~hemst~c circul~ of thR ~ r6t 6t~ge o~ th~ pse#~nt inv~!nti~n ~hows~ in F~u~e 3. I~
~omprl~ 4 lo~lc inverter, N~ND ~t~ ar~d ~l~p-~lop ~lriv~n by CLQCR si~ls. ~h~ REE~T~ n~ ov~ded a~ put ~o th~ ~llp-~lop uhil$~ it~ inver~oa ~ig~ d the ~!lip ~lop vut~?u~ are ~oupled to the N~r ~at~ to provide the output o~
the ~irst ~tage (DA~n ou~)~

~14-Opera'eion of th~ ~ir~t ~t~g~ wlll b~ as ~ollow~:
RE8ET\ ¦ r~ t Q D~A ou~r ¦ X~ET
I o I ~ O 1 1 1 1 1 ~ 1 1 0 ~ I ~

Fl~o ~D i~ ~ ~ch~matic clrc~ait of th~ slc~ve 8~ o~ ~h~ prsa~n~ ~ nvQnt~ or~ shown in Flgure 3 . It ~ib~d~ ~ th~ ~w~ teh lo~ d~ ns ~o~ th~ "On~-bi ~ to Pcigh~" test and th~ nch~st~r C~rry Ch~in" o~ Fi~ur~ 4A
~nd 4B, Thi~ i~ reallæ~ th~ u~ 4~ ~ix transis~o~
pa~-g~t~s ~4ting a~ ~n~logue ~wltah~s in ~h~ ~orm o~
par~ l pals~ o~ co~pl~men~ y tran~ ors~
Xt will~ be ~n that th~ ~llowing ~ e~ui~ lant~
botw~n th~ ~witch logic ~ igrl~ and active ~tzlge cir~lllt.
~q~neh~t~r C~ry ~hain A~tlve Stag~
RE~E~ ~ R~E~
F~OII 2~E~ ~TAG~ C~rry~n To P~$VIOUS æ~A~E ~ C~rryout P~E~NT ~q~ATE 0~ T~I~ ST~t~ I D3.ta C~ut or Q
One-~its to Pight T~st ACtlv~ ~t~
o~-a~ o RlGHT ~ t::~rr~n P~E~ ~G~ OP~ T~IS STAG~ ~ Data ~ut or N~ A~E t:)F T~I S S~A~E ~ D
N15~ UR AT ~EFT I ~ Dat~ In CO~ATO~ output ~ SAR}ow The D~ta .and C:~rry ~hift ~ n oposlte dir~ct1ons .
~h~ value of ~he NEX~ 8~A~ F ~HI8 ~TAG,. (D) i~
prlmar~: ly c~ntsolled by the ONE~BIT~ TO ~IG~ ( C:arry~ n ) slyn~ d ~econd~rily ~y the ~?RE~EN~ SI~A~ OF THIS ST~G~
tDat~ Out) ~gnal. Th~ 8teerlng ~ogic f~ds3 back the or~ginal 6tored v~Jue D~ta Ou~ (Q) to th~ ~oro,~e c~
~llp-flop), when~ver J~D ~ha~ge is r~quired ~C~r~y~n - l).
~!hi~ ad~ nt~geou~ly permit~ t giv~n a hlgh enough clock ~r~gu~ncy) th~ u8e of Dynamlc clrcult ~echn~qu~ ~n ~he -s~or~ge c~

R~r~n~e to Fl~u~ 5 ~which ~how~ typlc~l ~torag~
~ell~ usin~ 8~a~1c ~nd ~yn~mic m~tht)ds ) w~ h~ th~t th~
~ynamic cell ~ui~e~ zlb~ut hal~ th~ el~c~oni~ cul~y ( tran~istor~ lt$ ~at~c cQuntg~p~l:t . ~hl~ s~ving permit~ ~h~ axtra logic o~ th~ n~ n~ on to be ~sali~ed wlth llttl~ ~xtral eirc~ ry l:hnn would be requised nqle r~ ter og ~t~ic des~ o~ th~ p~e~nt ~nvo~at40n ~e~ui~o~ bu~ on0 ~uoh ~gls~r ~ plem~nt a ~R, whl~e p~ioJ: ~t requ~0~ 'cwo, thsr~ n~t savl~sg o~ 8t~
SO% of ~he ~ ed c~xouit~.
Rs~err4r~g b~ck ~o ~gu~ ~D, whan chanq~ 1 permitte~, eith~r th~ ~to~o~ v~lue ~:sr!l th~ preYl ~u~ sta~
(Da~a In~ or the 8~10w 81~nal ~ro3~ the C~M~T0~ i8 lnput to the ~tDra~e coll ¦ D ) .
Nhe~ T\ ~8 ~ hl~h1, the Car~y ~h~ln will ~
aonn~ct~ to a const~nk h~gh whe~ P~ta Out 1~ o hi~h, a:nd th~ ~hllin w~ll also ~nrry ths ~os~tan~ h~ sl~n~l ~rom th~
n~xt ~tag~ ~o thn p~eYlou~ ~A~e whe~ D~a Ou~ .t~ low~ .
Operati~ o~ l:ho ~lv~ S~a~ w~ll be a~ ~ollow~s R~S~T~ I Calrryin I ~a~a In I D~a Ou~ I S~Rlow D i ~arryout 4 ~ I ~ I 1 ~ I ~
o I e t ~ I 1 I o I o ~ I o I x o I
x 1 1 1 x 1 1 o I o ~ o I ~ .
o I 1 1 ~ ~ x 1 1 s:~
:- 1 1 o I x 1 1 1 ~ 1 1 ,'~, 1 1 ~ I x I 1 1 ~ I ~
-~It ii~ noted th~t wh~n RE~T~ 16 ~ow, C~yin ~ ~om ~hc la~t stage) ~nd D~tn ~r~ (from the ~ t st~ wi.ll al~o b~ low. Yu~th~r~ tho val~ o~ 6~Rlow will ~o dependen~ on ~ho E~res~nt st~te of ~to~g~ D~t~ C~ut ) .
~ n re~ R o~ s~ore th~r ~ ~w ~ti~e St~g~s, ~t wlll b~ ~d~nt~gaou~ to p~io~l~al~y reger,ar~
:.:the c~rry-~hain ~lgnal ~y u~e of ~ p~lr o~ inv~rt~ tP
lmprDve lts ~p~ed. Thi~ devi ce 1~ d~scr~e~ ln M~ad ~onw~y, op. cit., and elis~whexe, in connac~ on w~ th r.~1.~ I ~. . r ~ u~ 4~ ~5 ~ ~h~ma~ ui~ ~ th~ t ~
o~ th~ pret~e~t ln~ont;lon ~hown in ~S7ur~ 3. ~t $~nplemente the nM~anch~ Ca~ry Ch~,in~l ~o~ th~ t ~tags in ac~ordanca wl~h the decisi4n ta~lQ th~o~o~ ~bove. ~t will ~e ~een that Complot~ (Q) r~pre~en~ the Pr~e~l~ St~te ~n~
~arryout ropre~st~ th~ M~nc~t~r ea~ry sta~tO
Both th~ Carryout And th~ N~x~ 3~tQ ~P1 ar~
IsUtpUl DIII ~ p~titre N~D gate~ ~n~led by Res~. thR
oth~r ~nput~ t~ t~ ND gat~ ~r~ ou~put~ ~rc~m two ~p~t0 NOR q~e6 . The ~ R ~te for ~:he Ca2~ryoPt ~ bl~d b~f ~hl~ ~ Er~ah~ or ~cquirln~ ~h~ ~alu~ o~ the P~ t BtAtq ~, wh~l~t th~ ~tOR ~a~a ~or ~he Nex~ t~ abl~d the Pr~ent ~t~t~ or ~qui sing ~h~ val ua o~ ~h~
~colld la~t ~t~g~ ~Dat~i~) wh~n Sh~t ~ Er~abl~\ i6 on l~w.
op~rat~l o~ o~ th~ la~ ~t~ w~ll be ~h0 samo At~ ~he de~ 8ion ta~l~ there~or abov~.
The abov~ tla~cr1bed cl rcult ~os a fi~R m~y b~
d thr~ughout emp10y~ny on1y tr~n1stor~ of ~ g1e ~tandA~d ~z~ ~typ~e~11y tho sl~ln~um p~r~itted by ~h~ cho~sn ~abricat~on proce~ hl~ ~k~s thc ~mbodl~n~nt $nh~ren~1 c~mpatibl~ w~th Gat~ Arr~y proce8~es ~nd de~ric~s~
~pp~nd~æ 1 ~v~ imulat~ orl run ~ a 5-bit 6 ~ccordin~ to ~he 1nven~ion~ on th~ 1n~u~tr~-~tanda~d ~lreult ~u1~t~ o~ pr4~m P~?ICB ~ ~rom ~iaros~ Corp~rz~lt~on, Ir~lne, CA~. ~
C~th~r ~o~ n~s of ~che p~en'c inv~n'cion ~ncorpora~e tlmf3nd~nt~ or modi~ications wh~ch wlll be ~ound ~v~ ageous in oer~ application~.
Fiyu~e 6 ~w8 ~he actlv~ ~tag~ circui~ o~ Figu~
4~, modi~isd ~ncluding fu~th3r C~OS tran~is~os ~witeh2E to p~rmi~ tagal; to be ~et to 2~ro by ~ gl~ Clo~k si~n~l ~upon the appl~ ~at~ o~ of R~:SET~ . This ~ay b~
~d~Ant~geou~ ~h~r~ m~ mu~ ~parating sp~od i~ re~u~ ~d.
~ igur~ 7 ~how~ th~ ~ti~ 6tage ~cult o~ r19 ~D, ~u~'cher amend~d ~o p~rmi~ th~ resul~ (at ~ompl~tl~n o~

.

~)0~'6)96 ~on~ lon op~r~tl~Jn) ~o b~ ~hi~t~ ially out o~ th~ S~R, ~hlle ~l~ult~n~ou~ly ~hlf~lny ln Zeros, 1n ræadin~s for tho n~xt conv2r3i ~>n. In this dasign, he Acti~n o R~SET\
~orc~ the ~ o act a~ a $imple ~hlf~ r~gi~t~r. If ~eslE~d, th~ ~A~ oantent~ ay be ~hl~t~ ou~ ( ~or ~x~nlpl~, ~or ~ran~ sion ovor ~ome ~ui~able me~lur~ nd ~mul~neo~s~ly ~h~ed ~a~k ln~o the ~. In thi6 ~a~e, the c~ to r~ or~ the or~ln~ d~ hollld th~ b~
~e~u~ ~ed .
Whil~t th~ primary ~i~ld Q~ u~e the pre~nt ~nven~lon 18 ln ~DC, ~R may als~ ~ln~ ~her ~pplic3~10n~.
For ~xsmpl~, ~n ~ ph~ laoked l~p in whioh ~uch ~ ~R ie employed to p~ovlde ~ ~el~ c~libr~ting property, 80 provi~lng t~l~ranc~ to ~nu~c~urlng proce~s v~ri~tions, a~
di~lo~;otl in ~p~nd~ng Qppl~ c~ti~n ~C~Wa~Q0445 . o~h~
UlSe~6 wil~ occur to ~hoBe ~kill~ in th~ art wh~rfl SAR o~ th~
type h~inb~oro d~ ibc~ ~nay b~ ~oun~ ~uitabl~ i~ar oth~r ~unctlona and purposea, beaides tho~e alre~dy d~ribed.

2~0 ~09~;

D~ 1 . PSPI~::E 9imul ~iD
The fc)ll~win~ tWD ~ ve rc~spsac~tv~}y~, ~ library uf ul a~od 1 D9i ~- ~unct~a Dns y and ~ bi t SAR Y~ccordi ng tD the InventiDn~ ~hlch utililiies ~.ho3c ~imulated ~un~::tiDnG. T~e ~i mul ~ti on re!~ul ts ~r~ ~i ven i n Fi yur6~ Elc t IPuu~D-N~QS' Lo31c Funrti~n~ D R Bro~s NJY. ~ a The-~ ~uncti~ prwl~ e~ sl~ul-tiDnli D~ #~ tYI~ IDQ~IC
unetl~ns.
~ D~lng ~crd en ~olt~ge~Cont-Dll~t 911itth~l r~thee th3n tl~S
tr3n~1~tor5~ thYy rRqulro ~ fr~ctt~n of the e~putin~ rs~ourc~
oth~r#lr~ r~UlrQ~ ~t thr ~lplmu ~f ~ le~s ~ur~t~ ull~tion, Th~y are Intr~ d t~ prDYid~ supprrt fQnrtl~n~ fon elruitli UR~er d-nlDp~Qnt, ~here the aetual loglt l~pJollQnt~ttDn 1~ s~ullltod s~puat~ly. A typlul u~e lr in Idn d nnalDgueidlglt~ u1~ti~Rs t ~here llr"t jf thu c~qputing pD~er 1~ requirsd fDr th~ ~nalo~ur arOQ3.
It .
n 6ener~1 lorJit p-cr.
L~vel~ ~Y f~ls~ 5Y tru~.
l~ut~ lk I SpF
llnl Infinit~ ~v~ltl~rc~ntroll~d r~si~tcr) ~ thre~hDld~ IV, ~Y
t ~at~ ayl - 7n9 t~pic~l f~ t~t~t~ iS~ t~tW~tt~
~ Thll bd#ic Yoltlya~Cantr~lled 6Nltche5 ll~ S tr~ tor~l .~ud~l trOn~ Y~ltch IrDn-l roff~l~9 vD5~1.0 Yan~.O] ;PulldDIm .llod~ s~ v3~1tch (rDn~ rD~ tfYI-O ~3na~.~J ~Pa~ t~
~II~I~-~*~ St~ t~tQ~ t~ }tt~t~
, d~rd ~utput~ d ~taq~ Ipullup ~ lt ~Yitching rat~1 .rubck~ . IDI~ Vdd l~l out rpu~luplldd In 100 ~Pollup ra~i~tor r~lall in wt l~ l~tput l~ la1re C~loll wt 0 5pF IOutpllt ~ y .~nds ~ ~3~VQrte~
.l~ubc~t invert Vdd in ~ut aln Inter O In O tr~ Pul1dD~n ] Ydd ~nt~r ou~ ln~d ;Pu11u~1~tput Mdt . -~ t-t~ t~ 3~ t~rt-~t~ st~ H~
t 2~1n~ut NaND 6Ite - ~e~ tring ~ tltche~
.~utc~t n~r,d2 Vdd ini in2 wt t1nl Intor i~ Inl O tr~ns l~ulld~Kn ~1~2 Inx O ~n~ O ~r~n~
dd ~nt~r flnt 1r~ r~

~nd~
~t*~t~t~ 4~g~ 5~ t~3~ t~

3-lnput ~ANU ~t~ ~ mrle!l ~trlng DF ~l~it~
.~ubtkt nsnd3 Vd~ Inl in~ Ir3 ~ut 3inl int~r Inl Inl ~ tr~n~ IPulldDun 3tn2 ~nl Iny in2 o tra~
nin~ Inr In~ O tr~nl ~I Ydd Int~r 0ut l~d ~PulIu~/DutpQt .211~-t 2-1n~ut NOR 6~t~ - ~hunt ~litrh~
~ b~kt nor~ ~dd inl ln2 out 3~nl intPr O Inl O trms IPulldD#n ~InZ intYr O in2 D tran~
al Ydd Int~r DUt In~d ~Pullup/Ou~p~t .

~lltUYtHY~l~tt~l~t~ttt~lH14~110~gUt~Sl~ ittttttitli`41tMY~
g ~ ~lnput NûR 6~ h~lnt lltdtchn .subtl:t n~r3 ~Idd Inl ln~ In~ ~ut sjnl intu ~ . inl 0 tcin~ ~Pulld~
aln2 int~r O In2 O tran~ 1~u~ldn~n ~ln3 intar O in3 O tr~n~
~I Ydd Int~r wt l~ild IP~llup~Output ~nd ~ P~n~ts ~ ActlvY~Hl~H E~bl~l .~u~ckt hl~s Ydd euntr~l in wt ~Ydd ir ~ du~l~l tor rd~qy~dd O ~ Mei~t~ncy nlth other3 51 inout tPntr~l O pn~
e~ e ~ut ~1: ICa~ I~Dr u~e u dynl~le nud~
,~ndr ~ilff~ ff~fi~ttt~*~t*~ t P~s~-6~ ct~vrLOY En2~1e .III~Ckt l~p~55 Vdt eQntr~l In out ~vdd ~ ~ du~, fur rd~y~'dt O Ir~ ~eon~i~t~ncr llith other~
rl ~Rout ~dd csntrol ~
c~ve wt O ~ IC-O ~For U5~ ynult nodn .en~s }q~t~t~tSl~ t~ tll~i~tO~
t 2-Input XND~ j~t~ llhunt ~ltehe3 .~ekt xnDr Ydd inl in2 wt ~inlInten O inl in2 tr~n~ ~Pnlld~n 9~

~1 V~ IntP~ out IDad ~Pullup/~put .en~t t~*t~t~ q~ t~ s~a~s~Q~ ~t~*~
~ ~yr~iC~ sd ~u~fl~r Islwl~t~ ulge trlg9ered ~fl~p) .lu~sl~t clkbuff Wd tl~c~ ln wt ~1 V~d el~t~ in ~ntl l~pl~s~ IFir~t ~ntl! IGLK-) Ydd intl Int2 laYert sl IIJ~ clDck lnt2 lnt~ hlp~s~ ~gst~n~ gat~ ICLX~) s~ ~d Int3 ~ut InY~rt .rnd~
~ st~4~ 7~ ~t~t~
~ 113~iC~ ~ynchrDnow ~ount~r 9ts~ , tD ~lbll ,~obclt rtrblt ~dd ~LII LD~ar D CE CEout sl V~ CE ~b~r CeJIq xnDr ICwntt ~ ~t CE
s2 Vdd LDb3r c~ q d~n hlp~ J~adtC~u~t s3 Ydt LD3~r ~ din ~ lopa3r ~
Wd ~LK din O cl~tnlff ~Tha ~l~ck~t ~t~ge dd ~ r InY~rt Yd~ ~ CE C~out ~Ip~l~n ~Jh~ c~rry chain ~eelo~ CEwt 0 ~bar O trans ~ nthntllr) , ,~nd~
t~4tt~t~ tii~ t~ ttl~ Ptt~
t i ~t~ lulttpl~er IN.C. U~ pa~ t~ it 13 NOT ~l-t-ral~
.eubc~t ~ tsl Ydl ~EL li~LO IIIHI OUT
xl Ydd 9EL I~L~ DUT lop 2 Vdd aEL l~lNI WT bi~nu .~nd-!

9~; ~

5-1it ~,P.C. ~ Test uf S.~
S~R tunctiDn~ PIDnntrd ~ rhl~t reglot~r Functtr~n~l d~-r~3tr~tiDn, u31ng lde-l~s~d r~llpDnqnt~
t~ndlud dh~ nr te~t~ (po~r, clock, ~ llbr~ryl C.1I~
YYUppl,Y ~dd O
~rl~ elk O pulse~O 5 20n ~n 4n 3~n ~On~
vresnt r~rt ~ pul~etS O I~ n ~n) ~5 blt~' lohg SX7 ~d rs~et renbu imnrt Ylnput Yin O ~.2 ~thl~ wl~lnc~ ~DIt~g~
.~ub~kt Firl~t V~d cll: r~t r~bor ~O 1~uNy ~ir~t ~til~il ~1 Ydd r~!~et re~Je~ DO nrJr2 ~ ~ESET ~Idgs 2 Wd ~1~ r~ ti~ C~ de~-~tDr .ent~
t .aubckt ~ctive Vdd cl~ rurb~r 8R~lr~l ;S~ngl~ S.~.R. ~it ~tn auut ItCin ~nut t anln ~n~ut ~Rr~l~trr lidd~r pt~.
xl ~dd ~DU~ Diu ~RI~ dl llux2tnl ;Input Funr,ti~n ~2 Vd4 ~Ctn dl QDU~ d~ uu~t~l x3 Ydd clk ~ Cout rl~bu~f ~CIoc~ d Buftor dd 0DUt IlCin re~bsr 1iCwt wl~tnl I'Carry rhaln' rs ~nin ~nnut lO~ ~R/~R ladd~ ell tp ~nin ~1 201 31 ~ O Wd ~DUt tran~ Iteh rll~ent~
h ~ O ~r-R~
.-n~

.~ubr~t L~t Vdd cl~ r~ut ~Ehu ~4u~y ~n~l ~t~qe Ydd SE~-t ~ O Il 3u~2t~1 ~Z vdd ~anr 5Ebar t2 nDr2 3 V~d ~R~ dl ~ nDr2 Vdd d2 reu!t ~Cn n~r2 x~ ~dd ~3 ~ d~ ~1Dr2 x~ vdd ell~ D~ 1kbuf~
.Md~
~ t~t*~ t~ t~t~t~
t ~0 vdt clk rts2tre*~r DO ~Ir~t l~t~r~ of Reol~ter i ~1 Vdd cl~ re3bu SARID~ at~g~ 9~R
W O0 ~ 0~R4 ~m5 ACtiY~
:~2 Ydd el~ rnnb~r ~RI~
QO ~ 2 ~ n3 anl ~ctlve ~3 Ydd clk r~b~r ~R~
01 02 l~t ;1C2~n2 ~nS ~ot~ve ~4 Vdd ~1~ r~I~bu 6ARt~
t 02 ~ ~iC4 IIC3nl im~ ~tlve x5 Ydt ~1~ r~bar ~

9~

~1~ Vdd el t r~ t O D~ D~n~ ~CS La3t r~t ~1:0 0 1~ Du~le~l ~a P9PICE g~n no tlDatin~ n~de rd2 ~sne O leq st Df th~ ~DC Loglc .Do~i rCo~p va~itch lron~l rof~leq Yof~.OI v~n~O.OI) ri~t~rt ~nO 0 2~k ;St~rt thll fll~R la~der o~ Vd~ ;o~p~n ~I~R1DII IOItl ~Th~ YDlt~ C~p~rator ~eNp ~e~pln O anS vlll reQ~
~r~ eD~pln O r~ret O trl~n~ ~ulld~m at Re~t .trdh Jn 900r Ul .~rob .~11

Claims (22)

1. A successive-approximation register (SAR) having a single shift register for processing, that is presetting and selectively resetting, a number of bits, wherein said single shift register is arranged to provide bit selection for processing the bits and also to provide desired result accumulation in the processed bits.

2. An SAR claimed in Claim 1, wherein processing of a given bit is arranged to start simultaneously, on the same clock signal, with the completion of processing its immediate preceding bit.

3. An SAR as claimed in Claim 2, wherein the presetting of the given bit is arranged to occur simultaneously, on the same clock signal, with the selective resetting of its immediate preceding bit.

4. An SAR as claimed in Claim 2, wherein a processed bit is recognised by having at least one set bit in the shift direction.

5. An SAR as claimed in Claim 2, wherein the bit being processed is recognised by having no set bit in the shift direction and is itself a set bit.

6. An SAR as claimed in Claim 2, wherein an unprocessed bit is recognised by having no set bit in the shift direction and is itself not a set bit.

7. An SAR as claimed in Claim 2, wherein the next bit to be processed is recognized by having no set bit in the shift direction and having an adjacent set bit in the opposite direction to the shift direction and is itself not a set bit.

8. An SAR as claimed in Claim 2, wherein (a) processed bit is recognised by having at least one set bit in the shift direction, (b) the bit being processed is recognised by having no set bit in the shift direction and is itself a set bit, (c) an unprocessed bit is recognised by having no set bit in the shift direction and is itself not a set bit, and (d) the next bit to be processed is recognised by having no set bit in the shift direction and having an adjacent set bit in the opposite direction to the shift direction and is itself not a set bit.

9. An SAR as claimed in any one of Claims 4 to 8, wherein the status recognition of bits is performed by a Manchester Carry Chain, said chain being arranged to pass information in the opposite direction to the shift direction.

10. An SAR as claimed in Claim 1, wherein initialization of the register occurs upon application of a single clock signal.

11. An SAR as claimed in Claim 1, wherein the register is adapted to provide a bit-serial output.

12. An SAR as claimed in any one of preceding claims, wherein said single shift register comprises an array of stages, said stages including a first stage, a last stage and a number of active stages equal to the number of bits of digital output.

13. An SAR as claimed in Claim 12, wherein the first stage comprises a storage cell and is adapted to provide an output for presetting the active stages.

14. An SAR as claimed in claimed in Claim 12, wherein the last stage comprises a storage cell and is adapted to provide an output for controlling the bit selection for processing the active stages.

15. An SAR as claimed in Claim 12, wherein each active stage comprises a storage cell for storing successive bits of the desired digital output and switches for selective processing of data for said storage cell.

16. An SAR as claimed in Claim 15, wherein each storage cell is implemented in Dynamic Logic and adapted to hold its data as long as clock signals are applied to the register.

17. An SAR as claimed in Claim 15, wherein each switch is implemented in CMOS.

18. An SAR as claimed in Claim 12, wherein (a) the first stage is adapted to provide an output for presetting the active stages, (b) the last stage is adapted to provide an output for controlling the bit selection for processing the active stages, and (c) Each active stage comprises a storage cell for storing successive bits if the desired digital output and switches for selective processing of data for said storage cell.

19. An SAR as claimed in any one of preceding claims comprising only transistors of a single standard size and implemented in gate array devices.

20. An SAR as claimed in any one of preceding claims implemented in VSLI.

21. An SAR as claimed in any one of preceding claims implemented in MOS.

22. An analogue to digital converter (ADC) including SAR as claimed in any one of preceding claims.