CA1235824A - Vlsi mosfet circuits using refractory metal and/or refractory metal silicide - Google Patents
Vlsi mosfet circuits using refractory metal and/or refractory metal silicideInfo
- Publication number
- CA1235824A CA1235824A CA000486052A CA486052A CA1235824A CA 1235824 A CA1235824 A CA 1235824A CA 000486052 A CA000486052 A CA 000486052A CA 486052 A CA486052 A CA 486052A CA 1235824 A CA1235824 A CA 1235824A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- gate
- refractory metal
- silicide
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 61
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 60
- 239000003870 refractory metal Substances 0.000 title claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 5
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 238000005245 sintering Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 56
- 229910021341 titanium silicide Inorganic materials 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 229910000510 noble metal Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 244000187656 Eucalyptus cornuta Species 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000036647 reaction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
VLSI MOSFET CIRCUITS USING REFRACTORY METAL
AND/OR REFRACTORY METAL SILICIDE
Abstract of the Disclosure In the fabrication of VLSI MOSFET circuits, the sheet resistance of polysilicon gates and interconnects and the sheet resistance of shallow source and drain junctions are reduced by using refractory metal or refractory metal silicide. To optimize the use of refractory metal or silicide at the junction and gate regions, the refractory metal or silicide at the gate is made thicker than that at the source and drain by first forming a gate having a refractory metal or silicide content and subsequently forming a thin layer of refractory metal or silicide over the source, drain, and gate regions.
- i -
AND/OR REFRACTORY METAL SILICIDE
Abstract of the Disclosure In the fabrication of VLSI MOSFET circuits, the sheet resistance of polysilicon gates and interconnects and the sheet resistance of shallow source and drain junctions are reduced by using refractory metal or refractory metal silicide. To optimize the use of refractory metal or silicide at the junction and gate regions, the refractory metal or silicide at the gate is made thicker than that at the source and drain by first forming a gate having a refractory metal or silicide content and subsequently forming a thin layer of refractory metal or silicide over the source, drain, and gate regions.
- i -
Description
~23~
This invention relates to the fabrica-tion of very large scale integrated (VLSI) metal oxide semiconductor -field effect transistor (MOSFET) circui-tsO
In the fabrica-tion o-f high performance VLSI MOSFET
circuits polycrystalline silicon (polysilicon) is normally used for gate and interconnect regions. However, the high resistivity of polysilicon gives rise to RC time delays which limit device performance. Also, as the MOSFETs are scaled down to the sub-micron regime, the shallow source and drain junctions result in high sheet resistances.
To reduce the delay due to high sheet resistance of polysilicon gate and interconnects, refractory metal silicide or composite refractory metal silicide/polysilicon compositions have been proposed -for gate and interconr)ects. ("1 um MOSFET VLSI technology:
part VII - metal sil icide interconnection technology - a future perspective", lEEE, Journal of Solicl State Circuits, SC-14, page 291, 1971, Crowder et al).
In adclition, to lower the sheet resis-tance of shallow source and drain junctions, the silicidation of source, drain and polysilicon gate has been attempted and the resulting so-called SALICIDE structure is known, ("An optimally designed process for sub-micron MOSFETS", IEDM, Technical Digest, page 647, l9Sl, Shibata et al). In this SALICIDE technology, source, drain and polysilicon ga-tes of MOSFETS are formed with a silicide layer at the same time.
Sidewall oxide regions are used to separate the source and drain from the gate. In the silicida-tion process, a noble or refractory metal is deposited over the entire surface and then selectively reacted with the underlying silicon a-t the source, drain and polysilicon gate.
After the reac-tion, the unreacted metal is etched off selectively by chemical etchants. ~lo~ever in practice, a thin layer oF metal must be used for the silicidation -for two reasons. Firstly during the silicidation process, silicon is consumed as me-tal silicide is formed. The thickness oF silicon which is to be consumed must be equal or thicker than -the deposited metal thickness, depending on the phase of silicide formed. For example, in the case of -titanium silicide (TiSi2) -the polysilicon thickness is double the thickness of metal. To avoid the formation of Schottky junctions with consequent junction leakage, the thickness oF metal should be less than a quarter of the source and junction depths. The other reason for using a thin me-tal layer is to avoid the formation of silicide over sidewall oxide used to isolate the gate from the source and drain. Any silicide over this region would electrically short the source ancl drain to the gate.
Thus for VLSI MOSFET circuits with source and drain junctions approaching 0.1 micron in depth, the thickness of me-tal used should be less than 200 angstrom units. For a polysilicon gate of about 0.3 micron thickness, the thin layer oF 500 angstrom units of silicide which can be Formed From 200 angstrom units of metal deposited on the gate is not enough to lower the sheet resis-tance to the required order of about 1 ohm/square. In fact~ since the lowest resistivity oF silicide is of the order of 20 um ohm.cm, the sheet resistance of silicide (500 angstrom units) on polysilicon (2000 angstrom units) is higher than 4 ohm~square. Therefore the SALICIDE
technology does not provide optimal sheet resistance of gate and interconnects for submicron clevices.
To overcome these problems there is proposed according to one aspect of the present invention a process for fabricating VLSI
circuits using refractory metal silicide, comprising the steps of:
forming regions of field oxide on a semiconductor substrate; forming gate oxide within device wells defined by the field oxide; forming a conducting gate layer on the gate oxide and defining gate regions therein, the conducting gate layer having a refractory metal or refractory metal silicide content; forming source and drain regions in the semiconductor; forming a thin metal layer over the source, drain and gate regions, the metal layer being in contact with the refractory metal or refractory metal silicide layer of the conducting gate layer;
and forming a thin iunction silicide layer on the source, drain and gate regions using said thin metal layer.
Th~ conducting gate layer can be formed by first depositing a layer of polysilicon and then depositing a layer of refractory metal or refractory metal silicide. The conducting gate layer is alternatively deposited as a single layer of refractory metal such as Mo or W or refractory metal silicide.
The refractory metal silicide can be deposited directly by one of a plurality oF techniques such as co-evaporating, co-sputtering, sputtering of a composite target, or chemical vapour deposition (CVD). The refractory metal can be deposited by evaporation, sputtering or CVD.
The structure should be annealed aFter gate definition although the heat of subsequent oxidation and diffusion stages can also function to lower the gate sheet resistance. The gate regions within the gate conducting layer can be defined by reactive ion 32~
etching. The source and drain regions can be produced by ion implantation followed by annealing. Surface isolating oxide regions for elec-trically isolating the gate from the source and drain regions can be Formed by depositing an oxide layer over the wafer and etching back the oxide by reactive ion etching. Oxide is completely removed over the gate, source and drain regions but no-t at gate sidewall regions where the oxide is initially relatively thick.
The thin junction silicide layer formed over the source, drain and gate regions can be deposited as a refractory me-tal such as Ti and then sintered to form metal silicide where the metal overlies silicon. Other metals such as Co, Ni, Pt and Pd can also be used. Unreacted metal from over the -field and isolating oxide regions is subsequently dissolved. Alterna-tively refractory metal such as tungsten ancl molybdenum can be selectively deposited onto the source, drain and gate regions to shunt the sheet resistance of the underlying layer.
The refractory metal used to form the gate conduc-ting layer can be one oF the group of metals consisting of titanium, tantalum, tungsten and molybdenuln. If subsequent processing is not performed at high temperatures greater than 900C, the noble metals platinum and palladium can alternatively be used in the ga-te conducting layer. The thickness of the refractory metal or refractory metal silicide layer within the gate conducting layer is preferably in the range 1500 to 2500 angstrom units and the refractory metal or silicide iunction layer is preferably in the range 300 to 1000 angstrom units.
Device in-terconnects can be formed simultaneously with ~2~32~
the gate conduc-ting layer.
An embodiment of the invention will now be described by way of example wi-th reference to the accompanying drawings in which:-Figure 1 is a sectional view showing a VLSI MOSFET
5 according to the invention; and Figures 2 to 4 show successive stages in thefabrication of the Figure 1 transistor using a fabrication technique according to the invention.
Figure 1 shows in detail a metal-oxide-semiconductor field effect transis-tor (MOSFET) formed on a p-type silicon substrate 10. Isolating field oxide regions 12 are underlain by p~~-type regions 140 Within the substrate are n+-type source and drain regions 16, 18. Extending between the source and drain regions and overlying a channel r.egion 20 within the substrate 10 is a gate oxide layer 22. Over the gate oxide layer is a yate having a lower 2500 angstrom Ullits thick polysilicon layer 24 ancl a 2500 dngstrom unit thick titanium silicide upper layer 26. A-t side edges oF the gate are isolating oxide regions 28. Laterally adjacent the oxide regions 28 are 300 angstrom units thick titanium silicide layers 30 overlying the source and drain regions 16, 18. A corresponding thin titanium silicide layer 32 also overlies the gate.
Referring to Figure 2, to fabrica-te the device, boron ions are implanted at locations 14 to establish channel stop or isolation regions and a device active area is defined by thermally oxidizing regions of the silicon substrate 10 at 1000~C using a known local oxidation of silicon (LOCOS) technique. As shown in Figure 3 the polysilicon layer 24 is then deposited by low pressure chemical 3~2~
vapour deposi-tion (LPCVD) at 625C and is doped with phosphorus -from a POC13 gaseous source to give a sheet resistance of 40 ohm/square.
Next, the titanium silicide layer 26 is deposited by DC magnetron sputtering a-t ambient tempera-ture using a composite targe-t. After annealing in argon at 900C for 30 minutes, the combined titanium silicide/polysilicon layer yields a sheet resistance of 1 ohm/square.
If MoSi2 and WSi2 are used instead oF titanium silicide, a temperature of 1000C For 30 minutes is required. The resulting structure retains the properties oF a polysilicon/silicon dioxide interface in that the work function of polysilicon on oxide is very well known and a smooth interface can be obtained with good oxide layer integrity. The structure is compatible wi-th other high temperature processing steps used in the fabrication oF integrated circuits. The combined silicide/polysilicon gate layer 24, 26 is then patterned in a reactive ion etching (RIE) system using a chlorine based gas etchant to define the device gate. The gate patterning can also be performed prior to annealing.
~eferring to Figure ~, shallow junc-tion source and drain regions 16, 18 are formed at the source and drain by implanting As~ ions with an energy of 50 kev and a dose of 5 x 1015/cm2 followed by a subsequent annealing step For 30 minutes at 925C. The sidewall oxide regions 28 are produced by low pressure chemical vapour depositing a 0.5 micron silicon dioxide layer over the source, drain and gate and then etching back the layer using reactive ion etching in a fluorine based plasma. Since oxide is thicker at the gate sidewalls and since ma-terial is etched vertically by reactive ion etching, then although oxide is totally removed from over the gate, the sidewall ~3~
oxide portions remain.
The thin titanium silicide layer 32 is then formed by sputter depositing a 300 angstrom unit layer of titanium and then sintering the titanium layer a-t 600C. Where the ti-tanium overlies silicon at the gate, source and drain regions, a thin layer of ti-tanium silicide is -Formed. Ti-tdnium which overlies field and sidewall oxide regions remains unreacted and is removed by etching with a solution composed oF H202:NH~OH:H20 with a volume ratio of 1:1:5. After removing the unreacted titanium, the ti-tanium silicide is again sintered at 800C to further lower the sheet resistance.
Although in the specific embodiment described the silicide present in the gate and over the source and drain is titanium silicide, other silicides such dS those of tungsten, molybdenum and tantalum can also be used and in addition to these refrac-tory metals some noble metals such dS platinunl and palladium can make eFFective junction silicldes~
Although when using titanium in the formation oF the thin junction silicide layer, unreacted titanium must be removed From over the isola-ting oxides, the step oF metal removal may be unnecessary when using other metals. Thus For example, tungsten (~) can be chemically vapour deposited selectively over source, drain and gate from an ambient of WF6o No etching is required since no metal deposition occurs on the oxide regions.
In a further me-thod, the silicide layer over source and drain is formed simultaneously with, and over regions accurately vertically aligned with, the source and drain regions by first ~;~35~2~
depositing the layer oF reFractory metal and then bombarding -the regions with ions of selected conductivity type at an elevated temperature. The ions, for example As+ ions in n-channel devices and BF2~ ions for p-channel devices both pene-trate the silicon to Form a doped source or drain region and have sufficient energy to promote interface mixing between the refractory metal and -the underlying silicon with the resulting formation of silicide, Although in the embodiment specifically described the gate conducting layer is formed by deposi-tion and doping of a polysilicon layer followed by the deposition of a metal silicide layer, the gate conducting layer can alternatively be deposited as a single layer oF re-Frac-tory metal silicide of uniForm composition.
Although the thin layer of metal of the junction silicide layer is consumed by the Formation oF silicide over the source and drain, the metal deposited onto the gate merely renders an upper layer oF the gate rich in the metal. If a deposition/etch method is used then an upper nletal-rich part of the gate layer may be removed when the metdl overlying the oxide layers is etched away. The refractory or noble metal used in the gate silicide Formation may be difFerent From -that used in the gate conducting layer.
This invention relates to the fabrica-tion of very large scale integrated (VLSI) metal oxide semiconductor -field effect transistor (MOSFET) circui-tsO
In the fabrica-tion o-f high performance VLSI MOSFET
circuits polycrystalline silicon (polysilicon) is normally used for gate and interconnect regions. However, the high resistivity of polysilicon gives rise to RC time delays which limit device performance. Also, as the MOSFETs are scaled down to the sub-micron regime, the shallow source and drain junctions result in high sheet resistances.
To reduce the delay due to high sheet resistance of polysilicon gate and interconnects, refractory metal silicide or composite refractory metal silicide/polysilicon compositions have been proposed -for gate and interconr)ects. ("1 um MOSFET VLSI technology:
part VII - metal sil icide interconnection technology - a future perspective", lEEE, Journal of Solicl State Circuits, SC-14, page 291, 1971, Crowder et al).
In adclition, to lower the sheet resis-tance of shallow source and drain junctions, the silicidation of source, drain and polysilicon gate has been attempted and the resulting so-called SALICIDE structure is known, ("An optimally designed process for sub-micron MOSFETS", IEDM, Technical Digest, page 647, l9Sl, Shibata et al). In this SALICIDE technology, source, drain and polysilicon ga-tes of MOSFETS are formed with a silicide layer at the same time.
Sidewall oxide regions are used to separate the source and drain from the gate. In the silicida-tion process, a noble or refractory metal is deposited over the entire surface and then selectively reacted with the underlying silicon a-t the source, drain and polysilicon gate.
After the reac-tion, the unreacted metal is etched off selectively by chemical etchants. ~lo~ever in practice, a thin layer oF metal must be used for the silicidation -for two reasons. Firstly during the silicidation process, silicon is consumed as me-tal silicide is formed. The thickness oF silicon which is to be consumed must be equal or thicker than -the deposited metal thickness, depending on the phase of silicide formed. For example, in the case of -titanium silicide (TiSi2) -the polysilicon thickness is double the thickness of metal. To avoid the formation of Schottky junctions with consequent junction leakage, the thickness oF metal should be less than a quarter of the source and junction depths. The other reason for using a thin me-tal layer is to avoid the formation of silicide over sidewall oxide used to isolate the gate from the source and drain. Any silicide over this region would electrically short the source ancl drain to the gate.
Thus for VLSI MOSFET circuits with source and drain junctions approaching 0.1 micron in depth, the thickness of me-tal used should be less than 200 angstrom units. For a polysilicon gate of about 0.3 micron thickness, the thin layer oF 500 angstrom units of silicide which can be Formed From 200 angstrom units of metal deposited on the gate is not enough to lower the sheet resis-tance to the required order of about 1 ohm/square. In fact~ since the lowest resistivity oF silicide is of the order of 20 um ohm.cm, the sheet resistance of silicide (500 angstrom units) on polysilicon (2000 angstrom units) is higher than 4 ohm~square. Therefore the SALICIDE
technology does not provide optimal sheet resistance of gate and interconnects for submicron clevices.
To overcome these problems there is proposed according to one aspect of the present invention a process for fabricating VLSI
circuits using refractory metal silicide, comprising the steps of:
forming regions of field oxide on a semiconductor substrate; forming gate oxide within device wells defined by the field oxide; forming a conducting gate layer on the gate oxide and defining gate regions therein, the conducting gate layer having a refractory metal or refractory metal silicide content; forming source and drain regions in the semiconductor; forming a thin metal layer over the source, drain and gate regions, the metal layer being in contact with the refractory metal or refractory metal silicide layer of the conducting gate layer;
and forming a thin iunction silicide layer on the source, drain and gate regions using said thin metal layer.
Th~ conducting gate layer can be formed by first depositing a layer of polysilicon and then depositing a layer of refractory metal or refractory metal silicide. The conducting gate layer is alternatively deposited as a single layer of refractory metal such as Mo or W or refractory metal silicide.
The refractory metal silicide can be deposited directly by one of a plurality oF techniques such as co-evaporating, co-sputtering, sputtering of a composite target, or chemical vapour deposition (CVD). The refractory metal can be deposited by evaporation, sputtering or CVD.
The structure should be annealed aFter gate definition although the heat of subsequent oxidation and diffusion stages can also function to lower the gate sheet resistance. The gate regions within the gate conducting layer can be defined by reactive ion 32~
etching. The source and drain regions can be produced by ion implantation followed by annealing. Surface isolating oxide regions for elec-trically isolating the gate from the source and drain regions can be Formed by depositing an oxide layer over the wafer and etching back the oxide by reactive ion etching. Oxide is completely removed over the gate, source and drain regions but no-t at gate sidewall regions where the oxide is initially relatively thick.
The thin junction silicide layer formed over the source, drain and gate regions can be deposited as a refractory me-tal such as Ti and then sintered to form metal silicide where the metal overlies silicon. Other metals such as Co, Ni, Pt and Pd can also be used. Unreacted metal from over the -field and isolating oxide regions is subsequently dissolved. Alterna-tively refractory metal such as tungsten ancl molybdenum can be selectively deposited onto the source, drain and gate regions to shunt the sheet resistance of the underlying layer.
The refractory metal used to form the gate conduc-ting layer can be one oF the group of metals consisting of titanium, tantalum, tungsten and molybdenuln. If subsequent processing is not performed at high temperatures greater than 900C, the noble metals platinum and palladium can alternatively be used in the ga-te conducting layer. The thickness of the refractory metal or refractory metal silicide layer within the gate conducting layer is preferably in the range 1500 to 2500 angstrom units and the refractory metal or silicide iunction layer is preferably in the range 300 to 1000 angstrom units.
Device in-terconnects can be formed simultaneously with ~2~32~
the gate conduc-ting layer.
An embodiment of the invention will now be described by way of example wi-th reference to the accompanying drawings in which:-Figure 1 is a sectional view showing a VLSI MOSFET
5 according to the invention; and Figures 2 to 4 show successive stages in thefabrication of the Figure 1 transistor using a fabrication technique according to the invention.
Figure 1 shows in detail a metal-oxide-semiconductor field effect transis-tor (MOSFET) formed on a p-type silicon substrate 10. Isolating field oxide regions 12 are underlain by p~~-type regions 140 Within the substrate are n+-type source and drain regions 16, 18. Extending between the source and drain regions and overlying a channel r.egion 20 within the substrate 10 is a gate oxide layer 22. Over the gate oxide layer is a yate having a lower 2500 angstrom Ullits thick polysilicon layer 24 ancl a 2500 dngstrom unit thick titanium silicide upper layer 26. A-t side edges oF the gate are isolating oxide regions 28. Laterally adjacent the oxide regions 28 are 300 angstrom units thick titanium silicide layers 30 overlying the source and drain regions 16, 18. A corresponding thin titanium silicide layer 32 also overlies the gate.
Referring to Figure 2, to fabrica-te the device, boron ions are implanted at locations 14 to establish channel stop or isolation regions and a device active area is defined by thermally oxidizing regions of the silicon substrate 10 at 1000~C using a known local oxidation of silicon (LOCOS) technique. As shown in Figure 3 the polysilicon layer 24 is then deposited by low pressure chemical 3~2~
vapour deposi-tion (LPCVD) at 625C and is doped with phosphorus -from a POC13 gaseous source to give a sheet resistance of 40 ohm/square.
Next, the titanium silicide layer 26 is deposited by DC magnetron sputtering a-t ambient tempera-ture using a composite targe-t. After annealing in argon at 900C for 30 minutes, the combined titanium silicide/polysilicon layer yields a sheet resistance of 1 ohm/square.
If MoSi2 and WSi2 are used instead oF titanium silicide, a temperature of 1000C For 30 minutes is required. The resulting structure retains the properties oF a polysilicon/silicon dioxide interface in that the work function of polysilicon on oxide is very well known and a smooth interface can be obtained with good oxide layer integrity. The structure is compatible wi-th other high temperature processing steps used in the fabrication oF integrated circuits. The combined silicide/polysilicon gate layer 24, 26 is then patterned in a reactive ion etching (RIE) system using a chlorine based gas etchant to define the device gate. The gate patterning can also be performed prior to annealing.
~eferring to Figure ~, shallow junc-tion source and drain regions 16, 18 are formed at the source and drain by implanting As~ ions with an energy of 50 kev and a dose of 5 x 1015/cm2 followed by a subsequent annealing step For 30 minutes at 925C. The sidewall oxide regions 28 are produced by low pressure chemical vapour depositing a 0.5 micron silicon dioxide layer over the source, drain and gate and then etching back the layer using reactive ion etching in a fluorine based plasma. Since oxide is thicker at the gate sidewalls and since ma-terial is etched vertically by reactive ion etching, then although oxide is totally removed from over the gate, the sidewall ~3~
oxide portions remain.
The thin titanium silicide layer 32 is then formed by sputter depositing a 300 angstrom unit layer of titanium and then sintering the titanium layer a-t 600C. Where the ti-tanium overlies silicon at the gate, source and drain regions, a thin layer of ti-tanium silicide is -Formed. Ti-tdnium which overlies field and sidewall oxide regions remains unreacted and is removed by etching with a solution composed oF H202:NH~OH:H20 with a volume ratio of 1:1:5. After removing the unreacted titanium, the ti-tanium silicide is again sintered at 800C to further lower the sheet resistance.
Although in the specific embodiment described the silicide present in the gate and over the source and drain is titanium silicide, other silicides such dS those of tungsten, molybdenum and tantalum can also be used and in addition to these refrac-tory metals some noble metals such dS platinunl and palladium can make eFFective junction silicldes~
Although when using titanium in the formation oF the thin junction silicide layer, unreacted titanium must be removed From over the isola-ting oxides, the step oF metal removal may be unnecessary when using other metals. Thus For example, tungsten (~) can be chemically vapour deposited selectively over source, drain and gate from an ambient of WF6o No etching is required since no metal deposition occurs on the oxide regions.
In a further me-thod, the silicide layer over source and drain is formed simultaneously with, and over regions accurately vertically aligned with, the source and drain regions by first ~;~35~2~
depositing the layer oF reFractory metal and then bombarding -the regions with ions of selected conductivity type at an elevated temperature. The ions, for example As+ ions in n-channel devices and BF2~ ions for p-channel devices both pene-trate the silicon to Form a doped source or drain region and have sufficient energy to promote interface mixing between the refractory metal and -the underlying silicon with the resulting formation of silicide, Although in the embodiment specifically described the gate conducting layer is formed by deposi-tion and doping of a polysilicon layer followed by the deposition of a metal silicide layer, the gate conducting layer can alternatively be deposited as a single layer oF re-Frac-tory metal silicide of uniForm composition.
Although the thin layer of metal of the junction silicide layer is consumed by the Formation oF silicide over the source and drain, the metal deposited onto the gate merely renders an upper layer oF the gate rich in the metal. If a deposition/etch method is used then an upper nletal-rich part of the gate layer may be removed when the metdl overlying the oxide layers is etched away. The refractory or noble metal used in the gate silicide Formation may be difFerent From -that used in the gate conducting layer.
Claims (17)
PRIVILEGE IS CLAIMED ARE AS FOLLOWS:-
1. A process for fabricating VLSI circuits using refractory metal silicide, comprising the steps of:-forming regions of field oxide on a semiconductor substrate;
forming gate oxide within device wells defined by the field oxide;
forming a conducting gate layer on the gate oxide and defining gate regions therein, the conducting gate layer having a refractory metal or refractory metal silicide content;
forming source and drain regions in the semiconductor;
forming a thin metal layer over the source, drain and gate regions, said metal layer being in contact with said refractory metal or refractory metal silicide layer of said conducting gate layer; and forming a thin junction silicide layer on the source, drain and gate regions using said thin metal layer.
forming gate oxide within device wells defined by the field oxide;
forming a conducting gate layer on the gate oxide and defining gate regions therein, the conducting gate layer having a refractory metal or refractory metal silicide content;
forming source and drain regions in the semiconductor;
forming a thin metal layer over the source, drain and gate regions, said metal layer being in contact with said refractory metal or refractory metal silicide layer of said conducting gate layer; and forming a thin junction silicide layer on the source, drain and gate regions using said thin metal layer.
2. A process as claimed in claim 1 in which the gate layer is formed by depositing a first layer of polysilicon and a second layer of refractory metal silicide.
3. A process as claimed in claim 1 in which the gate layer is formed by depositing a refractory metal silicide.
4. A process as claimed in claim 1 in which the gate layer is formed by depositing on gate oxide a layer of a refractory metal being one of the group of refractory metals consisting of molybdenum and tungsten.
5. A process as claimed in claim 1 in which the gate layer is formed by depositing a first layer of polysilicon and a second layer of refractory metal which is one of the group of metals consisting of titanium, tantalum, tungsten and molybdenum.
6. A process as claimed in claim 1 in which the gate silicide layer is deposited by DC magnetron sputtering followed by annealing.
7. A process as claimed in claim 1 in which the gate regions are defined within the gate layer by reactive ion etching.
8. A process as claimed in claim 1 in which the silicide of the conducting gate layer is formed by depositing a layer of refractory metal and reacting the refractory metal with adjacent polysilicon.
9. A process as claimed in claim 1 in which isolating oxide regions are formed between the gate regions and the source and drain regions before the junction refractory metal or silicide layer is formed.
10. A process as claimed in claim 9 in which the isolating oxide regions between the gate regions and the source and drain regions are formed by depositing an oxide layer over the wafer and etching back the oxide so as to completely remove the oxide over the gate, the source and the drain and to leave said isolating oxide regions adjacent said sidewalls.
11. A process as claimed in claim 10 in which the junction metal silicide layer is formed by depositing a thin metal layer over the source, drain, gate and oxide regions, sintering the thin metal layer to form silicide where the metal overlies source, drain and gate and dissolving unreacted metal from over the isolating oxide regions.
12. A process as claimed in claim 10 in which the junction refractory metal layer is formed by selectively depositing a tungsten layer over source, drain and gate only.
13. A process as claimed in claim 1 in which the source and drain junctions are produced by ion implantation followed by annealing prior to formation of the junction silicide layer.
14. A process as claimed in claim 1 in which the metal of said metal silicide layer is one of the group consisting of molybdenum, titanium, tantalum, tungsten, platinum and palladium.
15. A process as claimed in claim 1 in which the thickness of the gate silicide layer is in the range 1000 angstrom units to 3000 angstrom units.
16. A process as claimed in claim 1 in which the thickness of the junction silicide layer is in the range 100 angstrom units to 2000 angstrom units.
17. An integrated circuit including a MOSFET having a silicon substrate, a source and drain formed in the substrate with a channel region extending therebetween and a gate overlaying the channel region and separated therefrom by an insulating layer, at least a part of the gate being a refractory metal or silicide layer, the gate, the source and the drain having a top junction refractory metal or silicide layer, the improvement comprising the gate refractory metal or silicide layer being of greater thickness than the junction refractory metal or silicide layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000486052A CA1235824A (en) | 1985-06-28 | 1985-06-28 | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
| GB8606040A GB2177255B (en) | 1985-06-28 | 1986-03-12 | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
| JP12139786A JPS624371A (en) | 1985-06-28 | 1986-05-28 | Manufacture of vlsi circuit using heat resistant metal silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000486052A CA1235824A (en) | 1985-06-28 | 1985-06-28 | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1235824A true CA1235824A (en) | 1988-04-26 |
Family
ID=4130897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000486052A Expired CA1235824A (en) | 1985-06-28 | 1985-06-28 | Vlsi mosfet circuits using refractory metal and/or refractory metal silicide |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS624371A (en) |
| CA (1) | CA1235824A (en) |
| GB (1) | GB2177255B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6266679A (en) * | 1985-09-19 | 1987-03-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| EP0295121A1 (en) * | 1987-06-11 | 1988-12-14 | General Electric Company | Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide |
| US4844776A (en) * | 1987-12-04 | 1989-07-04 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method for making folded extended window field effect transistor |
| GB2253090A (en) * | 1991-02-22 | 1992-08-26 | Westinghouse Brake & Signal | Electrical contacts for semiconductor devices |
| US6387803B2 (en) * | 1997-01-29 | 2002-05-14 | Ultratech Stepper, Inc. | Method for forming a silicide region on a silicon body |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5780739A (en) * | 1980-11-07 | 1982-05-20 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPS5818965A (en) * | 1981-07-28 | 1983-02-03 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0237093B2 (en) * | 1981-01-26 | 1990-08-22 | Tokyo Shibaura Electric Co | HANDOTAISOCHINOSEIZOHOHO |
| JPS5799775A (en) * | 1980-12-12 | 1982-06-21 | Toshiba Corp | Manufacture of semiconductor device |
| US4378628A (en) * | 1981-08-27 | 1983-04-05 | Bell Telephone Laboratories, Incorporated | Cobalt silicide metallization for semiconductor integrated circuits |
| DE3211761A1 (en) * | 1982-03-30 | 1983-10-06 | Siemens Ag | METHOD FOR MANUFACTURING INTEGRATED MOS FIELD EFFECT TRANSISTOR CIRCUITS IN SILICON GATE TECHNOLOGY WITH SILICIDE-COVERED DIFFUSION AREAS AS LOW-RESISTANT CONDUCTORS |
| JPS58175846A (en) * | 1982-04-08 | 1983-10-15 | Toshiba Corp | Manufacture of semicondutor device |
| GB2139420B (en) * | 1983-05-05 | 1987-04-29 | Standard Telephones Cables Ltd | Semiconductor devices |
| JPS60134466A (en) * | 1983-12-23 | 1985-07-17 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| EP0190070B1 (en) * | 1985-01-22 | 1992-08-26 | Fairchild Semiconductor Corporation | Semiconductor structure |
-
1985
- 1985-06-28 CA CA000486052A patent/CA1235824A/en not_active Expired
-
1986
- 1986-03-12 GB GB8606040A patent/GB2177255B/en not_active Expired
- 1986-05-28 JP JP12139786A patent/JPS624371A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB2177255B (en) | 1989-04-26 |
| JPS624371A (en) | 1987-01-10 |
| GB2177255A (en) | 1987-01-14 |
| GB8606040D0 (en) | 1986-04-16 |
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