CA1217246A - Wide band amplifier limiter device - Google Patents
Wide band amplifier limiter deviceInfo
- Publication number
- CA1217246A CA1217246A CA000468532A CA468532A CA1217246A CA 1217246 A CA1217246 A CA 1217246A CA 000468532 A CA000468532 A CA 000468532A CA 468532 A CA468532 A CA 468532A CA 1217246 A CA1217246 A CA 1217246A
- Authority
- CA
- Canada
- Prior art keywords
- amplifier
- circuits
- limiter device
- pair
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/06—Limiters of angle-modulated signals; such limiters combined with discriminators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
- H03G11/002—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general without controlling loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/001—Volume compression or expansion in amplifiers without controlling loop
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- Amplifiers (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An amplifier-limiter device intended to amplify a received signal up to a predetermined value. The device comprises 2n integrated circuits of the emitter coupled logic type which are connected in series, these integrated circuits forming n successive pairs and each pair having associated with it a compensating circuit which compensates for the linear distortion caused by the integrated circuits of the pair.
An amplifier-limiter device intended to amplify a received signal up to a predetermined value. The device comprises 2n integrated circuits of the emitter coupled logic type which are connected in series, these integrated circuits forming n successive pairs and each pair having associated with it a compensating circuit which compensates for the linear distortion caused by the integrated circuits of the pair.
Description
2~
BACKG~O~ND OF THE INVENTION
The present invention relates to an amplifier-limiter device.
It is ~nown that devices of this nature may be utilised, for example, in wide band Hertzian beam receivers. The known devices comprise an amplifier of the automatic gain control type, followed by an amplitude limiter. For particular applications, such as the aiming of the antenna o a receiver at the maximum energy received, it is necessary to have an auxiliary output which supplies a voltage proportional to the power of the signal received. In the case of the known amplifiers-limiters, it is the automatic gain control signal which represents this voltage.
There are no automatic gain control amplifiers produced as integrated circuits which are able to be utilised for the amplifier-limiter devices. This has the result that the amplifier-limiter devices have a comparatively high power consumption and are of high cost.
SUMMARY OF THE INVENTION
The present invention has as its particular object to reduce the aforesaid disadvantages.
This is accomplished by utilising existing integrated circuits of the line receiver type associated with circuits compensating for -the linear distortion introduced by these integrated circuits.
~ ccording to the inven-tion there is provided an amplifier-limiter device which comprises: a signal input and a signal output, 2n integrated logic circuits of the line receiver emitter coupled type (n being an integer ~Z~7~2~6 at least equal to 1), 2n ~ 1 connections for establishing a coupling in series o~ the 2n circuits between the signal input and output, these 2n circuits forming n pairs of successive and separate circuits, and n compensating circuits associated with the n pairs respectively, for compensating the linear distortion caused by the n pairs.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention wil-~ be be~ter understood and other features will emerge from the following description and from the accompanying drawings, in which:-Figure 1 illustrates a first embodiment of anamplifier-limiter device in accordance with the invention, and Figure 2 illustrates a second embodiment of an amplifier-limiter device in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 illustrates an amplifier-limiter device which has added to it a detector assembly providing a logarithmic measurement of the power of its input signal.
The amplifier-limiter device according to Figure 1 may be described as an amplifier-limiter arrangement comprising four amplifiers 1 to 4 formed by integrated circuits coupled in series, with a band pass output filter 7, and with a logarithmic detection assembly associated with this arrangement, the said detec-tion assembly performing a detecting operation on the signals applied to the four integrated circuits and summates the signals obtained by detection by means of an output summator 8-R8.
Figure l shows a signal input E to which is fed the signal which is to be amplified, the signal in question being one which is to be amplified to provide a signal at a constant level substantially equal to o dsm or say l mw at an output ~, and which has to be detected to provide a voltage proportional to the value expressed in dBm of the power of the signal at the input E, to an auxiliary output P. The input E is connected via a decoupling capacitor Co of lnF to the inversion input of the amplifier 1 which like the circuits 2 to 4 is an integrated logic circuit~ of the line receiver type of the emitter coupled kind (referred to in English literature as emitter coupled logic or E.C.L.) which has the dual function of an amplifier and of a voltage limiter. It is a question of MC lOHl16 circuits in this case. The inverting and direct inputs of the amplifier l are connected via a resistor P~lO of 51 ohms and the direct input is connected moreover to a source of voltage Vl of -1.3 volts. The inverting and direct outputs of the amplifier l are connected to a source of voltage V2 of -5.2 volts via, respectively, two biasing resistors Rl3 and Rl~ of 390 ohms. The inverting and direct outputs of the amplifier l are equally conn-ected via a decoupling capacitor ClO,Cll followed by an inductance Ll,L2 of 33 nanohenrys, respectively, to the inverting and direct inputs of the amplifier ~. The inverting and direct inputs of the amplifier 2 are connected via a fixed capacitor Cl of 3.3 pico-farads and a variable capacitor C2 connected in parallel, and these t~o inputs are coupled, respectively, to the ~7:~6 source Vl via two resistors R21 and R22 of 560 ohms.
The connection between the outputs of the amplifier l and the inputs of the amplifier 2, such as has been described, is a low-pass circuit connection. This low-pass inductance-capacitance circuit, which is also referred to as an L-C circuit, comprises the inductances Ll,L2 and the capacitances Cl,C2, being intended to establish a correction of the linear amplitude distor-tions of the pair of amplifiers l-l. As a matter of fact, these amplifiers being formed by the line receivers of the emitter coupled logic type offer a single-pole linear -~ransfer function at the rate of pulsation wn which in the case of the circuits in question corresponds to a frequency Fn of the order of 180 MHz, the L-C circuit formed by the elements Ll,L2,Cl,C2 introduces a transfer function having the form l + j.w r + _ (j.wn)2 wn 2 . wn in which j is the square root of -l, w the rate of pulsation and r the attenuation attributable to the L-C circuit, this transfer function compensating the distortions of the pair 1-2 up to say w = wn for r close to 0.25.
The inverting and direct outputs of the amplifier 2 are connected, respectively, to the source V2 via two resistors R23,R24 identical to the resistors Rl3 and Rl4, furthermore, the inverting and direct outputs of the amplifier 2 are connected -to the inverting and direct inputs respectively of the amplifier 3 via 2L~6 decoupling capacitors C20,C21. Two biasing resistors R31 and R32 of 100 ohms connect the invertiny and direct inputs respectively of the amplifier 3 to the voltage source Vl.
The amplifier 3 is connected to the amplifier 4 by means of a connection identical to that joining the amplifiers 1 and 2, the amplifiers 3 and 4 in this way forming a second pair of amplifiers with their decoupling capacitors C30,C31, their L-C balancing circuit Ll', L2',Cl',C2' and their biasing resistors R33,R34,R41,R42, of which the elements are identical respectively to the elements ClO,Cll,Ll,L2,Cl,C2,R13,R14,R21,R22 and of which the biasing voltages are also the same as for the outputs of the amplifier 1 and the inputs of the amplifier 2.
The inverting output of the amplifier 4 is connected via a biasing resistor R43 of 390 ohms -to the voltage source V2 and via a capacitor Cs of 1 nanofarad following by an impedance matching resistor Rs of 39 ohms, to the input of a filter 7 of which the band is selected as a function of the purpose for which the device is utilised. As above described, the device has a gain between its input E and the resistor Rs which may reach 69 decibels with a pass band extending from 10 MHz to 200 MHz.
The signal P from the auxiliary outpu-t, proportional to the value e~pressed in decibels with respect to a milliwatt (dBm) of the power of the signal at the input E is obtained by the conventional method of logarithmic detection. A detector is situated at the input of the ~2~7Z~6 amplifiers 1 to 4 and the voltages provided by the detectors are summated to yield the output signal P.
For this purpose, the amplifier-limiter according to Figure 1 comprises:
- four decoupling capacitors Cdl,Cd2,Cd3,Cd4 of which a first plate is connected, respectively, to one of the plates of the four decoupling capacitors Co,Cll,C21, C31, that is to say at points or mea$uring the input signals fed to the amplifiers l- to 4 respectively~
- four identical diode detectors in parallel, dl-Rl, d2-R2,d3-R3,d4-R4 each comprising a BAT l9 type diode such as dl, of which the anode is earthed and the cathode is connected to the second plate of the detection de-coupling capacitor having the same index (Cdl for the diode dl), and a resistor such as Rl of which a first extremity is connected to the cathode of the diode having the same index (dl for the resistor Rl), - a summator circuit obtained ky connecting the second extremities of the detector resistcrs Rl to R4 to the "minus" input of a differential amplifier 8 of which the "plus" input is connnected to earth and of which the output which forms the auxiliary output P is coupled via a resistor R8 to its "minus" input, R8 having the value of 1 megohm.
Another embodiment of an amplifier-limiter device in accordance with the invention is shown in Figure 2. This other amplifier-limiter device comprising six amplifiers 1 to 6 analogous to the amplifiers l to 4 of Figure l, connected in series between an input E and an output S and forming three successive pairs ..j.
7~4~
1-2,3-4,5-6 of amplifiers, with each pair having allo-cated to it a circuit compensating for the distortions caused by the pair in question. These three compensating circuits are feedback circuits which act between the direct output of the second amplifier of one pair and the inverting input of the first amplifier of the same pair. Each of the three feedback circuits comprises a resistor Rcl,Rc2,Rc3 of 2.4 kiloohms, connected between the two access points referred to in the foregoing and between which the circuit operates, and a capacitor Ccl,Cc2,Cc3 of 1 nanofaràd, foilowed by a potentiometer Pcl,Pc2,Pc3 of 100 ohms, these two elements being conn-ected between the inverting input of the first amplifer of the pair in question, and earth.
The connections between the input E and the output S of the amplifier-limiter device according to Figure 2 comprise.
- a connection via a capacitor Co between the input E and the direct input of the amplifier 1, - a connection via a capacitor Cs followed by an impedance matching resistor Rs and by a filter 7, similar to the corresponding elements of Figure 1, between the direct output of the amplifier 6 and the output S, - a connection via two conductors between the inverting and direct outputs of the first amplifier of a pair and, respectively, the inverting and direct inputs of the second amplifier of the pair in question, and - a connection via a single conductor between two 7~6 successive pairs, this connection being establshed between the direct output of the second amplifier 2,4 of one pair and the direct input of the first amplifier 3,5 of the following pair.
Figure 2 also shows the biasing resistors for the direct inputs and outputs of the amplifiers 1 to 6, as well as in each pair, the biasing resistors for the inverting output of the first amplifie~- of the pair in question and for the inverting input of the second amplifier of the same pair. These are the following resistors~ R15 connected between ~the direct input of the amplifier 1 and a voltage source Vl of -1.3 volts, R16 and R17 between respectively the inverting and direct outputs of the amplifier 1 and a voltage source V2 of -5.2 volts, R25 between the direct output of -the amplifier 2 and the source V2, R36 and R37 between respectively the inverting and direct outputs of the amplifier 3 and the source V2, R45 between~the direct output of the amplifier 4 and the source V2, R56 and R57 between respectively the inverting and direct outputs of the amplifier 5 and the source V2, and R65 between the direct output of the amplifier 6 and the source V2.
A signal of a constant level equal to 1 mw is provided at its output S by the circuit described with reference to Figure 2. It has a gain of 80 dB and a pass band of 300 MHz. It should be pointed out that the mean gain per amplifier is smaller than in the case of the embodirnent according -to Figure 1, that is to say 80 dB for six amplifiers instead of 69 dB for four amplifiers. By contrast, in this amplifier-limi-ter ~2~ 6 device providing compensation by feedback, the quality of transmission is improved as compared to that obtained with the device according to Fiyure 1.
The logarithmic detection assembly 8' which makes it possible to provide a voltage proportional to the power in decibels with respect to a milliwatt of the signal fed to the input E, has only been denoted by a rectangle in Figure 2. This~permits-simplifying the illustration without impeding a grasp of particular features of the invention. As a matter of fact, this particular logarithmic detection~array is similar to that of Figure 1, except that it comprises three instead of four diode detectors of which the output signals are summated by means of a summator similar to the summa-tor 8-R8 of Figure 1. In Figure 2 moreover, the conductors running from the input E and the direct outputs of the amplifiers 2 and 4 towards the decoupling capaci-tors which are not shown and situated as in Figure 1 at the input of each of the diode detectors of the logarithmic detector assembly,-are shown with references Cel to Ce3. It should be pointed out that the detection assembly of the device according to Figure 2 does, not comprise detection inputs connected to the connections between, respectively, the outputs of the amplifiers 25 1,3,5 and the inputs of the amplifiers 2,4,6 which is because the voltage in these three connections does not represent the signal transmitted from the input E towards the output S because of the negative or inverse f~edback.
The invention is not restricted to the two '724~
-- ~, o embodiments described. The amplifier-limiter device may thus comprise only one pair of amplifiers with i.ts associa~ed compensating circuit or else more than three pairs, each having its compensating circui~, and use may similarly be made of o~her compensating circuits associated with a pair of amplifiers and the compensating circuit may possibly differ from one pair to the next if the number of pairs is at least equal to two.
BACKG~O~ND OF THE INVENTION
The present invention relates to an amplifier-limiter device.
It is ~nown that devices of this nature may be utilised, for example, in wide band Hertzian beam receivers. The known devices comprise an amplifier of the automatic gain control type, followed by an amplitude limiter. For particular applications, such as the aiming of the antenna o a receiver at the maximum energy received, it is necessary to have an auxiliary output which supplies a voltage proportional to the power of the signal received. In the case of the known amplifiers-limiters, it is the automatic gain control signal which represents this voltage.
There are no automatic gain control amplifiers produced as integrated circuits which are able to be utilised for the amplifier-limiter devices. This has the result that the amplifier-limiter devices have a comparatively high power consumption and are of high cost.
SUMMARY OF THE INVENTION
The present invention has as its particular object to reduce the aforesaid disadvantages.
This is accomplished by utilising existing integrated circuits of the line receiver type associated with circuits compensating for -the linear distortion introduced by these integrated circuits.
~ ccording to the inven-tion there is provided an amplifier-limiter device which comprises: a signal input and a signal output, 2n integrated logic circuits of the line receiver emitter coupled type (n being an integer ~Z~7~2~6 at least equal to 1), 2n ~ 1 connections for establishing a coupling in series o~ the 2n circuits between the signal input and output, these 2n circuits forming n pairs of successive and separate circuits, and n compensating circuits associated with the n pairs respectively, for compensating the linear distortion caused by the n pairs.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention wil-~ be be~ter understood and other features will emerge from the following description and from the accompanying drawings, in which:-Figure 1 illustrates a first embodiment of anamplifier-limiter device in accordance with the invention, and Figure 2 illustrates a second embodiment of an amplifier-limiter device in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 1 illustrates an amplifier-limiter device which has added to it a detector assembly providing a logarithmic measurement of the power of its input signal.
The amplifier-limiter device according to Figure 1 may be described as an amplifier-limiter arrangement comprising four amplifiers 1 to 4 formed by integrated circuits coupled in series, with a band pass output filter 7, and with a logarithmic detection assembly associated with this arrangement, the said detec-tion assembly performing a detecting operation on the signals applied to the four integrated circuits and summates the signals obtained by detection by means of an output summator 8-R8.
Figure l shows a signal input E to which is fed the signal which is to be amplified, the signal in question being one which is to be amplified to provide a signal at a constant level substantially equal to o dsm or say l mw at an output ~, and which has to be detected to provide a voltage proportional to the value expressed in dBm of the power of the signal at the input E, to an auxiliary output P. The input E is connected via a decoupling capacitor Co of lnF to the inversion input of the amplifier 1 which like the circuits 2 to 4 is an integrated logic circuit~ of the line receiver type of the emitter coupled kind (referred to in English literature as emitter coupled logic or E.C.L.) which has the dual function of an amplifier and of a voltage limiter. It is a question of MC lOHl16 circuits in this case. The inverting and direct inputs of the amplifier l are connected via a resistor P~lO of 51 ohms and the direct input is connected moreover to a source of voltage Vl of -1.3 volts. The inverting and direct outputs of the amplifier l are connected to a source of voltage V2 of -5.2 volts via, respectively, two biasing resistors Rl3 and Rl~ of 390 ohms. The inverting and direct outputs of the amplifier l are equally conn-ected via a decoupling capacitor ClO,Cll followed by an inductance Ll,L2 of 33 nanohenrys, respectively, to the inverting and direct inputs of the amplifier ~. The inverting and direct inputs of the amplifier 2 are connected via a fixed capacitor Cl of 3.3 pico-farads and a variable capacitor C2 connected in parallel, and these t~o inputs are coupled, respectively, to the ~7:~6 source Vl via two resistors R21 and R22 of 560 ohms.
The connection between the outputs of the amplifier l and the inputs of the amplifier 2, such as has been described, is a low-pass circuit connection. This low-pass inductance-capacitance circuit, which is also referred to as an L-C circuit, comprises the inductances Ll,L2 and the capacitances Cl,C2, being intended to establish a correction of the linear amplitude distor-tions of the pair of amplifiers l-l. As a matter of fact, these amplifiers being formed by the line receivers of the emitter coupled logic type offer a single-pole linear -~ransfer function at the rate of pulsation wn which in the case of the circuits in question corresponds to a frequency Fn of the order of 180 MHz, the L-C circuit formed by the elements Ll,L2,Cl,C2 introduces a transfer function having the form l + j.w r + _ (j.wn)2 wn 2 . wn in which j is the square root of -l, w the rate of pulsation and r the attenuation attributable to the L-C circuit, this transfer function compensating the distortions of the pair 1-2 up to say w = wn for r close to 0.25.
The inverting and direct outputs of the amplifier 2 are connected, respectively, to the source V2 via two resistors R23,R24 identical to the resistors Rl3 and Rl4, furthermore, the inverting and direct outputs of the amplifier 2 are connected -to the inverting and direct inputs respectively of the amplifier 3 via 2L~6 decoupling capacitors C20,C21. Two biasing resistors R31 and R32 of 100 ohms connect the invertiny and direct inputs respectively of the amplifier 3 to the voltage source Vl.
The amplifier 3 is connected to the amplifier 4 by means of a connection identical to that joining the amplifiers 1 and 2, the amplifiers 3 and 4 in this way forming a second pair of amplifiers with their decoupling capacitors C30,C31, their L-C balancing circuit Ll', L2',Cl',C2' and their biasing resistors R33,R34,R41,R42, of which the elements are identical respectively to the elements ClO,Cll,Ll,L2,Cl,C2,R13,R14,R21,R22 and of which the biasing voltages are also the same as for the outputs of the amplifier 1 and the inputs of the amplifier 2.
The inverting output of the amplifier 4 is connected via a biasing resistor R43 of 390 ohms -to the voltage source V2 and via a capacitor Cs of 1 nanofarad following by an impedance matching resistor Rs of 39 ohms, to the input of a filter 7 of which the band is selected as a function of the purpose for which the device is utilised. As above described, the device has a gain between its input E and the resistor Rs which may reach 69 decibels with a pass band extending from 10 MHz to 200 MHz.
The signal P from the auxiliary outpu-t, proportional to the value e~pressed in decibels with respect to a milliwatt (dBm) of the power of the signal at the input E is obtained by the conventional method of logarithmic detection. A detector is situated at the input of the ~2~7Z~6 amplifiers 1 to 4 and the voltages provided by the detectors are summated to yield the output signal P.
For this purpose, the amplifier-limiter according to Figure 1 comprises:
- four decoupling capacitors Cdl,Cd2,Cd3,Cd4 of which a first plate is connected, respectively, to one of the plates of the four decoupling capacitors Co,Cll,C21, C31, that is to say at points or mea$uring the input signals fed to the amplifiers l- to 4 respectively~
- four identical diode detectors in parallel, dl-Rl, d2-R2,d3-R3,d4-R4 each comprising a BAT l9 type diode such as dl, of which the anode is earthed and the cathode is connected to the second plate of the detection de-coupling capacitor having the same index (Cdl for the diode dl), and a resistor such as Rl of which a first extremity is connected to the cathode of the diode having the same index (dl for the resistor Rl), - a summator circuit obtained ky connecting the second extremities of the detector resistcrs Rl to R4 to the "minus" input of a differential amplifier 8 of which the "plus" input is connnected to earth and of which the output which forms the auxiliary output P is coupled via a resistor R8 to its "minus" input, R8 having the value of 1 megohm.
Another embodiment of an amplifier-limiter device in accordance with the invention is shown in Figure 2. This other amplifier-limiter device comprising six amplifiers 1 to 6 analogous to the amplifiers l to 4 of Figure l, connected in series between an input E and an output S and forming three successive pairs ..j.
7~4~
1-2,3-4,5-6 of amplifiers, with each pair having allo-cated to it a circuit compensating for the distortions caused by the pair in question. These three compensating circuits are feedback circuits which act between the direct output of the second amplifier of one pair and the inverting input of the first amplifier of the same pair. Each of the three feedback circuits comprises a resistor Rcl,Rc2,Rc3 of 2.4 kiloohms, connected between the two access points referred to in the foregoing and between which the circuit operates, and a capacitor Ccl,Cc2,Cc3 of 1 nanofaràd, foilowed by a potentiometer Pcl,Pc2,Pc3 of 100 ohms, these two elements being conn-ected between the inverting input of the first amplifer of the pair in question, and earth.
The connections between the input E and the output S of the amplifier-limiter device according to Figure 2 comprise.
- a connection via a capacitor Co between the input E and the direct input of the amplifier 1, - a connection via a capacitor Cs followed by an impedance matching resistor Rs and by a filter 7, similar to the corresponding elements of Figure 1, between the direct output of the amplifier 6 and the output S, - a connection via two conductors between the inverting and direct outputs of the first amplifier of a pair and, respectively, the inverting and direct inputs of the second amplifier of the pair in question, and - a connection via a single conductor between two 7~6 successive pairs, this connection being establshed between the direct output of the second amplifier 2,4 of one pair and the direct input of the first amplifier 3,5 of the following pair.
Figure 2 also shows the biasing resistors for the direct inputs and outputs of the amplifiers 1 to 6, as well as in each pair, the biasing resistors for the inverting output of the first amplifie~- of the pair in question and for the inverting input of the second amplifier of the same pair. These are the following resistors~ R15 connected between ~the direct input of the amplifier 1 and a voltage source Vl of -1.3 volts, R16 and R17 between respectively the inverting and direct outputs of the amplifier 1 and a voltage source V2 of -5.2 volts, R25 between the direct output of -the amplifier 2 and the source V2, R36 and R37 between respectively the inverting and direct outputs of the amplifier 3 and the source V2, R45 between~the direct output of the amplifier 4 and the source V2, R56 and R57 between respectively the inverting and direct outputs of the amplifier 5 and the source V2, and R65 between the direct output of the amplifier 6 and the source V2.
A signal of a constant level equal to 1 mw is provided at its output S by the circuit described with reference to Figure 2. It has a gain of 80 dB and a pass band of 300 MHz. It should be pointed out that the mean gain per amplifier is smaller than in the case of the embodirnent according -to Figure 1, that is to say 80 dB for six amplifiers instead of 69 dB for four amplifiers. By contrast, in this amplifier-limi-ter ~2~ 6 device providing compensation by feedback, the quality of transmission is improved as compared to that obtained with the device according to Fiyure 1.
The logarithmic detection assembly 8' which makes it possible to provide a voltage proportional to the power in decibels with respect to a milliwatt of the signal fed to the input E, has only been denoted by a rectangle in Figure 2. This~permits-simplifying the illustration without impeding a grasp of particular features of the invention. As a matter of fact, this particular logarithmic detection~array is similar to that of Figure 1, except that it comprises three instead of four diode detectors of which the output signals are summated by means of a summator similar to the summa-tor 8-R8 of Figure 1. In Figure 2 moreover, the conductors running from the input E and the direct outputs of the amplifiers 2 and 4 towards the decoupling capaci-tors which are not shown and situated as in Figure 1 at the input of each of the diode detectors of the logarithmic detector assembly,-are shown with references Cel to Ce3. It should be pointed out that the detection assembly of the device according to Figure 2 does, not comprise detection inputs connected to the connections between, respectively, the outputs of the amplifiers 25 1,3,5 and the inputs of the amplifiers 2,4,6 which is because the voltage in these three connections does not represent the signal transmitted from the input E towards the output S because of the negative or inverse f~edback.
The invention is not restricted to the two '724~
-- ~, o embodiments described. The amplifier-limiter device may thus comprise only one pair of amplifiers with i.ts associa~ed compensating circuit or else more than three pairs, each having its compensating circui~, and use may similarly be made of o~her compensating circuits associated with a pair of amplifiers and the compensating circuit may possibly differ from one pair to the next if the number of pairs is at least equal to two.
Claims (5)
1. An amplifier-limiter device which comprises: a signal input and a signal output, 2n integrated logic circuits of the line receiver emitter coupled type (n being an integer at least equal to 1), 2n + 1 connections for establishing a coupling in series of the 2n circuits between the signal input and output, these 2n circuits forming n pairs of successive and separate circuits, and n compensating circuits associated with the n pairs respectively, for compensating the linear distortion caused by the n pairs.
2. An amplifier-limiter device according to claim 1, wherein the n compensating circuits are low-pass inductance-capacitance circuits connected respectively into the n linkages between the integrated circuits of one and the same pair.
3. An amplifier-limiter device according to claim 1, wherein the n compensating circuits are feedback circuits, wherein in each pair, that of the two integrated circuits which is the closest to the signal input comprises a feedback input and wherein for each pair, the associated feedback circuit couples the connection immediately following the pair in question to the feed-back input of that of the two integrated circuits of the pair in question which is the closest to the signal input.
4. An amplifier-limiter device according to claim 1, which comprises a logarithmic detector assembly intended to provide a voltage proportional to the log-arithmic value of the power of the signal to be amplified by the amplifier-limiter device this assembly comprising:
2n detectors respectively coupled to the signal input and to the 2n - 1 connections between the 2n integrated circuits to perform a detecting operation on the signals fed to these 2n integrated circuits, and a summator circuit for performing a summating operation on the signals provided by the 2n detectors.
2n detectors respectively coupled to the signal input and to the 2n - 1 connections between the 2n integrated circuits to perform a detecting operation on the signals fed to these 2n integrated circuits, and a summator circuit for performing a summating operation on the signals provided by the 2n detectors.
5. An amplifier-limiter device according to claim 1, which comprises a logarithmic detector-assembly for providing a voltage proportional to the logarithmic value of the power of the signal to be amplified by the amplifier-limiter device, this logarithmic detector assembly comprising: n detectors respectively coupled to the signal input and to the n - 1 connections between the n pairs of integrated circuits to perform a detecting operation on the signals fed to these n pairs, and a summator circuit for performing a summating operation on the signals provided by the n detectors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8318849 | 1983-11-25 | ||
| FR8318849A FR2555839B1 (en) | 1983-11-25 | 1983-11-25 | BROADBAND AMPLIFIER-LIMITER DEVICE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1217246A true CA1217246A (en) | 1987-01-27 |
Family
ID=9294542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000468532A Expired CA1217246A (en) | 1983-11-25 | 1984-11-23 | Wide band amplifier limiter device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4588956A (en) |
| EP (1) | EP0145568B1 (en) |
| JP (1) | JPS60134613A (en) |
| CA (1) | CA1217246A (en) |
| DE (1) | DE3478549D1 (en) |
| FR (1) | FR2555839B1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4782305A (en) * | 1987-10-02 | 1988-11-01 | Motorola, Inc. | Differential input-single output two pole filter implemented by a single amplifier |
| US4973919A (en) * | 1989-03-23 | 1990-11-27 | Doble Engineering Company | Amplifying with directly coupled, cascaded amplifiers |
| US4984079A (en) * | 1989-07-26 | 1991-01-08 | Hughes Aircraft Company | Video preamplifier circuit |
| JPH0548362A (en) * | 1991-08-13 | 1993-02-26 | Matsushita Electric Ind Co Ltd | Limiter use amplifier |
| JP3040035B2 (en) * | 1992-09-18 | 2000-05-08 | ローム株式会社 | Receiver with intermediate frequency amplification circuit |
| GB2281425B (en) * | 1993-08-27 | 1997-10-29 | Plessey Semiconductors Ltd | Logarithmic detector |
| DE4421072C2 (en) * | 1994-06-16 | 1996-09-05 | Telefunken Microelectron | Circuit arrangement |
| JPH10150333A (en) * | 1996-11-18 | 1998-06-02 | Toshiba Corp | Voltage conversion circuit and differential difference amplifier |
| JP4342111B2 (en) * | 2001-01-30 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | Current pulse receiver circuit |
| US6933781B2 (en) * | 2003-04-30 | 2005-08-23 | Intel Corporation | Large gain-bandwidth amplifier, method, and system |
| KR100651395B1 (en) * | 2004-09-24 | 2006-11-29 | 삼성전자주식회사 | Power amplifier of a transmitter |
| JP4852842B2 (en) * | 2004-11-25 | 2012-01-11 | パナソニック電工株式会社 | Injection mold used for powder injection molding |
| US8480577B2 (en) * | 2005-04-15 | 2013-07-09 | Ivy Biomedical Systems, Inc. | Wireless patient monitoring system |
| US7595697B2 (en) * | 2005-04-15 | 2009-09-29 | Ivy Biomedical Systems, Inc. | Wireless transmitter |
| US7259632B1 (en) * | 2005-08-05 | 2007-08-21 | National Semiconductor Corporation | Method for cascoding amplifiers by modulating isolated power supply reference points |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3909725A (en) * | 1957-03-29 | 1975-09-30 | Massachusetts Inst Technology | Frequency modulation receiver |
| US3678405A (en) * | 1970-08-26 | 1972-07-18 | Rca Corp | Amplifier-limiter circuit with reduced am to pm conversion |
| US4429416A (en) * | 1982-03-26 | 1984-01-31 | National Semiconductor Corporation | Multistage cascade/cascode limiting IF amplifier and meter circuit |
-
1983
- 1983-11-25 FR FR8318849A patent/FR2555839B1/en not_active Expired
-
1984
- 1984-11-20 EP EP84402366A patent/EP0145568B1/en not_active Expired
- 1984-11-20 DE DE8484402366T patent/DE3478549D1/en not_active Expired
- 1984-11-21 US US06/673,936 patent/US4588956A/en not_active Expired - Fee Related
- 1984-11-22 JP JP59247902A patent/JPS60134613A/en active Pending
- 1984-11-23 CA CA000468532A patent/CA1217246A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2555839B1 (en) | 1986-01-24 |
| EP0145568A2 (en) | 1985-06-19 |
| DE3478549D1 (en) | 1989-07-06 |
| US4588956A (en) | 1986-05-13 |
| EP0145568B1 (en) | 1989-05-31 |
| FR2555839A1 (en) | 1985-05-31 |
| JPS60134613A (en) | 1985-07-17 |
| EP0145568A3 (en) | 1985-07-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |