CA1260100A - Security control system - Google Patents

Abstract

ABSTRACT
SECURITY CONTROL SYSTEM
A security and control system for use in a home or building, utilizes a coded audio link between entry detectors/transmitters (12) and relay modules (18), and a digital pulse coded power line communication (PLC) link between the relay modules (18) and a system controller (20) as well as between the system controller (20) and various remotely located slave units (22, 24, 26) which control the energization of lamps, appliances, and alarms. The controller (20) is also adapted to receive coded audio signals directly from an entry detector/transmitter (12). The relay modules (22, 24, 26) and controller (20) include constant false alarm rate receivers for isolating the coded audio signal from background noise, and unique exclusion circuitry for decoding the isolated signal. The PLC messages are generated by impressing a pulse code modulated high frequency carrier signal onto the AC line (30) at selected points in the AC waveform. The location of each carrier frequency pulse relative to the AC line cycle determines the digital value of the pulse. Both before and during a PLC message transmission, the controller (20) and relay modules (22, 24, 26) are adapted to check the status of the AC power line for the presence of either intelligence or excessive noise levels. When operated as a remote control system, unit codes in the PLC messages transmitted by the system controller (20) serve to selectively identify particular slave modules (22, 24, 26). In the security mode, the system has three major states: INSTANT-ARM, ARM-DELAY, and DISARM.

Description

SECURITY CQ~rRDL SYSTEM

The present invention relates to security control systems, particularly to security control systems for installation in buildings or dwellings.
Most conventional securit~ systems fall into tWD main categories: wireless and hard-wired. The wireless systems typically employ ultrasonic or radio frequency signals to ccmn~nicate information from entry sensing devices to central alarms. While such systems generally possess the inherent a*vantage of easy installation, wireless security systems tend to be plagued by a relatively high percentage of false alarms. This is due in large part to the congested state of the airways. In addition, kecause radio frequency signals pass readily through walls of build mgs and hGmes, the possibility of a system in one building falsely triggering a system in an adjacent building is greatly increased. In this regard, it must be borne in mind that even a relatively low false alanm rate of once every several hundred hours of use may be sufficient to cause a loss of confidence in the reliability of a sys~3m.
Hard-wired systems, on the other hand, are generally more reliable and less subject to false triggering. ~owever, hard-wired systems require the installatian of a separate, dedicated wiring system, which or m~st consumers, renders such systems prohibitively expensive.

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~2$~ 0 Accordingly, it is an object of the present invention to provide an improved security control system that is reliabls, relatively inexpensive, and simple to install~
Preferably, a security control system of the present invention combines wireless communication and communication over the existing power lines in a building or dwelling.
The security control system according to a preferred form of the present invention comprise : an entry detector, a signal relay module, a controller, and a slave module. The entry detector is battery powered and adapted to be m~unt~d at each door and window of a home or building. Upon the opening of a protected door or window, a coded audible signal is emitted by the entry detector. The coded audible signal is received eit~er directly by the controller, if located within sufficiently close proximity to the activated entry detector, or by a signal relay module. Ihe signal relay module is adapted to be plugged into a conventional wall outlet and is intended to be place~ in each room or area of the home or building in which an ~2~

entry detector is located. Only one signal relay module is required in each room or area, regardless of the number of entry detectors located in the roam or area. me function of the signal relay module is to receive the coded audible signal emitted by the entry detector and transmit in response thereto a digital pulse coded signal over the power lines to the controller. The controller is also adapted to be plugged into a convention wall outlet and is adapted to receive and transmit digital pulse coded signals over the pcwer lines, in addition to being able to receive coded audible signals directly from an entry detector as previously mentioned. In response to the receipt of a signal either directly from an entry detector or frcm a signal relay module, the controller is adapted to transmit a digital pulse coded alarm signal over the power lines to the slave modules. me slave modules are similarl~ plugged into the wall outlets and serve to control the actuation of various loads, such as an alarm, siren, or lamp, or control the perform~nce of a specified ~sk, such as a telephone dialer. In addition, the controller can selectively address mdividual slave m~dules to provide a user with the ability to remotely control t~le actuation of lights and appliances, or other such loads. Thus, the controller according to the present invention allows the system to function as a security system or as a remote control system.
- W~en operated as a security system, the present system provides tw~ basic modes of operation: ~NSTANT-ARMED and-ARM-DEIAY.
In the INSTANT ARMED mode, the controller is programmed to activate an internal alarm and transmut an alarm signal to the slave modules to immediately actuate the alarm devices upon the receipt of an intrusion ~;~i$~
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signal. This m3de of operation is intended to be used, for example, when a home is occupied at night and the homecwner desires to be instantly notified of an attempted unauthorized intrusion. The ARM-DELAY mode, on the other hand, is used when set~ing the system before leaving the protected premises, so that upon return the cwner is provided with a predetermined time pexiod subsequent to re-entry in which to enter a secret disarm code into the controller to inhibit actuation of the alarm. Unlike conventional security systems in which this delay function is implemented at the controller, in the present system the time delay ~unction is contained within the remotely locaied slave mLdules. ~ore particularly, when in the ARM-DELAY mDde, the controller is programmed upon receipt of an intrusion signal to transmit a coded signal o~er the power lines to the ~emotely located slave units which is effective to initiate a digital timer in each slave unit. Once initiated, the slave units will automatically activate their respéctive loads or perform their respective tasks upon expiration of the predetermined delay period unless a disanm signal is received over the power lines from the oontroller. me controller is programmed to tr~nsmit this disarm signal only upon entry of a-secret user-selected code. Accordingly, it will be appreciated that the present syst~m cannot be defeated by a burglar simply disconnecting or disabling the controller within the time delay period provided in the ARM-DELAY mode.
An additional significant feature of the presen~ security control system consists of the unioue coded audio ccmmunication link between the entry detectors and the signal relay modules and controller(s). In the preferred embodiment, the coded audible signal transmitted by an entry detector upon detection of an intrusion event ccmprises alternating 6 KHz and 7.3 KHz tone bursts with predetermined spacing between successive tone bursts to eliminate echo problems.
The selection of the particular frequencies used in the coded audio link is based primarily on the following considerations: ~l) audible signals provide the cwner with a measure of assurance that the entry detector/transmitters are functioning properly, ~2) the use of signals in the audible frequency range significantly reduces the possibility of one system falsely triggering adjoining systems, and (3) the relatively low degree of natural occurrence of the frequencies.
me audio receivers in the signal relay modules and in the controller function in accordance with the Constant False Alarm Rate ("CF~R") principle to effectively isolate the coded signal from background noise and thereby predictably control the proh~hility of false alarms and provide a predictable signal-to-noise ratio. The audio receivers also include unique decoding circuitry which utilizes the exclusion principle by sequentially looking for the simultaneous presence of the 6 KHz tone and the absence of the 7.3 RHz tone followed by the simultaneous presence of the 7.3 KHz tone and the absence of the 6 KHz tone. The result of these combined features is a highly reliable audio communication link that virtually eliminates the possibility of false alarms.
Also of significance to the security control system according to the present invention is the power line communication technology used to reliably transmit information between the signal relays, controller, and slave modules. Information between the relay, controller, and slave modules is communicated over the power lines by impressing a relatively high freqwency (e.g., 121 KHz) carrier signal onto the power lines. The transmitted messages are in digital pulse coded form with individual binary data bits being represented by a carrier frequency burst or "pulse" that is generated during predetermlned periods of the 60 Hz AC ~aveform. Specifically, a binary "1" is represented by a pulse produced during the first half of the 60 Hz AC waveform and a binary "0" is represented by a pulse produced during the second half of the ~C waveform. Thus, synchronization between the various units is achieved b~ synchronizing the transmission and receipt of the digital pulse coded signals to the 60 Hz AC waveform. In addition, in the preferred embodiment of the present invention the signal relay mcdules and controllers are microprocessor-based and include programmed algorithms for checking the AC power line prior to transmission of a message to determine if another device is already transmitting a meassage or if there exists an unacceptable level of noise on the AC power line which would preclude the reliable transmission and receipt of a mes~age. If either the presenoe of intelligence or an unacceptable noise level is detected, the devices are programmed to execute a randcmly generated time delay before retransmission is attempted. In this mznner, the potential priority conflict over power line access is resolved and the likelihood of tw~ devices creating a perpetual standoff condition is avoided.
To prevent the present security control system from being rendered imoperable by the loss of AC power, the units in the system which rely mainly upon AC power -- namely the signal relay, controller, and certain of the slave units ~- are each provided with battery backup power which is autamatically enabled when primary AC
power is lost. These units also include internal quartz crystal or ceramic resonator oscillator circuits ~hat are utilized to provide the units with accurate timing signals which permlt the units to communicate asynchronously when primary AC power is absent. These internal tim mg circuits also provide the carrier frequency used for power line cc~munication.
Additional objects and advantages of the present invention will become apparent from a reading of the following detailed description of the preferred emkodiment which makes reference to the accGmpan~ring drawings in which:

BRIEF DE.SCRIPTION OF IHE DR~WINGS
Fiyure 1 is a diagrammatical illustration of the security control system according to the present invention showing the various components of the system and their interrelation in a typical mstallation;
Figure 2 is a ti~mg diagram illustrating the power line communication data code formats;
Figures 3A and 3B are timing diagrams illustrating the formats of the relay m~dule messages;
Figures 4A, 4B, and 4C are timing diagrams illustrating the formQts of the controller messages;
Figure 5 is a circuit diagram of the transmitter m~dule of the entry detector;
Figure 6 is a timing diagram of the coded audio signal transmltted by the transmitter module of the entry detector;

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Figure 7 is a circuit`diagram of the relay module;
Figure 8 is a sectional view of the mechanical tuned audio ports m the casing of the relay mcdule;
Figure 9 is a more detailed circuit and block diagram of the CFAR receiver in the custcm integrated circuit contained in the relay module illustrated in Figure 7;
Figure 10 is a circuit and block diagram of the PLC
transmitter portion of the custom integrated circuit of the relay mcdule and controller illustrated in Figures 7 and 12, respectively;
Figure 11 is a block diagram of the PLC receiver portion of the custom integrated circuit of the relay m~dule and controller illustrated in Figures 7 and 12, respectively;
Figure 12 is a circuit diagram of a portion of the controller; and Figure 13 is a circuit diagram of a lamp driver slave m~dule.

DETAILED DESCRIPIION OF THE PR~KKkw EMBODIMENT
Referring to Figure 1 a diagrammatical view of the security control system 10 according to the present invention is shown. The present invention is cap~ble of functioning both as a control system and as a security system. When used as a security system, ~he present invention is capable of detecting an entry at any protected door or window and performing a variety of functions in response- to such detection, including sounding an alarm, activating an tside siren, turn mg on lights, and/or enabling an automatic telephone dialer. In general, the security system comprises: the entry detector 12, the ~2l~0~
g signal relay module 18, the controller 20, and the slave modules 22, 24, and 26. An entry detector 12 is adapted to be loated at each entry point in the protected premises. mus, in a home installation, it is preferable to locate an entry detector 12 at each door and window m the house. me entry detector 12 comprises a msdule 14 which includes an audio transmitter as well as a sensor switching circuit for controlling the enabling of the audio transmitter circuit.
In the preferred embodiment, the entry detector 12 further includes a permanent magnet 16 which is adapted to be mounted to the door or window adjacent to the tran~mitter module 14. Thus, when the door or window is opened, the m~vement of the magnet 16 past the msdule 14 actuates the sensor switch in the transmitter module 14, thereby activating the audio transmitter circuitO As will readily be understood by those skilled in the art, other types of entry sensing devices for providing an GN/OFF switching ignal can readily be substituted for the magnet and reed switch-type sensor utili~ed in the preferred embodiment.
When the entry detector 12 detects an entry, the audio transmitter module 14 is ad~pted to prDduce a coded audible signal that is received either directly by the controller 20 or by a signal relay ~dule 18. me function of the relay module 18 is to relay t~e intrusion signal frcm an entry detector 12 over the power lines 30 to the controller 20. The relay modules are installed si~ply by plugging the devices into conventional 120 volt AC wall outlets. In a typical hame installation, a relay mcdule 18 is therefore required in each room or open ~rea in which an entry detector 12 is located, except for those entry detectors 12 m~nitored directly by a controller 20.

me system controller 20 is similarly adapted to be plugged into a conventional 120 volt AC wall outlet. In addition to receiving and decoding coded audio intrusion signals fram directly m~nitored entry detectors 12, the controller 20 also receives and interprets coded power line signals from the relay modules and ~ransmits coded instruction signals over the Fx~er lines 30 to the various slave modules 22, 24, and 26. mhe slave mcdules 22, 24, and 26 are similarly adapted to be plugged into the wall outlets and comprise either lamp modules 22, appliance modules 24, or alarm m~dules 26, depending upon the particulæ load to be controlled. Any desired number of slave modules may ke distributed thIoughout a home or building. The slave modules reoeive the coded instruction signals over the power lines from the controller 20 and control the energization of the~r respective loads in accordance with such lS instruction signals. mus, in response to the receipt of an intrusion signal, the controller 20 i5 programmed to transmit appropriate instruction signals over the power lines to direct the various slave mcdules 22, 24, and 26 to activate their respective loads.
- In addition, other ~ypes of slave devices, such as automatic telephone dialers, can be advantageously employed. In this regard, it is to be understood that when used as a security system, the present invention contemplates the use of any desired type of alarm response device and that accordingly, when reference is made in the specification and claims to an "alarm device", it is intended to mclude audio and visual alarm response devices, as well as other types of alarm response devices, such as automatic telephone dialers and the like. It should also be noted that the present securit~

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~L1-control system lO contemplates the use of multiple controllers. In such applications, the entry of an operating status change on one controller is Im~ediately communicated over the power lines to the other controller~s) to insure that the operating status of all controllers in a system is maintained the same. In addition, whenever a new secret code is established for a system and entered into one controller, the new secret code is automatically communicated over the pcwer lines to the other controllers m the system.
The present security system is selectively ARMED at a controller 20 for either INSTANT-~RM or ~RM-DEI~Y operation, the latter permitting the occupants to exit and re-enter the protected premises without triggering the alarm. In particul æ , in the ~RM-DELAY mcde, the owner ha5 tw~ minutes in which to exit the premises following arming of the system and 40 seconds following re-entry into the protected premises in which to enter a secret DI5ARM
code into a controller 20 to abort the alarm sequence. Significantly, the mere disabling of a controller 20 within the 40-second delay period will not prevent the slave modules Z2, 24, and 26 from activating their respective loads following the expirati~n of the delay period. As will subsequently be explained in greater detail, this is accomplished by providing the slav~ modules 22, 24, and 26 with internal timing circuitry which ~mplements ~he 40-second delay period ~ollcwing receipt from the controller 20 of a countdown signal.
Thus, practically speaking, the slave modules 22, 24, and 2Ç will only abort their timing function upon receipt of a DISARM signal over ~he power lines 30 from the controller 20.

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In addition, the controller 20 and slave m~dules 22 and 24 of the present system 10 can also be utilized as a central control system for providing remote control of various lamps and appliances.
Specifically, the control signals produced by the controller 20 and transmitted over the power lines 30 include an address or wnit code as well as an instruction code and the various slave modules are program~ed to respond only to ~hose signals having a unit code correspanding to their uniquely assigned address. Thus, the controller 20 can selectively operate the various loads connected to the slave m~dules 22 and 24. For security and reliability reasons, the relay modules 18, controller 20, and slave mcdules 22, 24, and 26 also have associated therewith a house code which prevents power line communications from one system causing an undesired response in an adjoining system. The house code associated with the system 10 is transmitted as part of each coded signal transmitted over the power lines 30.

POWER LINE CCMMUNICATION (PIC) FORM~IS
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Before proce0ding with the detailed description of the various devices in the system, an understanding of the power line communication formats used in the present system is appropriate. The relay n~dules 18 and controller~s) 20 communicate over the power lines by impressing onto the 60 Hz AC line a relatively high frequency carrier signal. The carrier freguency used in the - preferred em~odIment camprises 121 KHz. Information is transmitted between the various units by digital pulse code modulation ("PCM") of the carrier signal. Specifically, and with particular reference to Figure 2, the ~ ~2~t~0 location of the carrier frequency pulse burst relative to the 60 Hz AC
waveform determines the data content of ~he signal. As illustrated in the timing diagrams in Figure 2, if a-carrier frequency pulse burst occurs during the first half of the 60-cycle AC waveforrn, the pulse corresponds to a binary "1". Conversely, if a carrier frequency pulse bNr~Jt occurs during the second half of the 60-cycle AC waveform, the pulse corresponds to a binary "0". ffl us, it wlll be appreciated that a ccmplete cycle of the 60 Hz AC wa~eform is used to transmit each data bit of information in a power line communication message.
Additional data fonmats used in the preferred embodiment include the Double Mark ("~M"), which ccmprises a carrier frequency pulse burst during both the first and second half cycles of the 60 Hz AC waveform, and the Space which corresponds to an absence of a carrier frequency pulse burst during both halves of the 60 Hz AC
waveform. The DM-Data One sequence is used as a preamble to designate the beg mning of a data transmission as the resulting succession of carrier frequency pulses over three consecutive half cycles of the 60 Hz AC waveform represents a condition which ca~not occur during normal data tran~mission of binary l's and 0's. Ihe D~ signal code also serves to provide the reference for identifying the "first" and "second" halves of the Ç0-cycle ~C wavefonm. The double Space for~at is likewise used at the end of each message to designate the end of a data transmission. As will subsequently be seen, this is necessary as the differen~ messages used in the present pcwer line communication system are not all of equal length. Therefore, ~he end of a data transmission must be definitively identified.

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As will further be noted from the tlming diagram shown in Figure 2, the 121 KHz carrier signal data pulses are initiated at the zero-crossing points in the 60 Hz AC waveform. The auration of each carrier frequency pulse burst is preferably one millisecond in a relay message (as shcwn in Figure 2) and 7.33 milliseconds m a controller message.
Turning now to Figures 3A and 3B, the formats of the relay n~dule messages in the preferred emkodlment are shcwn. It will readily be appreciated that a virtually infinlte variety of message formats could be used. The present formats were ~elected as providing an accept~ble campromise between the number of available code selections and signal transmission bandwidth. Importantly, hcwever, by not requiring all system messages to be of equal length, several message formats in the preferred system can be made significantly shorter than others, thus reducing the required ban*width of such transmissions. In addition, due to the overall reliability of the power line ocmmunication technology employed in the present system, it is unnecessary to repeat message transmission to insure proper receipt.
The first relay module message format illustrated in Figure 3A comprises the ALARM message which is transmitted aver the pcwer lines to the oontroller 20 whenever a valid audio signal is received fxcm an entry detector. The relay AL~RM code selected in the preferred system co~prises two successive Double Marks. In addition, each power line comm~nication always includes the transmission of ~he ~yste~m's assigned House Code, which serves to distinguish the power lme comm~nications of one syst~m from those of ~nother~ An eight-bit -lS-House Code is used in the preferred embodiment which provides 28 or 256 possible codes. Following transmission of the House Code, the ALARM message concludes with a double Space.
The second relay module message format illustrated in Figure 3B comprises the LCW ~ATTERY message which is transmitted over the power lines to the controller whenever the voltage level of the backup battery power source is determlned to be below a specified minimum value. The relay LCW ~ATTERY message in the preferred embodiment ccmprises four consecutive Double Marks, followed by the system's assigned House Code and the concluding double Space.
Referring now to Figures 4A, 4B, and 4C, the formats for the power line communication commands for the controller 20 are shown.
When utilized as a central control system, the controller code format is capable of selectively accessing and controlling individual slave modules. The basic message format of a Controller Command Message illustrated in Figure 4A for imple~enting the remote control function includes a Preamble, oomprised of a DM-Data One, followed by an 8-bit House Code, a 4-bit Instruction Code, a single Parity Bit, an 8-bit Unit Code, and the concluding double Space. The state of the Parity Bit in the preferred embodiment is determined by number of binary "1"
bits in the Controller Command Message; a "1" parity bit corresponding to an even number and a "0" parity bit corresponding to an odd number.
The 4-bit Instruction Code identifies the particular task to be performed by the slave module and may, for example, include such remote control functions as "unit on", "unit off", "dim lamp", etc.
The 8-bit Unit Code serves to uniquely identify the desired slave ~cdule to be controlled. As will subsequently be seen from the descri~tion of the lamp mDdule illustrated in Figure 13, a slave m~dule will only respond to a Controller Ccmm~nd Message if the House Code and Unit Code in the message correspond to the paxticular House and 'Jnit Codes preset for that particular slave module.
Additionally, the controller 20 in the preferred e~bodiment is provided with a separate ccm~and illustrated in Figure 4B for turning on or turning off all lamp modules in the system. The format of this command co~prises simply the Preamble, 8-bit House Cbde, 4-bit Instruction Code, Parity Bit, and double Space. In that the ccmmand is intende~ to access all of the lamp m~dules in the system, no Unit Code is required.
The format of the coded messages tran~mitted by the controller when operated in the security mKde differ frcm the format of the command messages described above because security mode instructions are not selectively addressed to a particular slave module. Accordingly, the transmission of a Unit Cbde is not required.
m e basic CONT~DILER STATE CCMM~NDS used when the system is operated in the security mode include: (l) INS~ANT ARM, (2) ARM-DELAY, [3) DISARM, ~4) AI~RM, and (5) CO~NTDoWN. The controller is placed in either of the INSTANT-ARM or A~M-DELAY security mDdes by actuating the appropriate mcde select switch on the front panel of the controller 20. The controller 20 is progra~med to transmit the appropriate INSTANT-ARM or ARM-DELAY CCMM~ND message when placed in either of these armed states for the sole purpose of updating the status of any additional con~rollers which may be included in the system. Whe~ the present invention is used in an application haviny only one controller, the transmission by the controller of an INSTANT-ARM or ARM-DEL~Y status command is not necessary. The ALARM CCMMAND or the COUNTDOWN OOMM~ND is transmitted by the controller in response to the receipt of either a REI~Y AIARM signal over the pcwer lines or a coded audio signal from an entry detector 12. m e ALARM COMM~ND message is transmitted when the oontroller is in the INSTANT-ARM state and the COUNTDoWN COMMAND message is transmitted when the controller is in the ARM-DELAY state. The slave modules are prcgrammed to respond to the receipt of the AL~RM CoMMAND from the controller by immediately performing their respective t~sks. Canversely, the slave modules are programm~d to initiate a 40-second delay timer uFon receipt of the CO~NTDChN CCMMAND from the controller before performing their respective tasks. The DISARM CQMMAND message is transmitted by controller 20 whenever the controller is placed m the DISARM mode.
The controller is switched from the INSIANT-ARM or ARM-DELAY modes to the DI5ARM mode by entering on a keyboard located on the front panel of the controller a secret five-digit oode pre-selected by the cwner.
me slave units are programmed to respond to the receipt of a DISARM
CoMM~ND frQm the controller by ceasin~ to perform their respective tasks if previously activated, or by aborting their 40-second delay timers.
Each of the above-described controller state cGmmand messages uses the same coded format which is illustrated in Figure 4C.
As can be s~en from the diagram, the message is divided into tws segments. The first segment comprises the Preamble, 8-bit House Code, 4-bit Instruction Code, Parity Bit, 8-bit Secret Code, and double Space. The second segment similæly compAses the Preamble, B-bit House Code, 4-bit Instruction Code, Parity Bit, 8-bit Secret Code, and ~ 2~

double Space. me Secret Code in the preferred embodiment ccmprises a five-digit number (each digit comprising a decimal number 1 - 5) in or~er to provide a suitable nu%ber of possible code ccmbinations.
Accordingly, the binary coded decimal representation of the Secret Code requires three bits for each digit or 15 total bits of information. Accordingly, in order to maintain unifonmity in the controller message formats, the message transmission is divided into two segments with the second segment of the message duplicating the first se~ment except for the Secret Code portion of the transmission.
Specifically, the first segment includes the first seven bits of the Secret Code and the second segment includes the last eight bits of the Secret Code. A "0" is arbitrarily inserted into the first slot of the Secret Code portion of the message.

ENTRY DETECTOR (12) Referring to Figure 5, a circuit diagram of the transmitter m~dule 14 of the entry detector 12 according to the present inv~ntion is shcwn. As will be recalled, the transmitter module 14 is adapted bD r~spond to the proxlmate movement of the externally located permanent magnet and produce in response thereto a coded audible signal ccmprised of sequentially alternating 6 KHz and 7.3 KHz frequency tones with predetermlned spacing between successive tones.
With additional reference to Figure 6, a timing diagram illustrating the coded audible signal produced by the transmitter module 14 in the preferred embodiment of the present invention is shcwn. In particular, the coded audible signal generated by the transmitter m~dule 14 ccmprises an initial 6 KHz tone burst of approximately 15 milliseconds in duration ("A"), followed by a 62.5 millisecond pause, and then a second 15 millisecond tone burst at a frequency of 7.3 KHz ("B"). mis alternat mg tone signal is repeated five times ("AEPEPEa~aB") with a 62.5 millisecond gap ket~een successive tones.
me period of the spacing between successive alternating frequency tones is selected to be sufficiently long to eliminate potential echo problem~ (as explained in greater detail below), and at the same time sufficient1y brief to insure that the length of the entire transmission is kept relatively short; i.e., less than three-quarters of a second.
Returning to Figure 5, the transmitter module 14 in the ~referred embodiment is comprised primarily of a custom inbegrated circuit 40 which produces the 6 KHz and 7.3 KHz alternating frequency tone signals in the timed sequence pattern described in Figure 6. m e circuit is powered by a portable 9 volt battery source 42 which is connected to the V~ mput of the integrated circuit 40. In the preferred embodiment the custom integrated circuit 40 includes a low-kattery detection circuit for monitoring the voltage level of the battery 42 and producing a unique low-battery output signal when the v~ltage level of the b~ttery falls below a predetermined level. m e transmitter circuit 14 is energized by placing the internal n~de switch 44 in the ON position. With mcde switch 44 ~n the ON position, the integrated circuit 40 will respvnd to a detected change in the state of switch contact 46 which is responsive to the proximate movement of the externally located magnet 16 (Figure 1). In particular, sensor switch 46 is connected to the (~TR) input terminal of the custcm mtegrated circuit 40 which ccmprises the input to a ~2~

txigger circuit that is adapted to detect a change in the state of either of the switch contact inputs (~TR) and (-TR)~ The external connections shcwn in the circuit dia~ram are provided to permit the transnLitter mDdule 14 to be optionally utilized with any external entry sensor which provides a contact opening or closing.
The custom integrated circuit 40 additionally includes countex circuitry and a sequence coder which is responsive to the trigger circuitxy for contr~ ng the alternating 6 KHz and 7.3 KHz frequency transmission. ~he 6 KHz and 7.3 KHz frequency signals ar~
in turn produced by a freguency divider circuit within the custam integrated circuit 40 which divides down the 32.768 R~Iz frequency signal provided to the OSC-IN and OSC-O~T terminals of the custom IC
40 from a quartz watch crystal 48. The sequence coder in turn feeds an output amplifier that is connected to the transducer 50, which in the preferred e~bodiment ~cmprises a piezoelectric device having a fundamental frequency of 6.5 KHz. It has been determined that a single piezoelectric transducer having a fundamental frequency approxImately midway between the desired output frequencies of 6 KHz and 7.3 KHz can ~e used to produce both frequency tones at acceptable db levels.

SIGNAL REL~Y MODULE tl8) .

Tur~ing now to Figure 7, a circuit diagram of the- signal rel~y ~dule 18 according to the present invention is shown. The function of ~he relay n~dule 18, it will be recalled, is to receive the coded audible signal frcm the entry detector 12 and transmit in response thereto a digital pulse coded signal over the power lines to the controller 23. me relay mcdule 18 in the preferred embcdiment is ccmprised primarily of a power supply circuit 6~, a custom integrated circuit 70, and a 4-bit mucroprocessor 80. The rek~y m~dule 18 is adapted to be plugged into a conventional wall outlet and accordingly receives primary power fram the 120-volt, 60-cycle AC signal. In the event of a loss of primary pcwer, however, a p~rtable battery backup source 54 is also provided. The coded audible signal from the entry detector 12 is received by a transducer 56 which, in the preferred embodin~nt c~mprises a microphone that is mounted at the base of a pair of tuned mechanical ports. With additional reference to Figure 8, the casing of the relay module 18 includes a pair of tuned ports 58 and 59 which can,prise 1/16th wavelength resonators that act as simple mechanical bandpass filters to substantially exclude or attenuate noise and audible signals other than the desired 6 KHz and 7.3 KHz tones emitted by the entry detector 12 prior to the conversion of the tones mto electrical signals by the m1crophone 56.
Returning to Figure 7, the output from the microphone 56 is provided to an mput of the custom inte~rated circuit 70 which corresponds to the input of a constant false alarm rate ("CFAR") receiver for detecting the audio 6 KHz/7.3 KHz signal fro~ the entry detector 12. With additional reference to Figure 9, a m~re detailed circuit and block diagram of the CFAR receiver used in the preferred embodiment of the present invention is shown. Initially, the output signal from the microphGne 56 is provided thxough an amplifier 62 to a broadband bandpass filter 64. The output from the broadband bandpass filter is then provided to a limiter circuit 66 which in turn has its output provided to a pair of narrow bandpass filters 68 and 72 having ~2i~

fundamental frequencies centered at 6 KHz and 7.3 KHz, respectively.
In an en~ironment rich with white noise and multipath si~nals, such as is created when audio signals are transmitted in a house or building, it is important to concentrate the decoding effort on the strongest reflected signal. m e combination of the brcadband bandpass filter, the limiter, and the narrow kandpass filter signal processing accomplishes this by extracting the strongest signal in the spectrum.
More specifically, the limiter circuit 66 serves as a constant energy black box by providing energy to the strongest signals received from the output of the broadband bandpass filter 64. Thus, the limiter circuit 66 accentuates the difference between the strong information signal and the relatively weaker background noise. Note, that if only the narrow bandpass filters 68 and 72 were used, some form of automatic gain control w w ld be required to compensate for differing levels of background noise. Autcmatic ga m control, however, introduces unacceptable delays in the decoding process, in addition to requiring high "Q" bandpass filters which are difficult to implement in inteyrated circuit form. In this regard, it will be appreciated that whereas a receiver with automatic gain control will typically '~iss" a valid signal that occurs immediately following a noise transient, the present CFAR receiver will properly recognize such a signal as the gain in the CFAR receiver is not being constantly - adjusted.
The outputs from the narrow bandpass filters 68 and 72 are provided to envelope detectors 74 and 76, respectively. The envelope detectors 74 and 76 insure that the signals passed by the narrow bandpass filters 68 and 72 are of sufficient duration to constitute ~2~

valid signals. In addition, the envelope detectors 74 and 76 serve to eliminate any short dropouts in the output signals fr~m the narrow bandpass filters 68 and 72 which may occur as a result of the "nulling" of tw~ signals of the same amplitude and opposite phase angle. me outputs from the envelope det~ctors 74 and 76 are provided to a pair of comparators 78 and 82, respectively, which serve as threshold detectors to establish a m mimNm quality level which the received signals must exceed in order to be accepted as valid signals.
In the preferred embodiment, the magnitude of the reference signal provided to the threshold detectors 78 and 82 is selected to be one-half the maximum output level from the narrow bandpass filters 68 and 72.
At this point, the relationship between the operating characteristics of the CFAR receiver and the 62.5 millisecond delay period between successive tones in the audio intrusion signal can now be appreciated. In particular, the delay period in the audio intrusion signal is selected to be of sufficient duration to insure that by the time the 7.3 XHz signal, fsr example, is transmitted, the echoes frcm the previous 6 RHz tran~mission are sufficiently weak so that they are excluded ox "locked out" by the CFAR receiver. mus, only the valid 6 KHz and 7.3 KHz tone signals are alternatively passed by the CFAR receiver which makes possible ~he use of the "exclusion"
circuitry described below.
To ~urther enhance the reliability of the audio communication link, the audio receiver in the relay module 18 additionally includes unique logic gating circuitry which successlvely looks for the presenoe of the 6 KHz signal and the simultaneous absence of the 7.3 KRz signal, followed by the pres~nce of the 7.3 K~z signal and the simultaneous absence of the 6 KHz signal. In particular, the outputs from the two comparator circuits 78 and 82 are provided to inverters 84 and 86, respectively. The output frcm inverter 84 is provided to the input of a first N~D-gate 94 and through another inverter 88 to the input of a second N~ND-gate 92.
Similarly, the output from inverter 86 is provided to the other input of N~ND-gate 92 and through an in~erter 90 to the second input of NAND-gate 94. ~he outputs from N~ND-gates 92 and 94 are in turn connected to analog switching devices 96 and 98, respectively, before being combined and provided through a final inverter 104 to output pin 14 of the custom integrated circuit 70. The ON/OFF ~tates of analog switches 96 and 98 are controlled by a switching signal supplied by microprocessor 80 to input pin 15 of the custom integrated circuit 70.
me switching signal from the microprocessor is provided through a first inverter 100 to the control terminal of analog switch 96 and through a second inverter 102 to the cantrol terminal of analog switch - 98.
The logic gat mg circuitry Gperates in the following manner.
When a vRlid 6 R~Iz frequency pulse signal is received, the output of comparator 78 will go HI, thereby providing a HI input signal to N~ND-gate 92. However, the output of N~ND-gate 92 will not go HI
unless there exists simultaneously the absence of a 7.3 KHz signal so that the output of ccmparator 82 will be LO. In other w~rds, ~he output of NAND-gate 92 will go HI only when the output signal from co~parator 78 is HI and the output signal from comparator 82 is ~O.
Similarly, when a valid 7.3 KHz frequency pulse signal is subsequently received, the output fro~ ccmparator 82 will go HI, there~ providing ~2i~

a ~I signal to the input of N~ND-gate 94. Hcwever, the output from N~ND-gate 94 will not go HI upon receipt of the HI signal from comparator 82 unless the output signal from comparator 78 is also LO.
Accordingly, the output from N~ND-gate 94 will go Hl upon the receipt of a 7.3 KHz signal only if a 6 K~z signal is simLltaneously absent.
The analog switching devices 96 and 98 connected to the outputs of NPND-gates 92 and 94, respectively, are alternatively rendered conductive and non-conductive by the switching signal supplied by the microprocessor 80 to input pin 15 of the custom integrated circuit 70. The microprocessor 80 is programmed to look for the presence of valid 6 KHz and 7O3 KHz signals within predefined "windcws". Returning m~mentarily bD ~he timung diagram of the coded audio signal in Figure 6, the microprocessor 80 is programmed to look for valid 6 KHz and 7.3 KHz pulse si y ls within predefined 20 millisecond windows which are centered around the expected locations of the 15 millisecond pulse tone signals. To acoomplish this, the micr~processor 80 synchronizes to th audio transmission from the entry detector 12 following receipt of the first valid 6 gHz signal burst by waiting for a time period 2.5 milliseconds less than the full 77.5 millisecond period between the leading edges of successive alternating tone bursts and then looking for a valid 7.3 KHz tone burst signal within the follcwing 20 milliseconds. Although the tone signals produced by the entry detector 12 ha~e a duration of 15 milliseconds, the microprocessor 80 is programmed to accept-as a valid signal a tone burst of at least 7.5 milliseconds in duration, as "drop-outs" may occur within the full 15 millisecond period. In addition, the microproeessor 80 m the preferred em~cdiment is programmed to accept as a valid coded audio signal the receipt of any three successive valid alternating tone signals. In other words, a valid entry detector signal is presumed to have been detected follcwing receipt of a proper 6 KHz-7.3-KHz-6-P~Iz tone sequence or a proper 7.3-KHz-6-KHz-7.3-KHz tone sequence. Thus, given the fact that the coded audio signal transmitted by the en~ry detector 12 repeats the 6-KHz-7.3-KHz tone sequence five times, the present system provides a significant margin for error to insure ~hat the coded audio signal is reliably detected by the relay mcdule 18.
Once the microprocessor 80 m the relay n~dule 18 determines that a valid coded audio signal from an entry detector 12 has been received, the REL~Y AL~RM power l me carrier signal is transmitted over the power lines to the controller 20. m e PLC transmitter circuit in the preferred embodimEnt is incorporated in the custom integrated circuit 70. A block diagram of the PLC transmitter in the relay mDdule 18 is illustrated in Figure 10. The PLC signal, it will be recalled, comprises a pulse code n~dulated 121 KHz carrier frequency signal that is synchronized to the zero-cr~ssing points in the 60 Hz AC waveform when AC pcwer is present. The 121 KHz carrier frequency signal is produced from a 484 K~z oe ramic resonator that is connected to the OSC1 and OSC2 inputs of the custom integrated circuit 70. The OSCl and 0SC2 inputs ~eed an internal oscillator circuit llO
which produces a 484 KHz oscillator output signal. The 484 KHz oscillator signal is provided to a frequency divider circuit 112 which produces a 242 RHz output signal on line 114 and a 121 KHz output signal on line 116. Both the 242 KHz signal on line 114 and the 121 K~z signal on line 116 frcm divider circuit 112 are provided to a ~l2~

logic gating circuit designated 118. Iogic gating circuit 118 serves to reduce the 50 percent duty cycle of the 121 X~lz signal on line 116 to a 25 percent duty cycle on line 120. The resulting signal on line 120 is then supplied through a driver amplifier circll t 122 t~ the PLC
OUT terminal (pin 7) of the custom integrated circuit 70. The transmission of the 121 KHz signal through the logic gating circuit 118, hcwever, is controlled by the microprocessor 50 which supplies the enable signal to the PLC EN~BLE input Ipin 16) of the custam IC
70O mus, the microprocessor 80 controls the timing of the transmission of the PLC signal bursts.
Returning to Figure 7, the microprocessor 80 receives a 60 Hz zero-crossing signal on line 124 from the power supply circuit 60 for timing the PIC signal transmissions in accordance with the pulse ccded formats described above. The selected HOUSæ CODE for the system 15is supplied to microprocessor 80 via the setting of switches 126. The resulting PLC OUT signal from the custom IC (pin 7) is impressed onto the power lines via an output driver device 126 and a coupling transfonmer 128 which is connected across the 120 volt - 60 Hz outlet 52.
20In vi~w of the fact that a single power line ccmmunication "channel" is being used in the present system to transmit messages to and from v æious devices, the potential problem is presented where more than one device may attempt to transmit a message at the same time. The potential ~or this problem arising is particularly acute in Z5 a security system where simultaneous detection of the same ev~nt by more than one device is a real pvssibility. To avoid the problem of "collision" and the resulting scramble of messages it creates, the -28~ O

microprocessor 80 in the relay module 18 (as well as the microprocessor in the co~troller 20) is programmed to interrogate the power line bef~re beg m m ng a transmission to determine if intelligence or an excessive amount of noise is present on the line.
If either condition is detected, the microprocessor 80 will delay the transmission of its ~C message.
This "anticollision" feature of the present invention is implemented in the follcwing manner. Due to the type of PLC ~cding formats used in the present system, it is necessary for there to be an absence of a 121 KHz carrier frequency signal on the power line for at least three complete ~C line cycles before the lack of intelligence on the line can be presuned. Accordingly, the microprocessor 80 is programmed to interrogate the line for three complete ~C line cycles of "quiet time" before transmission of a PIC message is commenced. In addition, the microprocessor 80 is also programmed to interrogate the AC line for ~oth the presence of intelligence and/or excessive noise during the transmission of a PIC message as well. In particular, it will be recalled from the description of Figure 2 that the 121 KHz carrier frequency occurs only during one half of any given cycle of ~he 60 Hz AC waveform to produce a coded binary "1" or "Olo Accordingly, the microprocessor 80 is progra~med to interrogate the power line for the presence of intelligence and/or excessive noise during this "unused" half cycle of the AC waveform when transmitting a PLC message~ -In the preferred embcdiment of the present system, the interrogation of the pGwer line for the presence of intelligence or unacceptable noise levels is acoomplished in the following manner.

m e custom integrated circuit 70 in the relay mcdule 18 also includes a PLC receiver circuit for this purpose, even though the relay mcdule is only adapted to transmit PLC signals. The signal off the power line from the coupling transformer 128 is provided to the PLC IN input ~pin 20) of the custom IC 70 through a bandpass filter circuit 130 h~ving a center frequency corresponding to the P~C carrier frequency of 121 KHz. With additional reference to Figure 11, a block diagram of the PLC receiver circuit in the custom IC 70 is shown. The filtered AC input signal is provided to a threshold ccmparator circuit 132 which compares the incoming signal to an xternally established threshold supplied to pin 1 of the custom IC 70. m e output signal from oomparator 132 is rectified by rectifier 134 and provided to a peak detector and signal averager circuit 136 which produces a DC
level signal at its output. The DC output signal from circuit 136 is then provided through a second oomparator circuit 138 having an internally established threshold before pass m g to the P~C OUT tpin 18) terminal of ~he custam IC 70.
m e microprocessor 80 is programmed to detect the presence of Lntelligence or excessive noise on the AC p~wer line by examining the signal supplied frcm the output of the PLC receiver circuit at pin 18 of the custom IC 70. In particular, the microprocessor 80 in the preferred emkodiment is pr~grammed to sample the PLC OUT line signal at approximately a 150 microsecond sample rate. If a continuous signal of more than 400 microseconds in duration is detected, the presence of intelligence is presumed and the microprDcessor 80 will "standoff" ~i.e., wait). In addition, the micropr w essor 80 is - programmed to count the number of noise spikes detected over a predetermuned time period in the output signal from the PLC receiver circuit at pin 18 of the custom IC 70, and if the count total exceeds a predetermined number, to standoff as in the case of an intelligence "collision". In either event, when the presence of intelligence or excessive noise has been detected, the microprocessor 80 is programmed to execute a time delay of random duration before transmission is again attempted. In view of the duration of the CONTROLLER CCMMAND
and CONTROLLER STATE MESSAGES (Figures 4~ and 4C) -- the longest PLC
message formats used in the system - the random delay period in the preferred embodiment is selected to be between 400 ~illiseconds and 2 seconds. (Note, that the OONTROLLER STATE ME~S~GE illustrated in Figure 4C is transmitted in tw~ parts so that ~he required random standoff delay period is not excessively long.) All of the relay modules 18 and controllers 20 in the system are programmed to function in the same manner in this respect. Accordingly, by having each device in a potential collision situation execute a random time delay, the priority conflic* over access to the AC power line is resolved in an arbitrary manner. Thus, the likelihocd of tw3 devices creating a perpetual standoff condition is avoided.
Lastly, the relay module 18 in the preferred embodiment includes an LED 139 (Figure 7) that is connected to the 01 output port of the microprocessor 80. The microprocessor 80 is programmed to energize the LED 139 for 30 milliseconds when a valid coded audio intrusion signal has been received, and flash the LED 139 at a rapid 25 rate whenever the voltage level of the battery 54 falls below a predetermined m~ni~rnum (ass~ning, of course, that AC power is present).

~2~

CONTROLLER ~20) Referring now to Figure 12, a partial circult diagram of the controller 20 according to the present invention is shown. me controller 20 oomprises the pximary interface between the ~ystem 10 and the user. The controller ~0 in the preferred e7~nbodiment includes an LCD display for displaying system status information and for labeling the five keys on the key~oard. me keyboard a~ditionally includes dedicated keys for the ALL LIGHTS ON, ALL LIGHTS OFF, and SECRET CODE functions. As will be recalled from the system description above, the controller 20 is adapted to receiv~ PLC coded messages from the relay mcdules 18, or coded audio intrusion event signals directly from an entry detector 12, and in response thereto transmit PLC coded messages to the various slave modules 22 in the system. In addition, the controller 20 is adapted to receive PIC
messages from other controllers in the system indicating the major state status of the other syst~m controllers, the entry of a new secret code, or other information (e.g., parity check) which may be communicated to ~he controllers. In the pre~erred ~mhodiment, the major state statu of a controller is communicated over the pcwer lines every 15 munutes and at each major state change to insure that all controllers in the system are always m the same state. The major states in the pxesent system which are communicated over the power lines ccmprise the non-transibory states associated with the security mode of operation of the controller and include INSTANT-ARM, ARM-DEL~Y, and DI5ARM.
m e various states of the systEm controller in the preferred embcdLment are summarized below.

- ~2~

a) DI5~RM ST~IE. lhe DISARM state oomprises one of the three ma~or security states of the controller and is the state to which most non-security related states connec*~
b) TEST STAI~. The TES~ state is used to perform a camplete test of the installed security system. When in this state, the controller will transmit a PIC coded ALARM nessage to the various slave modules, ~ollowed two seconds later by a DISARM message. In addition, the user can test oFerate all of the entry detectors 12 in the system by manually activating the entry detectors and the controller will transmit an ALL LIGHTS CN message followed ~w~ seconds later by the ALL LIGHIS OFF message. In addition, the controller will activate its internal alarm during this twc-seoond perio~l.
c) ALL LIGHTS oN. This is a transitory state which issues the PLC command message ALL LIGHTS ON.
d) ALL IIG~TS OFF. This is a transibory state which issues the PLC ocmmand message ALL LIGHIS OFF.
e) P~NIC ~L~RM. This is a transitory state which issues ~he PLC command message ALARM, and is entered, regardless of the current state of the system, by simultaneously holding dcwn the ALL LIGHTS CN and ALL IIG~IS OFF buttons for longer than one-half second. Gnce entered, the PANIC AL~RM state behaves exactly like an intrusion alarm and can be ~xited either by inputting the secret code or by waiting out the 15-minute alarm timer.

~2~3~0 f) IN ERROR. miS is a transitory state which informs the user of an incorrectly entered number during a disarm code input or a new secret code input. This state issues a 100 millisecond low volume beep on the controller's internal alarm and blanks the display for one-half second.
g) PoWER APPLIED. miS is the state entered when p~wer is initially applied to the controller either frcm connecting a battery or plugging the controller into an AC outlet. miS
state stores lllll as the secret code and flashes all the display segments on and off until the secret codP button is pushed and a new secret code entered.
h3 SECRET CODE INPUT. miS state is entered whenever the secret code button is pushed and the system is in the DISARM, TEST, or PCWER APPLIED states. The button must be held down for the entire operation of inputting the five numbers in the secret oode. Upon release of the button, the secret oode is autcmatically stored.
i) INSTANT-ARM. This state comprises one o~ the three major system states. In this state, the receipt of either a coded audio signal from an entry detector or a PLC relay alarm signal results in an ~mmediate transition to the AL~RM
ACTION state. The INSTANT~ARM state can only be entered by depressing the INSTANT-ARM button for at least .75 seconds, or by receipt of an INST~NT-ARM state message over the power lines from another controller. In addition, this button will only be labeled INSTANT-ARM on the display when the controller is in the DISARM state. Accordingly, this state ~6~

can only be entered frcm the DISARM state and can only be exited from by inputting the correct secret code.
j) ALARM ACTION~ This state comprises the principal state for executing a systemrwide alarm. Assuming the system is in an armed state, this state can be entered ~ollowing receipt of a coded audio signal from an entry detector or a PIC alarm message from a relay mcdule. In addition, this state can also be entered by the simultaneous actuation of the ALL
LIG~TS ON and ALL IIGHTS OFF switches. This state is active during the entire 15-m mute alarm period and can only be tenminated prior to the 15-munute time-out by correct entry of the secret code.
k) ~LARM TIMæ-OUT. ~his state is an extension of the previous ALAR~ ACTION state and represents the actions taken when the 15-minute alarm tiner times out.
1) DISARM C~DE INPUT. This state is entered when the display labels the keys with numbers and a number button is pushed.
The five-digit secret code is entered and ccmpared with the stored code. Or, if the secret code button is also depressed and the controller is in either the DISARM, TEST, or POWER APPLIED states~ the five~digit number entered is stored as the new secret code.
m) ARM-DELAY. This- state comprlses one of the three major controller states. m e AaM-DELAY state can only be entered from the ARM ENABLE state. ~his state is exited upon receipt of a P~C relay alarm message or a coded audio alarm signal fram an entry detector, or by inputting the correct secret code.
n) COUNTDCWN DEL~Y. This state represents the 40-second counter which counts dawn from the receipt of an intrusion message to the ALARM ACTION state. This countdown state is also responsible for controlling the 40-second countdown indicator in the display and for transmltting the PLC
CCUNTDOWN message to the slave modules.
o) ARM EN~EIE. This state is entered by receipt of an ARM-DELAY state message over the p~wer lines from another controller or by depressing the ARMED DELAY button for at least .75 seconds, and represents the transition state between the major controller states of DISARM and ARMED
DELAY. The controller will complete the transition to the A~ DEL~Y state after the ARM EN~BLE state is entered upon either the elapse of 40 seconds after the detection of an exit event from the protected premises or after tw~ mmutes has elapsed without an exit event frQm the time the ARM
DELAY ~utton is depressed. The secret code can ke entered dur mg this time to abort this state and return the controller to the DISARM state.
p) LOW ~A'~ l REL~Y. miS is a transitory state which is entered when a LOW ~ATTERY PLC message is received fram a relay module in the system indicating that the r~lay module has a low battery condition. m e only action taken by this state is ~o tùrn on the "low battery relay" flag in the - controller display and to start the lcw battery time-out counter. In order for this low battery flag to stay set in the controller display, a LCW ~ATTERY PLC relay message must be received continuously ~etween 3- and 16-minute intervals, otherwise the flag is reset.
q) LCW RATTE~Y OONTROLLER. mis is a transitory state entered when a test of the controller battery indicates that a controller low battery condition exists. me only action taken by this state is to turn on the "low battery controller" flag in the controller display.

Returning to the circuit diagram in Figure 12, the controller 20 ccmprises m general a power supply 146, the same custom integrated circuit 142 used in the relay m~dule 18, and an 8-bit microprocessor. In addition, the controller includes a display board (not shown) which contains a conventional LCD display driver and the various switch contacts for the buttons appearing on the keyboard panel of the controller. The mlcroprocessor 140 controls the LCD
display driver on the display board via output ports B0-B2 and is connected ~o the various switch contacts on the display board via input p~rts D0-D7. The input ports D0-D7 of the microprocessor 140 are also connected to two rotary thumb switches 150 located on the bottom panel of the controller for settmg th8 system house code.
The function and operation of the custom integrated circuit 142, including the interface circuitry between the custcm ~C and the 120 volt - 60 ~z AC line, is identical to that contained in the relay module 18. Accordingly, the controller 20 receives information off the AC pawer line and transmits information onto the AC pcwer line in the same manner as the relay module 18. Of course, whereas the controller 20 decodes and interprets received PLC messages, the relay m~dule 18 merely identifies the presence of PLC messages on the line for anti-collision purposes. Andl as previously noted, the microprocessor 140 in the controller is programmed to monitor the AC
line both before and during a PIC message transmission for the presen oe of intelligence or excessive noise levels and "standoff" for a random delay period if either condition is detected. As an additional means of avoiding potential collisions in a system employing multiple oontrollers, the microprocessor 140 in the controller 20 is further programmed to automatically execute a random delay of between 0 - 400 milliseconds following receipt of a RELAY
AL~RM message before transmitting the appropriate PLC controller message to the slave m~dules.
As in the relay m~dule, the controller is also provided with a portable battery backup power source 148 so that the controller can continue to function in the event of a loss of primary A~ power. In addition, the controller 20 includes an internal audio indicator, piezoelect~ic transducer 152, driven by a 3 KHz oscillator circuit 154 that is in turn enabled by a control signal from the B6 output port of the microprocessor 140 supplied to the oscillator circuit 154 via switching transistors 156. The microprocessor 140 is programred to activate its internal alarm 152 immediately upon receipt of a RELAY
ALARM PLC signal or an audio intrusion signal when the controller is in the INSTANT-ARM mDde, and after executing a 40-second delay when in the ARM-DELAY mode. To msure adequate sound pressure levels (e.g., at least 85 db) from the transducer 152, the preferred embodiment .

-38- ~2~ 0 additionally employs a mechanical sounding plate located an appropriate distance from the piez oe lectric transducer 152 50 that sound waves emanating therefrcm reflect off the sounding plate without sound diminishing phase cancellation.

SL~VE M3DULE (22 - 26) .
Referring now to Figure 13, a circuit diagram of a la~p n~dule 22 accord mg to the present invention is shown. The slave mKdules 22, 24, and 26, it will be recalled, are adapted to receive PLC command signals from ~he controller 20 and oontrol the activation of their respective loads in accordance therewith. It will be appreciated, however, that the appliance and ala~m mcdules 24 and 26, respectively, are substantially equivalent m function and configuration to the lamp mLdule 22, with ~he differences therebetween being related to the characteristics of the particular load being controlled. In a~dition, the alarm module includes a battery backup pcwer source so that the audio alanm will still sound in the event of an intrusion despite a loss of primary AC pcwer. m e lamp and appliance modules, on the cther hand, æ e not provided with a battery - backup.
The lamp module 22 in the preferred en~lrl~lent comprises in general a power suFply 158, a 4-bit microprocessor 160, a PLC input circuit 162 for interfac m g the microprocessor 160 to ~he AC line, and an output circuit 164 for controlling the activation of the load in response to a control signal from the microprocessor 160. An oscillator circuit 166 including a crystal oscillator 168 is oonnected to the OSC1 and OSC2 inputs of the microprocessor 160 to pr~vide the internal clock timung for the microprocessor. A first set of eight switches is connected to the R0-R7 data inputs of the microprocessor and set to the house code for the system. A second ~et of eight switches is also connected to the R0-R7 data inputs of the microprocessor and establish the unit code of the slave m~dule.
m e PLC input circuit includes a coupling transformer that is oonnected across the AC line. 'rhe output ~rcm the coupling transformer 174 is provided to a 121 KHz bandpass filter and amplifier circuit 176 which in turn supplies the ELC IN signal to the K2 input 10 port of the microprocessor 160. The output circuit 164 includes a TRIAC 178 that is connected in series with the load across the AC
power lines to control the energization of the load. The oonductive state of the TRIAC 178 is controlled by the microprocessor 160 which has its 03 and 04 output ports connected to the gate of the TRIAC.
m e microprocessor is programmed to decode and interpret the received PLC mes~agPs and generate an output signal at output ports 03 and 04 when appropriate to enable the TRIAC 178 to activate the load. In particular, the mlcroprocessor 160 will enable the TRIAC 178 to energize the load in response to the receipt of a CONIROLLER CoMM~ND
~ESSA OE (Figure 4A), provided the transmitted house code and unit ccde correspond to the preset house code and unit code of the lamp slave module 22. The mlcroprocessor 160 will sinilarly enable/disable the 1'RIAC 178 in response to the receipt of an -ALL LAMPS ON/OFF, respectively, controller cGmmand message (Figure 4B), provided the ~5 message includes the proper house code. In response to the receipt of a CONTR~LLER ALARM CCMMAND MESSA OE (Figure 4C) with the proper house cod~, the microprocessor 160 will immediately enable the TRIAC 178 to .

~z~

energize the load In response tD the receipt of a CCNIROLLER
COI~ OWN CoMM~ND MESSAOE IFigure 4C) with the proper house code, the microprocessor 160 will initiate a 40-second time delay before enabling the IRIAC 178. Lastly, upon receipt of a CCNTR~LLER DISAR~I
CoMMAND MESSAGE (Figure 4C) with the proper .house code, the microprocessor 160 will abort the 40-second time delay if in progress and disable the TRIAC 178 to de-activate the load.
In addition, it will ke not0d that the microprocessor 160 m the preferred embcdiment of the lamp slavP module 22 includes a SIATUS
SENSE line 180 that is connected to the lamp to sense the CN/OFF
condition o~ the manually operable switch associated with the lamp.
In particular, in order to ma1ntain local ~anual control of the lamp, the microprocessor 160 is progra~med to respond ~o the pulse produced on the SENSE LINE 180 when the lamp ~witch is closed and enable the TRIAC 178 so that the lamp will turn on. Moreover, the STAIVS SENSE
lme 180 is also used to permit remote control of the la~p with~ut requiring that the lamp be contin~ously energized. Specifically, it will be appreciated that the micrcprocessor 160 cannot possibly tu~n th~ lamp ON unless the lamp ~witch is closed. However, it is obviously undesirable to require that the lamp be contin~ously ON in order to provide the remote control capability. Acoordingly, the microprocessor 160 is programmed to detect the sequential ON-OFFVON
manual toggling of the lamp switch within a preselected brief time period and turn off the lamp after t~o seconds. In this m~nner, the lamp is placed in the OFF condition despite the closed position of the lamp switch, thus permitting rem~te control of the lamp via the lamp slave module 22. To thereafter manually turn on the lamp, it is necessary simply bo toggle the lamp switch OFF-ON. An LED 182 connected to the Oo output pDrt of the microprocessor 160 is energized by the microproces~or when ~he la~p has been placed in the rem~te control condition.
Also, it should be noted that the relay modules 18, controller(s) 20, and alarm slave mDdules 2~ in the present system are each provided with battery backup to supply auxiliary pcw~r to the devices in the event of a loss of primary AC power. In such event, the switch to battery power occurs auto~atically and the microprocessors in each unit are programmed to gen~rate accurate timlng signals from the internal quartz crystal and ceramic resonator oscillator circuits mcluded m each unit to ~ermit the units to asynchronously oommunicate ovex the power lines when primary AC pcwer is absent. In this m~nner, the present security system cannot be deEeated by interrupting ~ power to the protected premises.
It will be appreciated from the foregoing that, according to one aspect of the present invention, an lmproved security control system can be provided that utilizes wireless audio communication and power line com~unication to facilitate system installation.
Moreover, it will be appr~ciated that, according to another aspect of the present invention, a security control system can be provided that also provides the ability to remotely control the operation of various loads, including lights and appliances.
Furthermore, it will be appreciated that, according to yet another aspect of the present invention, an improved security control system can be provided that cannot be readily defeated by an intruder and yet is easily disarmed following an authorized entry.

-42~

~aving described the preferred el~bo~iment of the present - invention, it will be appreciated that the invention is susceptible to modification, variation, and change, the scope of the invention being defined by the follawing claims

Claims (27)

Claims:

1. A security system for installation in and for detecting an intrusion into a premises and signalling the detection of the intrusion event, comprising:
one or more entry detectors, for operatively associating with a corresponding number of selected entryways to the premises to be protected, for sensing an entry through said respective entryways and producing a coded audio signal in response thereto:
at least one signal relay device, for electrically connecting to an AC power line in the protected premises and locating within the audio range of a said entry detector, said signal relay device comprising audio receiver means for receiving said coded audio signal and separating said coded audio signal from extraneous noise in the received signal, power line communication transmission means for impressing a coded relay signal onto said AC power line, and processor means for decoding said coded audio signal and enabling said transmission means in said relay device to transmit said coded relay signal in response to the detection of a valid coded audio signal;
a controller, for electrically connecting to the AC power line of the protected premises, said controller comprising power line communication receiver means for receiving said coded relay signal and separating said coded signal from extraneous signals on said AC power line, power line communication transmission means for impressing a coded controller signal onto said AC power line, and processor means for decoding said coded relay signal and enabling said transmission means in said controller to transmit said coded controller signal in response to the detection of a valid coded relay signal;
and at least one slave device, for electrically connecting between said AC power line and an alarm device to control the activation of said alarm device, said slave device comprising power line transmission receiver means for receiving said coded controller signal and separating said coded controller signal from extraneous signals on said AC power line, output means for activating said alarm device, and processor means for decoding said coded controller signal and enabling said output means to activate said alarm device in response to the detection of a valid coded controller signal.

2. The security system according to Claim 1, wherein said controller is selectively operable in either a first mode wherein a first coded controller signal is impressed onto said AC power line in response to the receipt and detection of a valid coded relay signal, or a second mode wherein a second coded controller signal is impressed onto said AC power line in response to the receipt and detection of a valid coded relay signal.

3. The security system according to Claim 2, wherein said processor means in said slave device is adapted to immediately enable said output means to activate said alarm device in response to the receipt and detection of said first coded controller signal, and is further adapted to enable said output means to activate said alarm device after a predetermined time delay following the receipt and detection of said second coded controller signal.

4. The security system according to Claim 1, wherein said processor means in said controller is adapted to determine if other coded signals are being transmitted over said AC power line before enabling said transmission means in said controller to transmit said coded controller signal.

5. The security system according to Claim 4, wherein said processor means in said controller is further adapted to wait a random period of time following a determination that other coded signals are present on said AC power line before again attempting transmission of said coded controller signal.

6. The security system according to Claim 4, wherein said processor means in said controller is further adapted to determine if noise levels in excess of a predetermined amount are present on said AC power line before enabling said transmission means in said controller to transmit said coded controller signal.

7. The security system according to Claim 6, wherein said processor means in said controller is further adapted to wait a random period of time before again attempting transmission of said coded controller signal following a determination of the presence on said AC power line of either coded signals or noise levels in excess of said predetermined amount.

8. The security system according to Claim 1, wherein said relay coded signal and said coded controller signal comprise predetermined carrier frequency signals that are digitally pulse code modulated relative to the zero-crossing points in the AC power line waveform such that one complete cycle of the AC power line waveform is used to transmit each bit of information in said coded signals.

9. The security system according to Claim 8, wherein said pulse code modulated carrier frequency signal is representative of a digital "1" when a carrier frequency pulse is generated during one half cycle of the AC power line waveform and a digital "0" when a carrier frequency pulse is generated during the other half cycle of the AC
power line waveform.

10. The security system according to Claim 9, wherein said processor means in said controller is further adapted to determine if other pulse code modulated carrier frequency signals are being transmitted over said AC power line during the transmission of a controller coded signal by looking for the presence of said carrier frequency on said AC power line during the unused half cycle of the AC
power line waveform.

11. The security system according to Claim 1, wherein said coded audio digital has at least one predetermined frequency associated therewith, and said audio receiver means in said signal relay device includes a constant false alarm rate receiver comprising a broadband bandpass filter circuit, a limiter circuit connected to the output of said broadband bandpass filter circuit, and a narrow bandpass filter circuit connected to the output of said limiter circuit and having a center frequency approximately equal to said predetermined frequency.

12. The security system according to Claim 11, wherein said coded audio signal comprises alternating predetermined first and second frequency tones having predetermined spacing between successive alternating tones.

13. The security system according to Claim 12, wherein said constant false alarm rate receiver includes first and second narrow bandpass filter circuits connected to the output of said limiter circuit and having center frequencies approximately equal to the frequencies of said first and second predetermined frequency tones, respectively.

14. The security system according to Claim 12, wherein said audio receiver means includes decoding means for decoding said coded audio signal, said decoding means comprising logic circuit means for detecting in corresponding alternating sequence the presence of said first predetermined frequency tone and the simultaneous absence of said second predetermined frequency tone followed by the presence of said second predetermined frequency tone and the simultaneous absence of said first predetermined frequency tone.

15. The security system according to Claim 12, 13, or 14, wherein said first and second predetermined frequency tones have frequencies of approximately 6 KHz, and 7.3 KHz, respectively.

16. A security system for installation in and for detecting an intrusion into a premises and signaling the detection of the intrusion event, comprising:
intrusion detection means for detecting an intrusion into the premises to be protected and producing a coded signal in response thereto;
controller means for receiving said coded signal from said intrusion detection means and for producing alarm signals in response thereto, said controller means being selectively operable in either a first mode wherein a first alarm signal is produced in response to the receipt of a coded signal from said intrusion detection means, or a second mode wherein a second alarm signal is produced in response to the receipt of a coded signal from said intrusion detection means; and slave means, to be located remotely from said controller means and to be connected to an alarm device for controlling the activation of said alarm device, said slave means being responsive to receipt of said first alarm signal from said controller means to immediately activate said alarm device and being responsive to receipt of said second alarm signal from said controller means for implementing a predetermined time delay before activating said alarm device.

17. The security system according to Claim 16, wherein said controller means is further adapted to produce a third signal, and said slave means is responsive to the receipt of said third signal from said controller means for aborting the implementation of said predetermined time delay and preventing activation of said alarm device.

18. The security system according to Claim 17, wherein said controller means includes input means for permitting an operator to input information into said controller means, and said controller means is further adopted to produce said third signal solely in response to the entry of a secret code established by the operator into said controller means via said input means.

19. The security system according to Claim 18, wherein said controller means is selectively operable in either of said first or second modes in response to predetermined entries made via said input means.

20. The security system according to Claim 16, wherein said controller means is adapted for electrical connection to an AC power line of the protected premises, and further includes power line communication transmission means for impressing said alarm signals onto said AC power line.

21. The security system according to Claim 20, wherein said slave means is electrically connected between said AC power line and said alarm device, and further includes power line communication receiver means for receiving said alarm signals transmitted over said AC
power line from said controller means.

22. A security system, comprising: detection means for detecting an intrusion into a premises being protected, and for producing an intrusion signal in response to detection of said intrusion; a signal relay device electrically connected to an AC power line in the protected premises for impressing a coded relay signal onto said AC power line in response to receipt of said intrusion signal; a controller electrically connected to said AC power line for impressing a coded controller signal onto said AC power line in response to the receipt of said coded relay signal; a slave device electrically connected between said AC power line and an alarm device for activating said alarm device in response to the receipt of said coded controller signal; said coded relay signal and said coded controller signal comprising predetermined carrier frequency signals that are digitally pulse code modulated with one complete cycle of the AC
power line waveform being used to transmit each bit of information in said coded signals with a digital "1"
corresponding to a carrier frequency pulse being generated during one half cycle of the AC power line waveform and a digital "0" corresponding to a carrier frequency pulse being generated during to the other half cycle of the AC
Power line waveform; and processor means in said signal relay device and processor means in said controller for determining if other coded signals are being transmitted over said AC power line both prior to and during the transmission of said coded relay and coded controller signals, respectively, and for delaying or aborting said respective transmissions in the event other intelligence on said AC power line is detected.

23. The security system according to Claim 22, wherein the processor means in said signal relay device and said controller are adapted to look for the presence of said predetermined carrier frequency on said AC power line both prior to transmission of said respective coded signals and during the unused half cycle of the AC power line waveform during the transmission of said respective coded signals.

24. The security system according to Claim 22 or 23, wherein the processor means in said signal relay device and said controller are further adapted to wait a random period of time following a determination that other intelligence is present on said AC power line before again attempting transmission of said respective coded signals.

25. The security system according to Claim 22, wherein the processor means in said signal relay device and in said controller are adapted to determine if noise levels in excess of a predetermined amount are present on said AC power line both prior to and during transmission of said respective coded signals and to delay or abort aid respective transmissions in the event excessive noise levels on the AC power line are detected.

26. The security system according to Claim 25, wherein the processor means in said signal relay device and in said controller are further adapted to wait said random period of time following the detection of excessive noise levels on said AC Power line before again attempting transmission of said respective coded signals.

27. The security system according to Claim 25 or 26, wherein the processor means in said signal relay device and said controller are adapted to look for the presence of excessive noise levels on the AC power line both prior to transmission of said respective coded signals and during the unused half cycle of the AC power line waveform during the transmission of said respective coded signals.