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BR9910802A - Processo e dispositivo para o processamento de dados - Google Patents

Processo e dispositivo para o processamento de dados

Info

Publication number
BR9910802A
BR9910802A BR9910802-0A BR9910802A BR9910802A BR 9910802 A BR9910802 A BR 9910802A BR 9910802 A BR9910802 A BR 9910802A BR 9910802 A BR9910802 A BR 9910802A
Authority
BR
Brazil
Prior art keywords
encoding
decoding
data processing
steps
data
Prior art date
Application number
BR9910802-0A
Other languages
English (en)
Inventor
Holger Sedlak
Peter Soehne
Michael Smola
Stefan Wallstab
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19828936A external-priority patent/DE19828936A1/de
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9910802A publication Critical patent/BR9910802A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7223—Randomisation as countermeasure against side channel attacks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7266—Hardware adaptation, e.g. dual rail logic; calculate add and double simultaneously
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/007—Encryption, En-/decode, En-/decipher, En-/decypher, Scramble, (De-)compress
    • G06F2211/008—Public Key, Asymmetric Key, Asymmetric Encryption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2107—File encryption

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

Patente de Invenção: <B>"PROCESSO E DISPOSITIVO PARA O PROCESSAMENTO DE DADOS"<D>. é previsto um processo para codificar e/ou decodificar dados, no qual os dados para a codificação ou decodificação são previstos em uma etapa de codificação ou de decodificação, que é escolhida de várias etapas de codificação ou de decodificação alternativas equivalentes, e/ou consiste de várias etapas parciais a serem processadas em seq³ência, onde a etapa de codificação ou de decodificação escolhida é escolhida aleatoriamente e/ou as etapas de codificação ou de decodificação são alteradas aleatoriamente.
BR9910802-0A 1998-05-29 1999-05-14 Processo e dispositivo para o processamento de dados BR9910802A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19824163 1998-05-29
DE19828936A DE19828936A1 (de) 1998-05-29 1998-06-29 Verfahren und Vorrichtung zum Verarbeiten von Daten
PCT/DE1999/001461 WO1999063419A1 (de) 1998-05-29 1999-05-14 Verfahren und vorrichtung zum verarbeiten von daten

Publications (1)

Publication Number Publication Date
BR9910802A true BR9910802A (pt) 2001-02-13

Family

ID=26046521

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9910802-0A BR9910802A (pt) 1998-05-29 1999-05-14 Processo e dispositivo para o processamento de dados

Country Status (6)

Country Link
EP (1) EP1080400B1 (pt)
JP (1) JP2002517787A (pt)
CN (1) CN100530025C (pt)
AT (1) ATE227445T1 (pt)
BR (1) BR9910802A (pt)
WO (1) WO1999063419A1 (pt)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587044B2 (en) 1998-01-02 2009-09-08 Cryptography Research, Inc. Differential power analysis method and apparatus
AU2557399A (en) 1998-01-02 1999-07-26 Cryptography Research, Inc. Leak-resistant cryptographic method and apparatus
AU6381699A (en) 1998-06-03 2000-01-10 Cryptography Research, Inc. Improved des and other cryptographic processes with leak minimization for smartcards and other cryptosystems
JP4216475B2 (ja) 1998-07-02 2009-01-28 クリプターグラフィー リサーチ インコーポレイテッド 漏洩抵抗力を有する暗号索引付き鍵の更新方法及びデバイス
JP2000305453A (ja) * 1999-04-21 2000-11-02 Nec Corp 暗号化装置，復号装置，および暗号化・復号装置
FR2804524B1 (fr) * 2000-01-31 2002-04-19 Oberthur Card Systems Sas Procede d'execution d'un protocole cryptographique entre deux entites electroniques
US8296577B2 (en) * 2004-06-08 2012-10-23 Hrl Laboratories, Llc Cryptographic bus architecture for the prevention of differential power analysis

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2638869B1 (fr) * 1988-11-10 1990-12-21 Sgs Thomson Microelectronics Dispositif de securite contre la detection non autorisee de donnees protegees
US5404402A (en) * 1993-12-21 1995-04-04 Gi Corporation Clock frequency modulation for secure microprocessors
US5533123A (en) * 1994-06-28 1996-07-02 National Semiconductor Corporation Programmable distributed personal security
DE19523466C1 (de) * 1995-06-28 1997-04-03 Informatikzentrum Der Sparkass Verfahren zur gegenseitigen Authentifikation von elektronischen Partnern mit einem Rechnersystem
FR2745099B1 (fr) * 1996-02-19 1998-03-27 Sgs Thomson Microelectronics Procede de sequencement d'un circuit integre

Also Published As

Publication number Publication date
CN1303493A (zh) 2001-07-11
WO1999063419A1 (de) 1999-12-09
ATE227445T1 (de) 2002-11-15
CN100530025C (zh) 2009-08-19
JP2002517787A (ja) 2002-06-18
EP1080400B1 (de) 2002-11-06
EP1080400A1 (de) 2001-03-07

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 6A, 7A E 8A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1913 DE 04/09/2007.