BE843362A - Circuit d'inscription et de lecture autoverificateur - Google Patents

Circuit d'inscription et de lecture autoverificateur

Info

Publication number: BE843362A
Authority: BE; Belgium
Prior art keywords: verifier; enrollment; self; reading circuit; reading
Prior art date: 1975-06-27

Application number

BE168273A

Other languages

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1975-06-27

Filing date

1976-06-24

Publication date

1976-10-18

1976-06-24 Application filed filed Critical

1976-10-18 Publication of BE843362A publication Critical patent/BE843362A/fr

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

Engineering & Computer Science (AREA)
General Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Computer Hardware Design (AREA)
Quality & Reliability (AREA)
Physics & Mathematics (AREA)
General Physics & Mathematics (AREA)
Detection And Correction Of Errors (AREA)
Techniques For Improving Reliability Of Storages (AREA)
Time-Division Multiplex Systems (AREA)
Test And Diagnosis Of Digital Computers (AREA)
Electronic Switches (AREA)

BE168273A 1975-06-27 1976-06-24 Circuit d'inscription et de lecture autoverificateur BE843362A (fr)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US05/591,140 US3992696A (en)	1975-06-27	1975-06-27	Self-checking read and write circuit

Publications (1)

Publication Number	Publication Date
BE843362A true BE843362A (fr)	1976-10-18

Family

ID=24365219

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
BE168273A BE843362A (fr)	1975-06-27	1976-06-24	Circuit d'inscription et de lecture autoverificateur

Country Status (10)

Country	Link
US (1)	US3992696A (fr)
JP (1)	JPS588005B2 (fr)
BE (1)	BE843362A (fr)
CA (1)	CA1056063A (fr)
DE (1)	DE2628847A1 (fr)
ES (1)	ES449276A1 (fr)
FR (1)	FR2317833A1 (fr)
GB (1)	GB1542115A (fr)
IT (1)	IT1081222B (fr)
SE (1)	SE423015B (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4155116A (en) *	1978-01-04	1979-05-15	The Bendix Corporation	Digital control system including built in test equipment
JPS54115026A (en) *	1978-02-28	1979-09-07	Sharp Corp	Signal read-in system to microprocessor
US4271521A (en) *	1979-07-09	1981-06-02	The Anaconda Company	Address parity check system
US4295219A (en) *	1980-03-31	1981-10-13	Bell Telephone Laboratories, Incorporated	Memory write error detection circuit
US4346474A (en) *	1980-07-03	1982-08-24	International Business Machines Corporation	Even-odd parity checking for synchronous data transmission
WO1983000242A1 (fr) *	1981-06-26	1983-01-20	Ncr Co	Dispositif de controle d'erreur de memoire a haute vitesse
US4528666A (en) *	1983-01-03	1985-07-09	Texas Instruments Incorporated	Memory system with built in parity
US4580265A (en) *	1983-06-30	1986-04-01	International Business Machines Corporation	Failure detection method and apparatus
US5367526A (en) *	1993-06-22	1994-11-22	Kong Edmund Y	Memory module, parity bit emulator, and associated method for parity bit emulation
JPH08304896A (ja) *	1995-05-02	1996-11-22	Asahi Optical Co Ltd	カメラ
US8438582B2 (en) *	2008-06-30	2013-05-07	Alcatel Lucent	Soft denial of application actions over the network communications

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3428945A (en) *	1965-05-20	1969-02-18	Bell Telephone Labor Inc	Error detection circuits
US3465132A (en) *	1965-08-23	1969-09-02	Ibm	Circuits for handling intentionally mutated information with verification of the intentional mutation
US3401379A (en) *	1966-01-10	1968-09-10	Bell Telephone Labor Inc	False code generator
US3541507A (en) *	1967-12-06	1970-11-17	Ibm	Error checked selection circuit

1975
- 1975-06-27 US US05/591,140 patent/US3992696A/en not_active Expired - Lifetime
1976
- 1976-06-08 CA CA254,325A patent/CA1056063A/fr not_active Expired
- 1976-06-21 SE SE7607092A patent/SE423015B/xx unknown
- 1976-06-22 GB GB7625990A patent/GB1542115A/en not_active Expired
- 1976-06-24 BE BE168273A patent/BE843362A/fr unknown
- 1976-06-25 FR FR7619490A patent/FR2317833A1/fr active Granted
- 1976-06-25 IT IT24759/76A patent/IT1081222B/it active
- 1976-06-26 ES ES449276A patent/ES449276A1/es not_active Expired
- 1976-06-26 DE DE19762628847 patent/DE2628847A1/de not_active Withdrawn
- 1976-06-28 JP JP51075666A patent/JPS588005B2/ja not_active Expired

Also Published As

Publication number	Publication date
SE7607092L (sv)	1976-12-28
SE423015B (sv)	1982-04-05
DE2628847A1 (de)	1977-01-13
CA1056063A (fr)	1979-06-05
GB1542115A (en)	1979-03-14
JPS588005B2 (ja)	1983-02-14
ES449276A1 (es)	1977-08-01
JPS524748A (en)	1977-01-14
IT1081222B (it)	1985-05-16
FR2317833B1 (fr)	1981-06-12
US3992696A (en)	1976-11-16
FR2317833A1 (fr)	1977-02-04

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