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AU722964B2 - Semiconductor device and method for manufacture thereof - Google Patents

Semiconductor device and method for manufacture thereof Download PDF

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Publication number
AU722964B2
AU722964B2 AU23707/97A AU2370797A AU722964B2 AU 722964 B2 AU722964 B2 AU 722964B2 AU 23707/97 A AU23707/97 A AU 23707/97A AU 2370797 A AU2370797 A AU 2370797A AU 722964 B2 AU722964 B2 AU 722964B2
Authority
AU
Australia
Prior art keywords
mount
electrode
legs
semiconductor device
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU23707/97A
Other versions
AU2370797A (en
Inventor
Hisao Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Sanken Electric Co Ltd
Original Assignee
Mitsubishi Electric Corp
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP35474195A priority Critical patent/JP2992873B2/en
Priority to GB9626677A priority patent/GB2308736B/en
Priority to FR9615959A priority patent/FR2742925B1/en
Application filed by Mitsubishi Electric Corp, Sanken Electric Co Ltd filed Critical Mitsubishi Electric Corp
Priority to AU23707/97A priority patent/AU722964B2/en
Priority to DE19724909A priority patent/DE19724909A1/en
Publication of AU2370797A publication Critical patent/AU2370797A/en
Application granted granted Critical
Publication of AU722964B2 publication Critical patent/AU722964B2/en
Anticipated expiration legal-status Critical
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/066—Heatsink mounted on the surface of the printed circuit board [PCB]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10568—Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
    • H05K2201/1075—Shape details
    • H05K2201/10757—Bent leads
    • H05K2201/10772—Leads of a surface mounted component bent for providing a gap between the lead and the pad during soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1178—Means for venting or for letting gases escape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Description

P/00/011 Regulation 3.2
AUSTRALIA
PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT
ORIGINAL
TO BE COMPLETED BY APPLICANT MITSUBISHI ELECTRIC CORPORATION and SANKEN ELECTRIC CO. LTD.
Name of Applicant: Actual Inventor(s): Address for Service: Invention Title: Hisao Tomizawa CALLINAN LAWRIE, 278 High Street, Kew, 3101, Victoria, Australia "SEMICONDUCTOR DEVICE AND METHOD MANUFACTURE THEREOF"
FOR
The following statement is a full description of this invention, including the best method of performing it known to me:- -1- Semiconductor Device and Method For Manufacture Thereof BACKGROUND OF THE INVENTION a) Field of the Invention This invention relates to a semiconductor device, in particular of type having a mount which is certainly secured on a circuit board to support a semiconductor element on the mount.
b) Description of the prior art A known semiconductor device includes a circuit board on which a mount made of copper is secured to support a semiconductor element thereon. The mount is effective to outwardly radiate heat produced by the semiconductor element upon operation for increase of electric current capacity.
However, the mount tends to be attached on the circuit board in the slant condition because of irregular amount of brazing metal between a flat surface of the mount and the circuit board. In addition, it is very difficult to secure the mount on the circuit board in an exactly upright condition with uniform thickness of the brazing metal all over the flat surface of the mount. Moreover, it is also actually impossible to braze a plurality of mounts on the circuit Sboard with a constant thickness of brazing metal for a same level although the mounts are cor- Srectly secured on the circuit board in the upright condition.
e g.
@055 In case the mount is secured on the circuit board in the inclined condition, a semiconductor element cannot correctly be attached on the mount by die bonding, and ends of thin wires cannot be connected on electrodes of the semiconductor element, thereby resulting in failure of connection or disconnection of the thin wires. Also, uneven or insufficient thickness of the brazing metal causes incorrect electric properties or deterioration of the semiconductor device in an environment test such as severe thermal test or thermal fatigue test, and sometimes the slant attachment of the mount would give rise to some troubles in the manufacturing process of the semiconductor device.
An object of the present invention is to provide a semiconductor device capable of avoiding slant attachment of a mount on a circuit board.
Another object of the invention is to provide a semiconductor device which has a mount certainly secured on a circuit board correctly in the upright condition.
Summary of the Invention The semiconductor device according to the present invention includes a support, a mount secured on the support by brazing metal and a semiconductor element secured on the mount.
The mount is formed with at least an inclined surface formed at the periphery which faces the support and a plurality of legs formed inside the inclined surface to form at least a dent between the legs. The inclined surface is divergent away from the support, and the legs are in contact with the support. The brazing metal is disposed in a gap including the dent and a flaring area between the support and the inclined surface of the mount between the support and mount.
In an embodiment of the present invention, the mount is formed into substantially rectangular shape to form four inclined surfaces, and the legs forms a cross dent inwardly extending from each inclined surface. The legs are formed into columns or elongated protrusions separated from each other, extending from the mount. The support includes a circuit board on which at least an electrode and circuit conductor are formed thereon for electrical connection.
The method for manufacturing a semiconductor device according to the present invention comprises the steps of: providing a mount formed with a plurality of integrally formed legs and at least an inclined surface formed at the periphery; piling in turn on an electrode formed on a .9 support, an adhesive solder paste, the mount, an adhesive solder past and a semiconductor chip to form a subassembly; and heating the subassembly to re-fuse the solder pastes and then cooling same for full setting to simultaneously bond the mount and semiconductor chip on the support.
Gas produced in brazing metal is released during the heating process through at least a dent formed between the legs and the inclined surface out of the brazing metal, thus preventing trapping of bubbles therein.
The legs formed in the mount are effective to prevent slant attachment of the mount on the support with substantially uniform thickness of brazing metal between the support and mount. In addition, the mount is firmly bonded on the support by brazing metal filled in the dent between the legs and in the flaring area between the support and the inclined surface of the mount to prevent exfoliation or detachment of the mount from the support when the semiconductor device is used under severe variation of ambient temperature. As a result, the semiconductor device can keep good electric properties during its long duration and improve yield in manufacture. A plurality of legs separated from each other provide stable attachment of the mount against its inclined condition because gas produced in brazing metal is released through the dent out of the brazing metal, thus preventing trapping of bubbles therein and enhancement of braze strength.
The above-mentioned as well as other objects of the present invention will become apparent during the course of the following detailed description and appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial section view of an embodiment of the semiconductor device according to the present invention.
~Fig. 2 is a partial plan view of the semiconductor device.
a. .a S"Fig. 3 is a side view of a mount used in the semiconductor device shown in Fig. 1.
Fig. 4 is a bottom view of the mount.
Fig. 5 is a partial section view of a second embodiment of the semiconductor device according to the present invention.
Fig. 6 is a side view of the mount used in the second embodiment shown in Fig. Fig. 7 is a bottom view of the mount used in the second embodiment shown in Fig. e• DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figs. 1 to 4 indicate a first embodiment of the semiconductor device according to the present invention. As shown in Fig. 1, the semiconductor device comprises a circuit board 1 to form a support of ceramics such as alumina (A1 2 0 3 a mount 2 secured on the circuit board 1, and a diode chip 3 of silicon (Si) as a semiconductor element. Not shown but, the mount 2 comprises a base of copper and a metallic coating formed on the base. The metallic coating consists of a first nickel (Ni) plating layer formed on the base and a second silver (Ag) plating layer formed on the first layer.
As shown in Figs. 1 and 2, an electrode (pad) 4 and a circuit conductor 5 connected with the electrode 4 are mounted on a main surface la of the circuit board 1. The electrode 4 has a substantially rectangular shape similar to the shape of the mount 2 to preferably bond the mount 2 on the electrode 4.
As illustrated in Figs. 3 and 4, the mount 2 comprises a plate-like main body 6 and four column-like legs 7. An inclined surface 8 is formed at the looped periphery of a first main surface 6a of the main body 6 which faces the circuit board 1. The inclined surface 8 is divergent away from the circuit board 1 to form a flaring area 13 between the circuit board 1 and the inclined surface 8 of the main body 6. In this embodiment, the inclined surface 8 is formed into arch shape with a certain radius of curvature. Four legs 7 are formed in the vicinity of four corners 6b and slightly inside the inclined surface 8 to form a cross dent 14 between the legs 7 all of which have a substantially same extension length from the first main surface 6a. Two of the 2: corners 6b of the mount 2 shown by dotted line in Fig. 2 are connected with the circuit conductor 9 9. 5. In this embodiment, a surface area of the electrode 4 is slightly larger than a plane area of the mount 2. No inclined surface is provided at the periphery of the second main surface 6c.
9 The first main surface 6a of the mount 2 is secured to the electrode 4 of the circuit board 1 by solder 9 as a brazing metal which is filled in the dent 14 and the flaring area 13. Since each bottom surface 7a of the legs 7 is brought into contact with the electrode 4, the mount 2 can be .9 fixed on the electrode 4 so that the first main surface 6a of the main body 6 is kept substantially 99 •parallel to the surface of the electrode 4 due to the same extension length of the four legs 7. The solder 9 is fully filled in a gap including the flaring area 13 and dent 14 formed between the mount 2 and electrode 4 to bond the first main surface 6a of the main body 6, side walls of the legs 7, inclined surfaces 8 and the surface of the electrode 4. The solder 9 is spread all over the surface of the electrode 4 and a part of the circuit conductor 5. As the surface area of the electrode 4 is slightly larger than a plane area of the main body 6, the outer surface of the solder 9 is formed into inverted funnel shape divergent toward the electrode 4.
A diode chip 3 is attached on a second main surface 6c of the main body 6 by solder In this embodiment, known reflow soldering method is utilized to apply solders 9 and 10 respectively between the mount 2 and electrode 4 and between the mount 2 and diode chip 3. Specifically, a subassembly is made by piling in turn on the electrode 4, adhesive solder paste, the mount 2, adhesive solder past and diode chip 3. The subassembly is transported through a heater or furnace to re-fuse the solder pastes and then the solder pastes are cooled for full setting to simultaneously bond the mount 2 and diode chip 3 on the electrode 4. Another bonding method may be applied for such subassembling.
This embodiment of the present invention can produce the following effects: 1 The legs 7 formed in the vicinity of four corners 6b of the mount 2 are in contact with the electrode 4 to set the mount 2 in position to thereby prevent slant attachment of the mount 2 on the electrode 4. In addition, the main body 6 is kept away from and substantially parallel to the electrode 4 by the legs 7 with substantially uniform thickness of solder 9 between the electrode 4 and mount 2.
2 The mount 2 can firmly be bonded on the electrode 4 by solder 9 filled in the dent i 14 between the legs 7 andinthe flaring area 13 between the electrode 4 and the inclined surface 8 of the mount 2.
3 The outer surface of the solder 9 is formed into inverted funnel shape divergent toward the electrode 4 whose surface area is slightly larger than a plane area of the main body 6 to provide a sufficient boriding area by the solder 9.
4 An additional bonding area is further provided by a part of the circuit conductor over which solder 9 is spread.
A plurality of the legs 7 separated from each other provide stable attachment of the mount 2 to avoid its inclined condition of the mount 2.
6 Gas produced in solder 9 is released through the dent 14 out of solder 9 to prevent trapping of bubbles formed by evaporation of flux contained in solder paste for enhancement of bonding strength.
7 Exfoliation or detachment of the mount 2 from the electrode 4 can be avoided when the semiconductor device is used under severe variation of ambient temperature.
8 The resultant semiconductor device can effectively keep good electric properties during its long duration and improve yield in manufacture.
Figs. 5 to 7 show a second embodiment of the present invention with the mount 11 which has legs 12 formed into elongated protrusions. Same reference symbols are applied to similar parts shown in Figs. 5 to 7 to those shown in Figs. 1 to 4. Each of these legs 12 has V-shaped section and two rows of the legs 12 are separated from each other inside two opposite side walls.
It is apparent that the second embodiment provides similar effects to those of the preceding embodiment.
The foregoing embodiments of the invention may varied in view of actual demands. For instance, the legs 7 may be formed into a rectangular section although rounded section of the legs 7 is better to promote discharge of bubbles in solder 9. Also, the legs 17 may be of rectangular S. or U-shaped section. The main body 6 may be formed into a disk. Additional circuit conductors may be provided on the circuit board 1 for connection with the electrode 4 which may be formed in selected one of various shapes. The circuit conductor 5 may be deleted as required.
o° o *o9•9 9* 9
AU23707/97A 1995-12-26 1997-05-30 Semiconductor device and method for manufacture thereof Expired AU722964B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP35474195A JP2992873B2 (en) 1995-12-26 1995-12-26 Semiconductor device
GB9626677A GB2308736B (en) 1995-12-26 1996-12-23 Semiconductor device and method for manufacture thereof
FR9615959A FR2742925B1 (en) 1995-12-26 1996-12-24 SEMICONDUCTOR DEVICE OF THE TYPE HAVING A FRAME FOR DISCHARGING THE HEAT, AND MANUFACTURING METHOD THEREOF
AU23707/97A AU722964B2 (en) 1997-05-30 1997-05-30 Semiconductor device and method for manufacture thereof
DE19724909A DE19724909A1 (en) 1995-12-26 1997-06-12 Semiconductor device with mount for its securing to PCB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU23707/97A AU722964B2 (en) 1997-05-30 1997-05-30 Semiconductor device and method for manufacture thereof

Publications (2)

Publication Number Publication Date
AU2370797A AU2370797A (en) 1998-12-03
AU722964B2 true AU722964B2 (en) 2000-08-17

Family

ID=3712788

Family Applications (1)

Application Number Title Priority Date Filing Date
AU23707/97A Expired AU722964B2 (en) 1995-12-26 1997-05-30 Semiconductor device and method for manufacture thereof

Country Status (1)

Country Link
AU (1) AU722964B2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740617A (en) * 1968-11-20 1973-06-19 Matsushita Electronics Corp Semiconductor structure and method of manufacturing same
US4862247A (en) * 1987-11-24 1989-08-29 Texas Instruments Incorporated Contact joint for semiconductor chip carriers
US5410451A (en) * 1993-12-20 1995-04-25 Lsi Logic Corporation Location and standoff pins for chip on tape

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740617A (en) * 1968-11-20 1973-06-19 Matsushita Electronics Corp Semiconductor structure and method of manufacturing same
US4862247A (en) * 1987-11-24 1989-08-29 Texas Instruments Incorporated Contact joint for semiconductor chip carriers
US5410451A (en) * 1993-12-20 1995-04-25 Lsi Logic Corporation Location and standoff pins for chip on tape

Also Published As

Publication number Publication date
AU2370797A (en) 1998-12-03

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