AU711123C - Apparatus for sampling and displaying an auxiliary image with a main image - Google Patents

Description

APPARATUS FOR SAMPLING AND DISPLAYING AN AUXILIARY IMAGE WITH A

MAIN IMAGE

The present invention relates to a picture-in-picture system using quincunx sampling to improve horizontal resolution.

Present image display systems include the ability to display a small auxiliary image in addition to a larger nain image. This smaller image may be displayed within the boundaries ot the larger main picture, in which case, such a system is termed a picture-in-picture (PIP) system, or the smaller image may be located outside (e.g. to the left or right side of the main image, in which case the system is termed a picture- outside-picture (POP) system. The main and auxiliary images may be derived from the same image source, such as a freeze frame PIP image of the main image, or may be derived from an independent source, such as a system in which one tuner tunes to one video signal which is displayed as the main image, and a second tuner tunes a second video signal, independent of the first tuner, which is displayed as the PIP image.

A PIP or POP system operates by storing compressed image data representing the auxiliary image as it occurs in the auxiliary video signal, and then substituting this compressed image data for the main image signal at the portion of the main image which is designated to display the auxiliary image. The system must supply an amount of memory sufficient to store the auxiliary image data from the time it occurs in 1-3 video signal to the time it is displayed in the rram image. Known systems provide sufficient memory to hold either a frame or a field of auxiliary video data. Because memory is relatively expensive, it is desirable to minimize the amount of memory required. To decrease the amount of memory required, known PIP and FOP systems subsample the auxiliary video signal, and store only a single field of subsampled auxiliary video data. A display method, complementary to the subsampling method, is used to generate the display image signal for the inset PIP or FOP image.

Known subsampling techniques, however, consist of

straightforward 'take one sample, discard N samples' repeated for each line in the auxiliary video signal. This undesirably decreases the horizontal resolution of the PIP or POP image. This, in turn, decreases the perceived quality of the displayed PIP or POP image. A subsampling method which can increase the horizontal resolution of a PIP or POP image, without increasing the amount of memory necessary to store the PIP or POP image data for later display with the main image is desirable.

In accordance with principles of the present invention, apparatus for displaying a combined image of an auxiliary image and a main image includes a source of a main image signal and a source of samples representing an auxiliary image signal. A quincunx subsampler is coupled to the auxiliary image sample source. A signal combiner is coupled to the main image signal source and the quincunx subsampler. The sample combiner combines the main image signal and a signal representing the quincunx subsampled samples to generate a signal representing a combined image of the main and auxiliary images. In the drawing:

Fig. 1 illustrates a display image illustrating a main and a picture-in-picture (PIP) image and incorporating the present invention;

Fig. 2 is a diagram, partially in block form, partially in logic form, of a portion of a PIP system incorporating the present invention;

Fig. 3 is a more detailed illustration of the PIP display image illustrating quincunx sampling;

Fig. 4 is a waveform diagram of the main and PIP video signals, and of PIP memory access addresses;

Figs. 5 and 6 are more detailed illustrations of portions of a PIP display image illustrating a problem using quincunx sampling for a PIP image, and the solution;

Fig. 7 is a diagram, partially in block form and partially in logic form, of an encoder for generating PIP data for storage in a field memory; and

Fig. 8 is a diagram, partially in block form and partially in logic form, of a decoder for generating PIP data for insertion into a main image.

The illustrated embodiment is described in terms of a picture-in-picture (PIP) system, producing an image as illustrated in Fig. 1. However the principles of the present inven- tion are equally applicable to other multiple picture systems, such as a picture-outside-picture (POP) in which a small image is plsced outside of (i.e. to the left or the right; of a main image. Fig. 1 illustrates a PIP display image inducing a irain and an auxiliary image and incorporating the present invention. In Fig. 1, a main image 2 is shown as it night be displayed on a display device, such as a television receiver or monitor. The mam image 2 may be generated by known signal processing circuitry, including a tuner responsive to a television signal received from antenna or a cable. Also shown in Fig. 1 is a second image 4 which is inset in the bottom left hand corner of the main image 2. The auxiliary image 2 in the illustrated embodiment is termed a picture-in-picture (PIP) image. The PIP image is also generated by known signal processing circuitry, possibly including a second tuner responsive to a second television signal received from an antenna or a cable. Alternatively, the second tuner may be embodied in a separate video cassette recorder (VCR) . A 3ignal representing the PIP image 4 is combined with the signal representing the main image 2 in a known manner, and the combined signal supplied to a αisplay device, which displays the image illustrated in Fig. 1.

Fig. 2 is a diagram, partially in block form, partially in logic form, of a portion of a PIP system incorporating the present invention. In Fig. 2, a source 102 of a main video image representative signal includes an output terminal coupled to respective input terminals of a synchronization component processor 103 and a video component processor 104. An output terminal of the synchronization component processor 103 is coupled to a main timing signal generator 106. An output terminal of the video component processor 104 is coupled to a first data input terminal of multiplexer 103. An output terminal of the multiplexer 108 produced the combined video signal, and is coupled to a display device (not shown) in a known manner. Respective output terminals of the main timing signal generator 106 are coupled to a clock input terminal of the viαeo component processor 104 and to a control input terminal of the multiplexer 108.

A source 110 of a PIP video image signal is coupled to an input terminal of a PIP ADC 112. An output terminal of the PIP ADC 112 is coupled to respective input terminals of a PIP video processor 113 and a PIP timing generator 114. An output terminal of the PIP video processor 113 is coupled to a data input terminal of a quincunx subsampler 116. An output terminal of the subsampler 116 is coupled to a data input terminal of a field memory 120. A data output terminal of the field memory 120 is coupled to a data input terminal of an inset image display signal generator 124. An output terminal of the display generator 124 is coupled to a second data input terminal of the multiplexer 108. Respective output terminals of the PIP timing signal generator 114 are coupled to a corresponding input terminals of the subsampler 116 and a write acdress generator 118. The write acdress generator 118 nas an output terminal coupleα to respective write address input terminals of the subsampler 116 and the field memory 123. Respective output terminals of the maim timing signal generator 106 are coupled to correspondin g input terminals of a read acdress generator 122 and the display generator 124. The read address generator 122 has an output terminal coupled to respective read address input terminals of the subsampler 116 and the field memory 120. Referring to both Fig. 1 and Fig. 2, the main video signal from the main video signal source 102 includes a video component and a synchronization component. The synchronization component processor 103 extracts and processes the synchronization component signal. The synchronization signal is supplied to timing generator 106 which generates a timing signal in synchronism with the clock signal at 4·f_sc (the color subcarrier frequency). This timing signal is coupled to the main video processor 104. The video processor 104 processes the main video signal in a known manner. For example, in a preferred embodiment, the main video processor 104 contains a luminance/chrominance signal separator, such as a comb filter, producing separate luminance and chrominance signals. The main video processor 104 may also include a demodulator for the chrominance signal and produce separate I and Q or U and V signals, and may further include a color signal matrix, and generate R, G and 3 color component signals. Also in the preferred embodiment, the main video processor 104 includes an analog-to-digital converter, and may perform part of its processing, including comb filtering, in digital circuitry.

Alternatively, it is also possible to perform no video processing at all. In this case the main video signal is passed, unchanged, from the main video signal source 102 to the multiplexer 108.

The main timing signal generator 106 also produces a signal indicating when the display device is scanning the portion of the display image in which the PIP inset image is to be located. This signal is supplied to the control input terminal of the multiplexer 108. When the main image is to be displayed, the multiplexer 108 is conditioned to couple the main video processor 103 to its output terminal, and when the PIP image is to be displayed, the multiplexer 108 is condi- tioned to couple the display generator 124 to its output terminal.

Simultaneously, the PIP video signal is processed by the PIP ADC 112 to produce samples representing the PIP video signal at a frequency of 4·f_sc. These samples are processed by the PIP timing signal generator 114 and the PIP video signal processor 113. Specifically, the PIP timing signal generator 114 identifies, extracts and processes the PIP synchronization component. The PIP video processor 113 comprises digital circuitry processing the PIP video signal samples from the PIP ADC 112. Similarly to the main video processor 104 described above, in a preferred embodiment, the video processing includes circuitry, such as a comb filter, to separate the luminance and chrominance components fron the PIP video signal. The PIP video processor 113 may further induce a demodulator to separate the Z and Q or U and V chrominance components. Alterna- tively, the PIP video processor 113 nay perform no further processing of the PIP video signal samples, in wnich case the output of the PIP ADC 112 is coupled directly to the input terminal of the quincunx subsampler 116.

This PIP image sample sequence from the PIP video proces- sor 113 is subsampled by the quincunx subsampler 116, m response to a timing signal from the PIP timing signal generator 114, and the field memory read and write addresses, in a manner to be described in more detail below. In general, each field of the PIF sample sequence is independently subsampled in the following manner. In the vertical direction, three vertically aligned horizontal PIP samples are filtered to generate a single PIP subsampled sample. In a preferred embodiment, the three vertically aligned samples are averaged. In the horizontal direction the filtered sequence is subsampled at a 6:1 ratio, i.e. keep one sample, discard five samples in a manner to be described in more detail below. The timing of the horizontal subsampling is controlled in a manner described in more detail below to provide quincunx sampling. It is possible to quincunx subsample only a component of the PIP image sample stream. For example, in the preferred embodiment, the luminance component sample stream is quincunx subsampled. One field of the subsampled PIP samples from the subsampler 116 are stored in the field memory 120. Under the control of the main timing signal generator 106, the display generator 124 extracts the previously stored subsampled samples from the field nemory 120, when the PIP image 4 is being displayed. The display generator 124 performs an inverse function to the subsampling performed in the quincunx subsampler 116 to generate a sample sequence representing the inset auxiliary image. In addition, the αisplay generator 124 includes a digital-to- analog converter if the main video signal 104 is maintained in the analog domain. The output signal from the display generator 124, thus, corresponds to the output signal from the main video processor 104. That is, if the output signal from the main video processor 104 is respective analog luminance and chrominance signals (as in the preferred embodiment), then the output signal from the display generator 124 is also respective analog luminance and chrominance signals.

During the time when the PIP inset image 4 is to be displayed, the multiplexer 108 is conditioned to pass the decoded samples from the decoder 124 to its output terminal. When the main image 2 is being displayed, the main video samples from the main ADC 104 are passed through the multiplexer 108. In the preferred embodiment, where the main and PIP image signals comprise respective analog luminance and chrominance signals, the multiplexer 109 comprises two analog signal switches, one switching between the analog luminance components of the main viαeo and PIP video signals, and the other switching between the analog chrominance components of the main video and PIP viceo signals. If the main chrominance signal is demodulated into I and Q or U and V signals, or further dematrixed into R, G and B color component signals, then three multiplexers, one for each component, are provided.

As described above, when horizontal subsampling is performed, the horizontal resolution of the image represented by the subsamples has low horizontal resolution. Using quincunx sampling, described below, is a method of overcoming the low horizontal resolution of the subsampled PIP image.

Fig. 3 is a more detailed illustration of the received PIP display image 4 illustrating quincunx sampling. As described above, in the preferred embodiment, the luminance and chrominance components of the PIP video signal are separated into respective sample streams. The top portion of Fig. 3 illustrates the sampling pattern of a portion of a frame of the PIP image sample sequence. Each line in Fig. 3 represents the results of vertically filtering (e.g. averaging) three vertically adjacent lines in each field. Each line of vertically filtered samples (referred to simple as lines, below) is represented by a horizontal line of "X"s or "+"s (referred to simply as samples, below). Each such sample is produced at a cycle of the PIP 4·f_sc timing signal (PIP CLK), illustrated below the illustrated portion of the received PIP display image, and consists of one portion representing the luminance component of that sample, and one portion representing the chrominance component of that sample. Each "X" represents a sample taken in the horizontal subsampling process, and each "-" represents a sample s<ιpped. Because the PIP viceo image is interlaced, adjacent vertically filtereα horizontal lines are transmitted in successive fields.

In the topmost line of Fig. 3, samples are taken, "X", every sixth sample, witn the leftmost sample being the first sample taken. Five samples are then skipped, "+", before the next sample is taken "X". This pattern repeats through the remainder of the line. Samples in the third and fifth illustrated vertically filtered lines are taken at the same set of horizontal locations as the first line. Because of the interlacing, these lines are all from the same field. Thus, each line in a field is sampled in an identical pattern. This pattern is designated sample pattern SP1.

In the second line of Fig. 3, in the next field, the fourth sample, "X", is the first sample taken. Then, five samples are skipped,^' "+", before the next sample is taken.

This pattern repeats through the remainder of the line. Sam- pies in the fourth line are taken at the same set of norizontal locations as the second line. The samples in this field are taken from horizontal locations midway between the horizontal locations of samples of the adjacent lines from the preceding field. This pattern, designated sample pattern 3P2, may be produced by delaying the subsampling timing signals wnich generate sample pattern SP1 by three 4·f_sc PIP clock cycles. Tne use of sample patterns SP1 and SP2 results m a pattern of sampling termeα quincunx sampling, and increases the perceived horizontal resolution of the PIP image by providing samples from more horizontal locations m the PIP image. The samples taker illustrated as "X"s m the top portion of Fig. 3 are stored in the memory 120 [of Fig. 2).

The bottom portion of Fig. 3 illustrates the method for displaying the PIP inset samples previously stored in the memory 120 ιof Fig. 2) as described above. The bottom portion of Fig. 3 illustrates a portion of the PIP image 4 as it is displayed in the combined image illustrated in Fig. 1. Each sample illustrated in the bottom portion of Fig. 3 is produced at a mam 4 · f_sc timing signal time (MAIN CLK). In general, each sample is displayed, as represented by an "X", and then immediately repeated, as represented by an "O" immediately to the rignt of its corresponding "X".

The leftmost sample of the topmost line of the illustrated portion of the PIP image 4, "X", is displayed. This sample is then repeated at the next 4·f_scmaιn clock time, "O". Then the next previously stored sample is displayed, "X", and immediately repeated, "O". This is repeated for the remainder of this PIP image line. This pattern is repeated for the third and fifth (and all odd numbered) lines of the PIP image. These lines are in the same field as that of the first line. Thus, as for the PIP video signal sampling process described above, each line in a field is displayed in the same pattern. This pattern is designated display pattern DP1, and corresponds to sample pattern SF1, described above.

The leftmost sample of the second line is an "0", which is a repeat of a preceding sample (not shown) immediately to its left. The second sample of the second line, "X", is displayed, and then immediately repeated at the next 4 · f_sc main clock time, "O" . Then the next previously stored sample is displayed, "X" and repeated "O". This is repeated for the remainder of this PIP inset image line. The same pattern is repeated for the fourth (and all even numbered) lines of the PIP image. This pattern is designated display pattern DP2, and corresponds to sample pattern SP2, described above. The display pattern DP2 may be produced by delaying the samples produced as display pattern DP1 by one 4 · f_sc main clock cycle. Each sample consists of a portion representing the luminance component of that sample and a portion representing the chrominance component of that sample. In the preferred embodiment, theses sample portions are converted independently to analog form and respective luminance and chrominance analog signals generated, corresponding to the analog luminance and chrominance signals generated by the main video processor 104. As can be seen, the "X"s, representing the first display of previously stored PIP image samples, are arranged in a quincunx display pattern, the same as the sampling pattern illustrated in the top portion of Fig. 3. In this manner, the perceived horizontal resolution of the PIP image is increased without increasing the memory size required of the field memory 120 (of Fig. 2).

A proolem can arise using quincunx sampling for a PIP mage signal, however. This problem may be better understood by reference to Figs. 4 and 5. Fig. 4 is a waveform diagram, of the main and PIP video signals, and of PIP memory access addresses. In Fig. 4, the signal from the main video signal source 102 (of Fig. 2) is illustrated in the top waveform as consisting of successive frames. As in standard interlaced viαeo signals, in each frame there are two fields whose lines are interlaced in a known manner, and usually designated even and odd fields. Each field of the main video signal is represented by a rectangle. This is represented in Fig. 4 by numbering the rectangles representing the fields of the main video signal 1 and 2. Two complete fields of the main video signal, 1 and 2, respectively, are illustrated in Fig. 4. The left hand edge of each rectangle represents the time location of the vertical synchronization pulse associated with tnat field.

There is no intended correspondence between even and odd fields of a video frame, and the field designations 1 and 2 in Fig. 4.

The signal from the PIP video signal source 110 is illustrated in the second waveform. This video signal also includes successive frames, each frame containing two fields of interlaced lines, each represented by rectangles numbered 1 and 2. The left hand edge of each rectangle represents the time location of the vertical synchronization pulse associated with that field. The PIP video signal is not temporally aligned witn the main video signal, as indicated by the differing tine locations of the vertical synchronization pulses between the πam and PIP video signals. Referring to Fig. 2, as samples of the PIP video signal, containing a luminance and a chrominance portion in the preferred embodiment, are generated by the PIP video processor 113, they are first vertically filtered, and then the vertically filtered samples are horizontally subsampled, in a manner to be described in more detail below, at times controlled by the subsampler 116, and those subsampled samples are stored in the memory 120 in locations controlled by the write address generator 118. In response to the PIP vertical synchronization pulse, the write address generator resets the write address to the beginning of the field memory 120 (or to the beginning of a buffer within the field memory 120) which is to hold the subeampled PIP inset samples. Such a buffer is usually filled from a low address to a high address, so this initial address is the minimum address. The write address produced by the write address generator 118 is represented in Fig. 4 in the third waveform. At the beginning of field 2 in the PIP video signal (second waveform), the write address generator 118 is conditioned to produce a PIP write address which is the minimum address. As subsampled samples are produced by the subsampler 116 (of Fig. 2), they are stored in the field memory 120 at increasing addresses as supplied by the write address generator 118. This is indicated in Fig. 4 by a gradually increasing write address signal. By the end of field 2, subsampled samples have beer, written into all of the write buffer, and the address signal nas reached its maximum value. The vertical synchronization pulse of the next field (field li then resets the write address generator 113 address to the beginning of the buffer (i.e. the minimum address) again, and the process repeats itself.

While subsampled PIP samples are being written into the memory 120 under control of the subsampler 116 and the write address generator 118, as described above, the scan location of the main video signal is being monitored by the display generator 124. During the first portion of the main image, 6 (of Fig. 1), no portion of the PIP image is being displayed.

During the last portion of the main image, 8, (e.g. in the illustrated embodiment, the bottom third of the combined image) the subsampled samples previously stored in the memory 120 are retrieved by the display generator 124 from addresses controlled by the read address generator 122. These samples are processed by the display generator 124 in a manner to be described in more detail below, to produce the sampie pattern illustrated at the bottom of Fig. 3. In the preferred embodiment, these samples are further processed to form respective analog luminance and chrominance signals. These signals are then substituted for the corresponding main video luminance and chrominance signals at the multiplexer 108, during the time when the PIP image is being displayed. Similarly to the write acdress generator 118, the vertical synchronization pulse of the main video signal conditions the read address generator 122 to produce an acdress whicn points to the beginning of the field memory 120 (or the beginning of the buffer in the field memory 123) holding the PIP subsampled samples. During the bottom portion, 8, of the combined image where the PIP image 4 is inserted into the combined image, the read address generator 122 controls the field memory 120 to retrieve PIP samples from the field memory 120 m the same order as they were written into the field memory 120 by the subsampler 116. Thus, samples are retrieved starting at the minimum address and progressing to the maximum address as the PIP image samples are inserted into the combined image.

The read addresses generated by the read address generator 122 are represented by the fourth waveform. At the vertical synchronization pulse of the main video image, the read acdress generator 122 is conditioned to produce the address of the beginning of the field memory (or buffer within the field memory). The address doesn't change during the first portion, 6, of the combined video image. As the PIP samples are extracted from the field memory 120, the read address increases to the maximum address by the end of the main video field 2. The beginning of the next main video field 1 resets the read address generator 122 and the process repeats. Fig. 5 illustrates a problem which can occur with one implementation of quincunx sampling in a PIP system. In Fig. 5, a portion of the contents of the field memory 120 at a time TS1, which occurs within field 1 of the PIP image, as illustrated in Fig. 4. Referring to Fig. 5, a portion of the preceding field of the PIP image, field 2, is illustrated in the upper left hand portion of Fig. 5, witn its sampling pattern SP2 illustrated (using the same indicia as in Fig. 3). Dashed lines represent lines from field 1. Field 2 is scanned from top to bottom, in normal manner, as indicated by the arrow to the left of field 2. A portion of the next successive field, field 1, is illustrated directly below field 2, with its sampling pattern SP1. Dasned lines represent lines from field 2. Field 1 is also scanned from top to bottom as indicated by the arrow to the left of field 1. To the right of the fields 1 ana 2 images, is the state of the portion of the memory 120 corre- sponding to the illustrated portions of field 1 and field 2, at the time TS1. The memory 120, as illustrated in Fig. 5, is written into from the top to the bottom, as indicated by the arrow to the right of the memory 120. One skilled in the art will understand that only the subsampled samples, "X", are stored in the memory, and not the intervening samples "+". The patterns illustrated in the memory block 120 of Fig. 5 are meant merely to indicate the sampling pattern in which the subsampled samples stored in the illustrated portion of the field memory 120 were taken. At the end of PIP image field 2, the memory 120 is completely filled with subsampled samples, "X", taken from field 2 using sampling pattern SP2. At the start of field 1, the field 2 samples in memory 120 are overwritten witn subsampled samples from field 1 using sampling pattern SP1, starting at the top of the memory toward the bottom, &s illustrated in Fig. 5. At time TS1, the bottom portion of the memory 120 contains samples from frame 2, as indicated by the arrow from frame 2 to the bottom portion of the memory 120; while the top portion contains samples from frame 1, as indicated by the arrow from frame 1 to the top portion of the tremory 120.

Referring to Fig. 4, a portion of the PIP write acdress waveform for field 1 of the PIP video signal is superimposed in phantom atop the PIP read address waveform for field 2 of the main viαeo signal. At time TS1, the PIP read address is the same as the PIP write address. Referring to Fig. 5, immediately before time TS1, line 202 from field 1 of the PIP image is subsampled from the PIP video signal and is written into the memory 120 at the address provided by the write address generator 118 (of Fig. 2). In addition, line 202, just written into the memory 120, is read from that same location in the memory 120 and displayed at the appropriate location in the PIP inset image 4 (of Fig. 1). Immediately after time TS1, the samples making up the next line 204 in the PIP image 4 (of Fig. 1) are to be read from the memory 120 at the address provided by the read address generator 122. However, this line has not yet been received and subsampled from the PIP video signal in field 1. Instead, the line 204 of the displayed PIP image 4 is generated from samples which were subsampled from the previous field 2. Line 202 (and the preceding lines! of the displayed PIP image 4 was sampled from field 1 of the PIP image, while line 204 (and the remaining lines) was sampled from the preceding field 2, which, thus, occurs 1/60 second earlier than field 1 (in the United States NTSC standard). This juxtaposition in the PIP image produces what is termed a temporal seam, TS, and is a phenomenon known in PIP systems using field memories. In addition to the temporal seam, in the system illustrated in Fig. 5, the samples in the lower portion of the field memory 120 (e.g. from the current field 1) were taken using sampling pattern SP1, while the samples in the upper portion of the field memory 120 (e.g. from the preceding field 2) were taken using the sampling pattern SP2. The difference in the horizontal locations of the samples taken between sampling pat- terns, SPI and SP2, of field 1 and field 2, respectively,

(emphasized by the sampling patterns illustrated in the memory block 120 in Fig. 5) makes a visible discontinuity in the displayed PIP image 4 at the temporal seam location, termed a spatial seam in the remainder of this application. The change in sampling patterns at the temporal seam, thus, causes a perceptible degradation of the PIP image at the temporal seam.

Fig. 6 corresponds to Fig. 5, and illustrates a solution to the problem of the spatial seam at the temporal seam TS1, and its perceptible degradation of the PIP image. The begin- ning of field 2 is sampled using sample pattern SP2 (as illustrated in Fig. 3), which continues until time TS2, as is illustrated at the bottom of Fiα. 4. At time TS2, the subsampling pattern for field 2 is changed frorr sample pattern SP2 to samp.e pattern SP1, ana the remainder of field 2 is sampled using sample pattern SP1. At the beginning of field 1, the sampling pattern remains SP1 until time TS1. At tine TS1, the sample pattern is changed to sanple pattern SP2 again. This is repeated fcr all successive fields.

The result of controlling the sampling patterns in this manner is shown in the memory 120 status at time TS1 in Fig. 6. At time TS1, the bottom portion of the memory 120 still con- tarns that portion of the subsampled samples from the bottom portion of field 2 (e.g. below the line indicating time TS2 in field 2). These samples have been sampled using sample pattern SP1, as described above. The top portion of the memory 120 contains subsampled samples from the top portion of field 1 (e.g. above the line indicating time TS1 in field 1). These samples aiso have been sampled using sample pattern SP1. Thus, when these samples are retrieved from the memory 120 to generate the PIP image 4, the sample pattern will be consistent from top to bottom of the PIP image. There will be no perceptible spatial seam at the temporal seam location in the main video field 1. In a similar manner, although not illustrated, all the samples for the next field of the displayed PIP image 4 (of Fig. 1) will have been sampled using sample pattern SP2, again, producing no perceptible spatial seam at the temporal seam location for that field. Fig. 7 is a diagram, partially m block forn and partially in logic form, of a subsampler llδ for generating subsampled PIP samples for storage m the field memory 120 (of Fig. 2). In Fig. 1 , the read address signal from the read address gener- ator 122 is coupled to a first input terminal of a comparator 405, and the write address signal from the write address generator 113 is coupled to a second input terminal of the comparator 405. An output terminal of the comparator 405 is coupled to a set input terminal S of an S-R flip flop 410. A non- inverting output terminal Q of the S-R flip flop 410 is coupled to an input terminal of an inverter 420. An output terminal of the inverter 420 is coupled to a first input terminal of an exclusive-OR gate 430. An output terminal of the exclusive-OR gate 430 is coupled to a first input terminal of an AND gate 435. An output terminal of the AND gate 435 is coupled to a control input terminal of a multiplexer 450. The PIP vertical synchronization pulse signal from the PIP timing signal generator 114 is coupled to a reset input terminal R of the S-R flip flop 410. A signal indicating the current PIP video signal field type (described below) is coupled to a second input terminal of the exclusive-OR gate 430. A signal, FREEZE*, an active-low signal indicating that a freeze frame function is to be performed, is coupled to a second input terminal of the AND gate 435. A PIP horizontal synchronization reset signal from the PIP timing signal generator 114 is coupled to a first data input terminal of the multiplexer 450 and to an input terminal of a three 4-f_sc PIP timing signal cycle delay circuit 440. In the preferred embodiment, the PIP horizonta. synchronization reset signal is a pulse naving a width of a single PIP 4-f_sc cycle occurring at the middle of the PIP horizontal synchronization component signal. Alternatively, such a pulse signal may occur at the beginning or end of the PIP horizontal synchronization signal, or anywhere wit.nm the horizontal synchronization signal.

An output terminal of the delay circuitry 440 is coupled to a second data input terminal of the multiplexer 450. An output terminal of the multiplexer 450 is coupled to a reset input terminal of a divide-by-6 circuit 460. A timing signal output terminal of the dιvιde-by-6 circuit 460 produces a PIP subsample timing signal, and is coupled to a corresponding input terminal of a subsampler 470. The 4-f_sc PIP timing signal from the PIP timing signal generator 114 is coupled to a timing signal input terminal of the dιvide-by-6 circuit 460. The PIP video sample stream from the PIP video processor 113 is coupled to a data input terminal of the subsampler 470. An output termma'l of the subsampler 470 produces subsampled data, and is coupled to the field memory 120.

Referring to Fig.3, it may be seen that the sample pattern SP2 is identical to the sampling pattern SP1, but delayed by three 4·f_sc PIP timing signal cycles. In operation, the S-R flip flop 410 is reset at the beginning of each PIP field by the PIP vertical ynch ronιzatιon pulse . Thus, at the beginnng of eacn field, the signal at the Q output terminal of the S-R flip flop 410 is a logic '0' signal. The comparator 405 monitors the PIP read address and the PIP write address. When they are the same (e.g. at time TS), the comparator generates a logic '1' signal, and generates a logic '0' signal otherwise. This logic '1' signal from the comparator 405 at time TS sets the S-R flip flop 410, generating a logic '1' signal at the Q output terminal. This signal is inverted by the inverter 420 to produce a signal which is a logic '1' within a field before time TS and a logic '0' after time TS.

The PIP field type signal is a bistate signal indicating the type of the PIP field currently being received. Referring to Fig. 4, a PIP field is either field type 1 or field type 2. As described above, there is no intended correspondence between even ana odd fielas and field types 1 and 2. In the illustrated embodiment, a logic '0' signal indicates field type 1 and a logic ' 1' signal indicates field type 2. The exclusive- OR gate 430 operates to generate a signal representing the proper sampling pattern (e.g. SP1 or SP2) which is to be used to subsample the PIP video signal. In the illustrated embodiment, when the output of the exclusive-OR gate 430 is a logic '1' signal, sampling pattern SP1 is used, and when it is a logic '0' signal, sampling pattern SP2 is used.

Referring again to- the description of Figs. 5 and 6, above, for field type 1, sample pattern SP1 is used before time Tsi and sample pattern SP2 is used afteri time TS1. For field type 2 sample pattern SP2 is useα before time TS2 ana sample pattern SP1 is used after time TS2. Wnen the PIP field type signal is a logic '0' signal, indicating field 1, and the

BEFORE TS signal is a logic '1', e.g. before TS1, then the output of the exclusive-OR gate 430 is a logic '1' signal, which indicates sample pattern SP1. When the BEFORE TS signal changes to a logic '0' signal at time TS1, the output of the exclusive-OR gate 430 changes to a logic '0' signal, indicating sample pattern SP2. When the PIP field type signal is a logic '1' signal, indicating field 2, and the BEFORE TS signal is a logic '1', e.g. before TS2, then the output of the exclusive-OR gate 430 is a logic '0' signal, which indicates sample pattern SP2. When the BEFORE TS signal changes to a logic '0' signal at time TS2, the output of the exclusive-OR gate 430 changes to a logic '1' signal, indicating sample pattern SP1.

The sample pattern selection signal from the exclusive-OR gate 430, SP1/*SP2, is gated through the AND gate 435 by the *FREEZE signal. The *FREEZE signal, as described above, is used to indicate that a PIP freeze frame is to be performed. In a freeze frame operation, the writing of PIP data to the field memory 120 (of Fig. 2) is suspended, while read operation continues unchanged. Because no new samples are being written into the field memory 120 in this condition, the same samples are repeatedly read from the field memory and used to generate the inset PIP image. This has the effect of producing a fixed, or frozen, PIP inset image 4 on the display device. If, how-ever, write operations are suspended at the end of a PIP f field bemg quincunx sampled, as described aoove, then the portion of the field memory 120 written to before tine TS will contain samples which were sampled with a one sample pattern while the portion of the field memory 120 written to after time TS will contain samples which were sampled witn the other sample cat- tern.

During times when the full motion PIP image is being displayed, controlling the sampling patterns as just described, avoids a spatial seam at the temporal seam location, as de- scribed above. However, during times when the PIP image 13 frozen, this same overall sampling pattern will introduce a spatial seam into the PIP image at the temporal seam location. In order to prevent the display of a spatial seam at .the temporal seam location in a frozen PIP image, the quincunx sampling is suspended for at least two fields before the writing of PIP viceo subsampled samples to the field memory 120 is susperded. The PIP inset image is subsampled in a rectangular pattern instead. While this decreases the perceived horizontal resolution, it eliminates the spatial seam at the temporal seam location which would result from freezing a quincunx sampled signal.

When the *FREEZE signal is a logic '1' signal, indicating that no freeze is imminent, the SP1/*SP2 signal is passed through the AND gate 435 to the control input terminal of the multiplexer 450. When the "FREEZE signal is a logic '0' signal, indicating that fr eeze is immitent , then the SP1/-SP2 signal is blocked, and the output of the AND gate 435 is a logic '0' signal, indicating that sample pattern 3?2 is to be used throughout the subsequent fields. This suspends the quincunx sampling pattern resulting from the simultaneous use of both sample pattern SP1 and SP2. Instead, the auxiliary image is subsampled in a rectangular pattern at the set of horizontal locations defined by sample pattern SP2. This continues for two fields, under the control of other, known, circuitry (not shown). Then this other circuitry suspends write operations to the field memory 120. When the freeze is canceled, the * FREEZE signal is conditioned to become a logic '1' signal, and quincunx sampling is enabled once more.

When the signal from the AND gate 435 is a logic '1' signal, indicating that sample pattern SP1 is to be used, the multiplexer 450 is conditioned to couple the PIP horizontal synchronization reset pulse signal directly from the PIP timing signal generator 114 to the reset input terminal of the divide- by-6 circuit 460. When the signal from the AND gate 435 is a logic '0' signal, indicating that sample pattern SP2 is to be used, the multiplexer 450 is conditioned to couple the delayed PIP horizontal synchronization reset pulse signal from three 4·f_sc PIP timing signal cycle delay circuit 440 to the reset input terminal of the divide-by-6 circuit 460.

The divide-by-6 counter produces a subsampling pulse every sixth PIP 4·f_sc timing signal cycle, starting from when a reset pulse is received from the multiplexer 450. When the undelayed PIP horizontal synchronization reset pulse is received at the reset input terminal of the divice-by-6 circuit 460 from the multiplexer 450, samples are taken at times whicn result in sample pattern SP1 (of Fig. 3). When the PIP horizontal synchronization reset pulse delayed by three PIP 4'f_sc clock cycles is received at the input terminal of the divide-by-6 circuit 460 from the multiplexer 450, samples are taken at times which result in sample pattern SP2. The subsampler 470 subsamples the PIP video sample stream from the PIP video processor 113 in response to the sampling signal from the divide-by-6 circuit 460. These subsampled samples are supplied to the field memory 120 (of Fig. 2).

Fig. 8 is a diagram, partially in block form and partially in logic form, of a PIP inset image display generator 124 for generating PIP data for insertion into a main image. In Fig. 8, PIP subsampled samples from the field memory 120 (of Fig. 2) is coupled to an input terminal of a sample retrieval circuit 479. An output terminal of the sample retrieval circuit 479 is coupled to an input terminal of a one main 4·f_sc timing signal cycle delay circuit 480 and to a first data input terminal of a multiplexer 490. An output terminal of the delay- circuit 480 is coupled to a second data input terminal of the multiplexer 490. An output terminal of the multiplexer 490 is coupled to the multiplexer 108 (of Fig. 2). Amain field type signal is coupled to a first input terminal of an AND gate 485, and the *FREEZE signal (of Fig. 7) is coupled to a second input terminal of the AND gate 485. An o utput terminal of the AN D gate 455 is coupled to a control input terminal of the multiplexer 490.

In operation, samples are retrieved from the field memory 120 from locations specified by the read aαdress signal from the read address generator 122 by the sample retrieval circuit 479. As described above, in a preferred embodiment, these samples each have one portion representing the luminance component of that sample, and a second portion representing the chrominance component of that sample. The sample retrieval circuit 479, retrieves a sample at a 4-f_sc PIP timing signal cycle and provides that sample at its output terminal. The sample retrieval circuit 479 then holds that sample at its output terminal to be repeated at the next 4·f_sc PIP timing signal cycle. Then the next sample is retrieved from the field memory 120. This is repeated for all the samples in each line in the field memory 120.

Referring to Fig. 3, in operation, the main field type signal provides an indication of the display pattern (DP1 or DP2) corresponding to the sample pattern (SP1 or SP2, respectively) used to subsample the PIP video data currently being retrieved from the field memory 120 in a similar manner to the PIP field type signal described above with reference to Fig. 7. That is, when sample pattern SP1 had been used to sample the data currently being retrieved from the field memory 120, display pattern DP1 is used to display that data, and when sample pattern SP2 had been used to sample the data, then display pattern DP2 is used to display it. The 'FREEZE signal, described aDove with reference to Fig. ⁷ is an active-lew signal wnich is asserted when a freeze function is imminent. In response to this signal, quincunx sampling is disabled.

This signal is used to gate the main field type signal to the control input terminal of the multiplexer 490.

In the illustrated embodiment, when the main fielα type signal is a logic '1', then display pattern DP1 is used to display the subsampled PIP samples, and when it is a logic '0' signal, then display pattern DP2 is used to display the subsampled PIP samples. When enabled by the *FREEZE signal, the main field type signal controls the multiplexer 490. When the main field type signal is a logic '1' signal, indicating display pattern DP1, then the multiplexer 490 is conditioned to couple the PIP sampled data directly from the sample retrieval circuit

479 to the multiplexer 108. This provides PIP subsampled samples undelayed, and produces the display pattern DP1, illustrated in Fig. 3. When the main field type signal is a logic '0' signal, indicating display pattern DP2, then the multi- plexer 490 is conditioned to couple the delayed PIP sampled data from the one main 4 · f_sc timing signal cycle delay circuitry

480 to the multiplexer 108. The delay introduced by the delay circuit 480 produces the display pattern DP2, illustrated in Fig. 3. When the *FREEZE signal indicates that a freeze frame function is being performed, then the output of the AND gate 485 is a logic '0', indicating display pattern DP2, which corresponds to the sampling pattern 3?2 selectee by the *FREEZE signal in Fig. 7.

The PIP sampling system descπoed aoove, and illustrated in the drawing provides a PIP inage with improved horizontal resolution without requiring additional samples, or a larger field memory. In addition, this system eliminates the perceptible spatial seam at the temporal seam location which can occur in such a system. Finally, this system provides a method for providing a freeze frame function without introducing a spatial seam at the temporal seam location into the frozen PIP image.

Claims (17)

What is claimed is:

1. Apparatus fcr displaying a combined image of an auxiliary im age and a main image, comprising:

a source of a main image signal;

a source of samples representing an auxiliary image signal;

a quincunx subsampler, coupled to the auxiliary image sample source; and

a signal combiner, coupled to the main image signal source and the quincunx subsampler, for combining the main image representative signal and a signal representing the quincunx subsampled samples to generate a signal representing a combined image of the main and auxiliary images.

2. The apparatus of claim 1, wherein the quincunx sub- sampler selectively subsamples the auxiliary image samples in one of a first sample pattern taking samples at a first set of horizontal locations and a second sample pattern taking samples at a second set of horizontal locations substantially midway between the first set of horizontal locations.

3. The apparatus of claim 1, wherein the auxiliary image sample source comprises:

a source of an auxiliary image signal, including a video component and a synchronization component; an auxiliary analog-to-digital converter responsive to the auxiliary image signal video component, for generating samples representing the auxiliary video component; and

an auxiliary timing signal generator, responsive to the auxiliary im age signal synchronization component, for generatin g the auxiliary sample timing signal.

4. The apparatus of claim 3 wherein the quincunx subsampier is further responsive to a timing signal from the auxillary timing signal generator.

5. The apparatus of claim 4 wherein:

the auxiliary timing signal generator further generates an auxiliary horizontal synchronization reset signal and an auxillary field type signal having a first state during auxiliary video odd fields and a second state during auxiliary video even. fields; and

the quincunx subsampler comprises:

a subsampler, coupled to the auxiliary sample source, and responsive to a subsample timing signal, for subsampling the auxiliary video component representative samples at times determined by the subsample timing signal;

a timing signal divider, responsive to the auxiliary sample timing signal and a reset signal, for producing the subsample tining signal; and a reset signal generator, responsive to the auxiliary horizontal synchronization reset signal and tn.e auxiliary field type signal, for generating a reset signal procucing a first sampling pattern in even auxiliary fields and a second sampling pattern m odd auxiliary fields.

6. The apparatus of claim 5 wherein:

the timing signal divider proαuces one subsample timing signal for each predetermined number of auxiliary sample timing signals, starting at the time the reset signal is receiveα; and the reset signal generator is responsive to the auxiliary field type signal naving the first state to produce a reset signal simultaneous witn the auxiliary horizontal synchromzation reset signal, and is responsive to the auxiliary field type signal having the second state to produce a reset signal which is the auxiliary horizontal synchronization reset signal delayed by one half the predetermined number of auxiliary sample timing signals.

7. The apparatus of claim 6 wherein the reset signal generator comprises:

a delay circuit, responsive to the auxiliary horizontal synchronization reset signal, for delaying the auxiliary honzontal synchronization reset signal by one half the predetermined number of auxiliary sample timing signals; a multiplexer having a first data input terminal responsive to the auxiliary horizontal synchronization reset signal, a second data input terminal coupled to the delay circuit, a control input terminal responsive to the auxiliary field type signal, and an output terminal producing the reset signal.

8. The apparatus of claim 5 wherein:

subsamples are taken m the first sampling pattern at respective times in eacn horizontal line corresponding to respective horizontal positions; and

subsamples are taken in the second sampling pattern at respective times in horizontal lines corresponding to horizontal positions midway between the respective horizontal positions in the first sampling pattern.

9. The apparatus of claim 1, further comprising a main timing signal generator, coupled to the main image signal source; and wherein the sample combiner comprises:

an inset image display generator, coupled to the quincunx subsampler and responsive to a timing signal from the main clock signal generator, for generating a signal representing an inset auxiliary image; and

a multiplexer, having a first data input terminal coupled to the inset image display generator, a second data input terminal coupled to the main image signal source, and an output terminal producing a signal representing the combined image.

10. The apparatus of claim 9, wherein:

the main timing signal generator further proαuces a select signal having a first state when the signal from the inset image display generator forms the combined image, ana a second state when main image signal forms the combined image; anc

the multiplexer further comprises a control input terminal responsive to the select signal, and couples the inset image signal to its output terminal when the select signal nas the first state and the main image signal to its output terminal when the select signal nas the second state.

11. The apparatus of claim 10, wherein:

the main timing signal generator produces a main field type signal having a first state during an even main field, and a second state during an odd main field; and

the inset image display generator produces an inset image signal using a first display pattern when the main field type signal has the first state, in using second display pattern when the main field type signal has the second state.

12. The apparatus of claim 11 wherein:

the main timing signal generator generates the main sample timing signal as successive timing signal pulses; and

the inset image display generator comprises:

a sample retrieval circuit, coupled to the quin- cunx subsampler, for producing inset image display samples comprising successive pairs of samples, a first sample cf the pair being a quincunx suosamplec auxiliary image sample at one nain timing, signal p-ise, and a second sample of the pair being the first sample cf the pair repeated at the next main timing signal pulse; and

a circuit for producing the successive pairs of samples in synchronism with the main sample timing signal when the main field type signal has the first state, and in synchronism with the main sample clock signal delayed by one main sample clock cycle when the main field type signal has the second state.

13. The apparatus of claim 12 wherein the inset image display generator comprises:

a one main sample timing signal cycle delay circuit, coupled to the sample retrieval circuit; and

a multiplexer, having a first data input terminal coupled to the sample retrieval circuit, a second data input terminal coupled to the delay circuit, a control input terminal respon- sive to the main field type 3ignal, and an output terminal producing the inset image samples.

14. The apparatus of claim 1, wherein the signal combiner comprises:

an inset image display generator, coupled to the quincunx subsampler; and a multiplexer, having a first data input terminal coupled to the inset image display generator, a second data- input terminal coupled to the main image signal source, ana an output terminal procucing the combined image representative signal.

15. The apparatus of claim 1, further comprising a memory, coupled between the quincunx subsampler and the signal combiner, for storing a field of quincunx subsampled samples.

16. The apparatus of claim 15, wherein the memory is responsive to a write address signal, and further comprising: a source of an auxiliary image video signal, including a synchronization component;

an auxiliary timing signal generator, responsive to the auxiliary image signal synchronization component, for generating an auxiliary sample timing signal; and

a write address generator, responsive to the auxiliary sample timing signal, for generating a write address signal fo: the memory.

17. The apparatus of claim 15, wherein the memory is responsive to a read address signal, and further comprising: a source of a main image video signal, including a synchronization component; a main timing signal generator, responsive to the main image signal synchronization component, for generating a main sample timing signal; and

a read address generator, responsive to the main sample timing signal, for generating a read address signal for the memory.