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ATE450889T1 - Verfahren zur herstellung von verbindungs- strukturen - Google Patents

Verfahren zur herstellung von verbindungs- strukturen

Info

Publication number
ATE450889T1
ATE450889T1 AT07101676T AT07101676T ATE450889T1 AT E450889 T1 ATE450889 T1 AT E450889T1 AT 07101676 T AT07101676 T AT 07101676T AT 07101676 T AT07101676 T AT 07101676T AT E450889 T1 ATE450889 T1 AT E450889T1
Authority
AT
Austria
Prior art keywords
layer
substrate
organic material
porous layer
connection structures
Prior art date
Application number
AT07101676T
Other languages
English (en)
Inventor
Didier Louis
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE450889T1 publication Critical patent/ATE450889T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12347Plural layers discontinuously bonded [e.g., spot-weld, mechanical fastener, etc.]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
AT07101676T 2006-02-08 2007-02-02 Verfahren zur herstellung von verbindungs- strukturen ATE450889T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0650443A FR2897198B1 (fr) 2006-02-08 2006-02-08 Structure d'interconnexions et procede de realisation

Publications (1)

Publication Number Publication Date
ATE450889T1 true ATE450889T1 (de) 2009-12-15

Family

ID=37307276

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07101676T ATE450889T1 (de) 2006-02-08 2007-02-02 Verfahren zur herstellung von verbindungs- strukturen

Country Status (5)

Country Link
US (1) US7825023B2 (de)
EP (1) EP1818985B1 (de)
AT (1) ATE450889T1 (de)
DE (1) DE602007003488D1 (de)
FR (1) FR2897198B1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3069072B1 (fr) * 2017-07-11 2021-06-04 Commissariat Energie Atomique Procede de fabrication d'un micro/nano-filtre sur un micro/nano-canal ou micro/nano-cavite realise dans un substrat silicium

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2573854B2 (ja) * 1987-12-12 1997-01-22 日興バイオ技研株式会社 超精密装置の超精密洗浄方法
SU1661844A1 (ru) * 1989-01-19 1991-07-07 Латвийский Государственный Университет Им.П.Стучки Способ изготовлени анизотропного электропровод щего материала
US5750415A (en) * 1994-05-27 1998-05-12 Texas Instruments Incorporated Low dielectric constant layers via immiscible sol-gel processing
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
DE10227615A1 (de) 2002-06-20 2004-01-15 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
JP4574145B2 (ja) * 2002-09-13 2010-11-04 ローム・アンド・ハース・エレクトロニック・マテリアルズ,エル.エル.シー. エアギャップ形成
US7294568B2 (en) * 2004-08-20 2007-11-13 Intel Corporation Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures

Also Published As

Publication number Publication date
US20070275261A1 (en) 2007-11-29
FR2897198B1 (fr) 2008-09-19
EP1818985B1 (de) 2009-12-02
EP1818985A1 (de) 2007-08-15
FR2897198A1 (fr) 2007-08-10
DE602007003488D1 (de) 2010-01-14
US7825023B2 (en) 2010-11-02

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties