NL2027068B1

NL2027068B1 - Integrated circuit comprising improved die attachment layer

Info

Publication number: NL2027068B1
Application number: NL2027068A
Authority: NL
Inventors: Suman Nakka John
Original assignee: Stichting Chip Integration Tech Centre
Priority date: 2020-12-08
Filing date: 2020-12-08
Publication date: 2022-07-07
Also published as: WO2022124895A2; WO2022124895A3

Abstract

The present invention is in the field of an integrated circuit (IC) which is attached to a substrate. Thereby an IC-package is formed. Generally, in many IC packages, the devices are situated on top of a substrate. The present invention relates to an integrated circuit comprising a substrate, a die, and an improved die attachment layer, and a method of die bonding, wherein a die is attached to a substrate with a die attachment layer.

Description

P100574NL00 Integrated circuit comprising improved die attachment layer

FIELD OF THE INVENTION The present invention is in the field of an integrated circuit (IC) which is attached to a substrate. Thereby an IC-package is formed. Generally, in many IC packages, the devices are situated on top of a substrate. The present invention relates to an integrated circuit com- prising a substrate, a die, and an improved die attachment layer, and a method of die bond- ing, wherein a die is attached to a substrate with a die attachment layer.

BACKGROUND OF THE INVENTION The present invention is in the field of an integrated circuit (IC) which is attached to a substrate. Thereby an IC-package is formed. Generally, in many IC packages, the devices are situated on top of a substrate. The substrate may serve as a physical interconnection be- tween the devices and a board in a system. Sometimes this is referred to as embedded pack- aging. The purpose is to embed dies inside or on the substrate using a multi-step manufac- turing process. A die, multiple dies, MEMS or passives may be embedded in a side-by-side fashion in the core of an organic laminate substrate. The components can be connected using copper-plated vias. Three broad categories in IC packaging may be mentioned, namely lead- frame, wafer-level packaging (WLP), and substrate. The present invention makes in particu- lar use of a substrate. Substrate-based packages may fall into several categories, such as ce- ramic and organic laminate packages. Ceramic substrates can be based on aluminium oxide, aluminium nitride and other materials. Ceramic-based packages can be used for surface- mount devices, CMOS image sensors and multi-chip modules. Organic laminate substrates can be used for volumetric devices, flip-chip devices, and system-in-packages (SiPs). For these packages, the devices reside on top of the substrate. Such substrates may use similar or identical materials as a printed-circuit board (PCB). Organic substrates may also be multi- layer technologies, where at least two organic layers are separated by a metal layer. The metal layers act as an electromigration shield in the package. Typically, in a conventional die-attach process, only one die-attach material is used to attach die on to the substrate. In an alternative solution of wafer level chip scale packaging (WLCSP) technology, a die is connected to a substrate, which is then referred to as lead- frame, via. bumps while the free space in between the bumps (solder, Cu, etc.) and the die- edges and corners are filled with a (soft) tough material, which is called underfill. One of the most common failures of electronic packages is fracture of die and die- attach materials as can be visualized during reliability testing such as by thermal cycling (TMCL). During TMCL, the package may undergo thermal cycling from low temperatures (<0°C) to high temperatures (>100°C), and back. Quite often a fracture (or crack) is found at the corner of the die (or substrate), and it can propagates in different regions within the package. Also, fracture may occur as a consequence of poor package design, and of external factors, such as humidity.

The present invention therefore relates to an integrated circuit and further aspects thereof, which overcomes one or more of the above disadvantages, without compromising functionality and advantages.

SUMMARY OF THE INVENTION It is an object of the invention to overcome one or more limitations of the integrated circuits of the prior art and at the very least to provide an alternative thereto. The present invention relates to a new type of integrated circuit comprising a substrate (10), on the substrate an attachment layer (20), and on the attachment layer a die (30), characterized in that the die attachment layer comprises at least one first region (21) comprising a first attachment mate- rial and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region is located centrally on the substrate, wherein the at least one second region is located eccentric, such as at a side, at a part of a side, or at a corner. Therewith at least mechanical and material properties, such as (visco)elastic properties, of the respective elements (e.g. substrate, die, and attachment lay- er), and thermal coefficient can be matched to one and another much better. It is noted that typically a die attachment layer may have good (visco)elastic properties, which allow to mit- 1gate stresses, but provides limited thermal conductivity, which may cause the die or part thereof to become to warm, or vice versa. By carefully selecting respective attachment mate- rials a much better match in view of the (visco)elastic properties and thermal conductivity properties of the respective elements can be made. It is noted that the inner die attachment material (IDA) and outer die attachment material (ODA) are considered to be visco- plastic/ Viscoelastic, which both have a time and temperature dependency, in nature and not being elastic, which is considered time and temperature independent. It is also considered that the die and substrate are elastic in nature. With the present invention stress is mitigated. For instance, in an embodiment the present integrated circuit comprises a substrate 10 with a first thermal coefficient (TCE:), wherein thermal coefficients relate to linear expansion, on the substrate an attachment layer 20, and on the attachment layer a die 30 with a second thermal coefficient (TCEz), characterized in that the die attachment layer comprises at least one first region 21 with a third thermal coefficient (TCE3) and at least one second region 22 with a fourth thermal coefficient (TCE:), wherein the first region may be considered the in- ner region and the second region the outer region, wherein the at least one first region is lo- cated centrally on the substrate, which may be considered as inner die, wherein the at least one second region is located eccentric, such as at a side, at a part of a side, or at a corner, which may be considered as outer die, wherein the values of the respective third thermal coefficient (TCE:) and fourth thermal coefficient (TCE4) are each individually in between the values of the first thermal coefficient (TCE) and the second thermal coefficient (TCEz). It 1s noted that typically the thermal coefficient of the substrate TCE; is larger than the ther- mal coefficient of the die TCE», but sometimes and TCE>TCEy). Typically the TCEs are taken at room temperature (about 20 °C). The present invention relate to a combination of at least two die-attach materials to attach the die onto a substrate, which helps in preventing package failures, especially failures occurring close to the die corner. The first die-attach material is typically provided under a more central region of the die, such as except under the corner regions thereof. The second die-attach material may then occupy the corner and edges of the die. The second (or corner) die-attach material may further a lower modulus, a TCE closer to that of the substrate (s), and a high toughness. It is thus found that a combina- tion of two die-attach materials to attach the die on to a substrate helps in preventing the package failures especially occurring close to the die corner. The first die-attach material is under the entire region of the die except the corner regions. The second die-attach material occupies the corner and edges of the die. Thermal conductivities may be measured using a standard test, such as ASTM 5334, IEEE 442, such as by using a TEMPOS machine. Some examples of designs of the two die-attach materials are shown in the figures, such as in figs. 5a-e. The figures show application of the die attachment material on the substrate before actual attachment of the die; once the die is attached the attachment material spreads out over a surface of the substrate and likewise die. Dot-like application of the second material is preferred, as a risk of gas entrapment is reduced. In an alternative embodiment, the present integrated circuit may comprise at least one first region (21) with a first elastic modulus (EM), and at least one second region (22) with a second elastic modulus (EM), wherein the first elastic modulus (EM) of the at least one first region is higher than the second elastic modulus (EM:) of the at least one second region, and preferably wherein the first elastic modulus (EM;) of the at least one first region is lower than an elastic modulus of the die, and preferably wherein the second elastic modulus (EM:) of the at least one second region is higher than an elastic modulus of the substrate. The respective elastic moduli each individu- ally are selected from a Young’s modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus. The elastic modulus, such as the Young's modulus, is typically ex- pressed in GPa, and may be determined using a standard test, such as EN 10002-1, ASTM E8 and ASTM E111, e.g. using an Ametek. It is noted that inaccuracies in testing in practice do not matter much, as the present invention is more concerned with relative values (be- tween elements) than absolute values. Even further the two above embodiments may be combined.

In a second aspect the present invention relates to a method for die bonding comprising providing a substrate with a first thermal coefficient (TCE), providing an attachment layer with at least one first region with a third thermal coefficient (TCE:3) and at least one second region with a fourth thermal coefficient (TCE) on the substrate, and attaching a die, with a second thermal coefficient (TCE:), to the attachment layer, wherein the values of the respective third thermal coefficient (TCE:3) and fourth thermal coefficient (TCE4) are each individually in between the values of the first thermal coefficient (TCE;) and the second thermal coefficient (TCE), and wherein the value of the fourth thermal coefficient (TCE4) is in between the values of the third thermal coefficient (TCE:) and the first thermal coefficient

(TCE). Therewith the present integrated circuit can be obtained. Typically the first inner die-attach material is dispensed, printed (e.g. stencil) or applied as a preform film, and the second outer die-attach is deposited via non-contact deposition technology at the corner are- as of the die (e.g. via dispensing). These steps may be interchanged. So typical dispensing and printing processes can be used to achieve any die-attach designs. No special equipment’s is therefore needed. Then, using e.g. a die-bonder machine, the die may be placed on the two die-attachment materials and pushed such that the two materials will spread out and cover an entire area under the die. The inner die material (IDA) will typically cover the entire area under the die except the die edges and corners, whereas the outer die material (ODA) will then cover the edges and corners. The IDA and ODA regions typically touch one and anoth- er, and some, typically minor or no, mixing of the two materials may occur there. It is found that as such the ODA material can absorb the thermo-mechanical stresses while the IDA material provides for thermal and electrical paths. In comparison, for conventional WLCSP technology, the bumps serve as electrical and thermal path while the underfill material ab- sorbs the stresses. In view of viscoelasticity the following is noted. Unlike purely elastic substances, a viscoelastic substance has an elastic component and a viscous component. The viscosity of a viscoelastic substance gives the substance a strain rate dependence on time. Purely elastic materials do not dissipate energy (heat) when a load 1s applied, then removed. However, a viscoelastic substance dissipates energy when a load is applied, then removed. Hysteresis is observed in the stress—strain curve, with the area of the loop being equal to the energy lost during the loading cycle. Since viscosity is the resistance to thermally activated plastic de- formation, a viscous material will lose energy through a loading cycle. Plastic deformation results in lost energy, which is uncharacteristic of a purely elastic material's reaction to a loading cycle. The present invention provides a solution to one or more of the above mentioned problems and overcomes drawbacks of the prior art. Advantages of the present description are detailed throughout the description.

DETAILED DESCRIPTION OF THE INVENTION In an exemplary embodiment of the present integrated circuit the value of the fourth thermal coefficient (TCE) is in between the values of the third thermal coefficient (TCE3) and the first thermal coefficient (TCE;). In an exemplary embodiment of the present integrated circuit the value of the fourth thermal coefficient (TCE:) is in between the values of the third thermal coefficient (TCE3) and the second thermal coefficient (TCE:). As such one can modify and adapt the thermal coefficients in view of thermal proper- ties of die and substrate, respectively, such that problems of the prior art are overcome. In an exemplary embodiment of the present integrated circuit the at least one first re- gion comprises a material with a thermal conductivity of > 50 W/(m*K), preferably > 100

W/(m*K), such as > 150 W/(m*K).

In an exemplary embodiment of the present integrated circuit the at least one second region comprises a material with a thermal conductivity of > 40 W/(m*K) , preferably > 50 W/(m*K).

5 For better understanding some information is given below: Die (Si & SiC) 1120 - 450 W/(m*K) Substrate (Cu) 401 W/(m*K) Ag sinter (centre DA) :50 — 400 W/(m*K) (Depending on the % Sintering), Avg: ~250 Ag filled polymer DA :50 W/(m*K) It is noted that a typical thermal conductivity in W/(m K) range at room temperature, of a die, such as comprising Si, and at least one of silicon oxide, silicon nitride, and silicon carbide, is in the order of 120 — 450, which is a rther large range, that of a substrate, such as Cu, is around 400, whereas the attachment material with a % is in the range 50 — 400, and an Ag filled polymer DA is around 50 (all in W/(m*K)).

In an exemplary embodiment of the present integrated circuit the area of the at least one first region is 66-99% with respect to the bottom area of the die, preferably 75-95% thereof, more preferably 80-92% thereof, such as 85-90% thereof.

In an exemplary embodiment of the present integrated circuit the bottom area of the dieis from 1 mm?-400 mm}, preferably 2 mm?-100 mm}, such as 5 mm?-60 mm? In an exemplary embodiment of the present integrated circuit a shape of the at least one second region is selected from circular, rectangular, square, L-shape, and v-shape, series thereof, matrices thereof, and combinations thereof.

In an exemplary embodiment of the present integrated circuit the at least one first re- gion comprises a die-attach material selected from heat assisted attach materials, pressure- based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably wherein the metal is selected from Ag, Au. An amount of metal may vary from 1-35%, such as 2-20%, e.g. Ag.

In an exemplary embodiment of the present integrated circuit the at least one second region comprises a die-attach material selected from heat assisted attach materials, pressure- based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably wherein the metal is selected from Ag, Au. An amount of metal may vary from 1-30%, such as 2-20%, e.g. Ag.

In an exemplary embodiment of the present integrated circuit the attach material is lead free.

In an exemplary embodiment of the present integrated circuit the attachment layer has a thickness of 5-250 um, preferably 10-100 um, more preferably 20-80 um, such as 30-50 um.

In an exemplary embodiment of the present integrated circuit the attachment layer ex- tends up to a side of the die, preferably forming a fillet 27 of up to 97%, such as of 75-95%. Therewith the die is well embedded and a good heat dissipation is provided.

In an exemplary embodiment of the present integrated circuit the die an IC with an output power of >50 W, such as > 100 W, such as a Low power die with 80-100W output, a Medium Power die with 110-200W power output, or a high power die with 200-270W out- put.

In an exemplary embodiment of the present integrated circuit the substrate comprises a material selected from metals, such as copper, and alloys thereof, dielectric materials, such as metal oxides, laminates, such as epoxy-based laminates, epoxy-blends laminates, tape substrates, preferably comprising a polymer, such as poly-imide, ceramic materials, compris- ing fibres, such as fibre glass, multi-layers comprising two or more of the aforementioned materials, and combinations thereof.

In an exemplary embodiment of the present integrated circuit the die attach layer com- prises a cavity 28 for receiving the die, preferably a cavity adapted to outer dimensions of the die.

In an exemplary embodiment of the present method the at least one first region is pro- vided and thereafter the at least one second region is provided, or vice versa.

In an exemplary embodiment of the present method the at least one first region and the at least one second region each individually are provided by fluid dispensing, or by printing, or by stencilling, or by screen printing, or by depositing, or by preforming, or by a combina- tion thereof.

In an exemplary embodiment of the present method the at least one first region is pro- vided in the form of at least one central bar-shaped volume.

In an exemplary embodiment of the present method the at least one first region is pro- vided with at least one first order side branch, preferably at least one first order side branch in every corner, optionally with at least one further first order side branch at each longitudi- nal side of the substrate, wherein first order side branches may be oriented in-plane perpen- dicular to the at least one central bar-shaped volume, or under an in-plane angle therewith, such as under an angle of 30-60 degrees.

In an exemplary embodiment of the present method the at least one first region is pro- vided with at least one second order side branch of the first order side branch.

In an exemplary embodiment of the present method the at least one first region is pro- vided centrally on the substrate, such as over an area of 5-50% of the substrate, preferably 10-40% of the area, such as 20-35%.

In an exemplary embodiment of the present method the at least one second region is provided eccentric, such as at a side, at a part of a side, or at a corner, such as over an area of 1-15% of the substrate, preferably 2-10% of the area, such as 4-8%. In an exemplary embodiment of the present method the die is attached by applying pressure, or by applying heat, or by applying curing, or sintering, or diffusion, or a combina- tion thereof.

The invention will hereafter be further elucidated through the following examples which are exemplary and explanatory of nature and are not intended to be considered limit- ing of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims.

FIGURES Figures 1-3 show a cross-sections of the present device.

Figures 4a,b shows a top view of the present device.

Figures 5a-e show initial patterns of regions 21 and 22.

Figures 6a-b show ab overview (6a) and zoomed-in section (6b) at the corner of the die) with two die-attach materials.

DETAILED DESCRIPTION OF FIGURES In the figures: 10 substrate 20 die attachment layer 21 first region 22 second region 27 fillet 28 cavity die Figure 1 shows a cross-section of the present device, with a substrate 10, a die at- tachment layer 20, and a die 30.

Figure 2 shows a cross-section of the present device, with a substrate 10, a die at- tachment layer 20, and a die 30. Also a cavity 28 is provided for receiving the die.

30 Figure 3 shows a cross-section of the present device, with a substrate 10, a die at- tachment layer 20, and a die 30. Also a fillet 27 is provided for embedding the die, and for dissipating heat. The fillet as shown , from top to bottom, gradually increases in thickness. It also extends exactly to the top surface of the die, and hence is considered to be 100% in height.

In figure 4a an initial die attachment material configuration is shown, prior to attach- ing the die. On substrate 10 a first region 22 and several second regions 21 of die attachment material are provided. After attaching the die (the die being virtually removed) the first re- gion 21 is spread out over the central region of the substrate, whereas the second regions are slightly increased in surface are size and are position at the sides and comers.

Figures Sa-e show initial patterns of regions 21 and 22, with small and larger dots, and with thin and thick L-shaped corner sections. Figures 6a-b show ab overview (6a) and zoomed-in section (6b) at the corer of the die) with two die-attach materials. Initially, the double Y shape is stencil printed with IDA (Ag sinter material) and then the ODA material is dispensed in the shape of dots as shown in pic.5c (Note: we can use any shape in 5.a-c). Later, the die is placed on the ODA IDA pat- terns and pushed such that both ODA & IDA materials gets squeezed and flow out and cover the entire die area under the die. The IDA material covers the four corners of the die and forms a filled. While, the ODA forms a fillet on the edges of the die. Note: 6b pic. 1s zoom in of 6a at the ODA material. Then, the sintering/curing is done by increasing the temperature and time. After sintering the IDA & ODA changes from liquid to solid/stiff materials. A recipe for die attachment is as follows: Inner die attach application: - Stencil printing Heraeus DA295A and/or Tanaka TS-9853 - Stencil thickness 75 um Outer die attach application: - Needle dispensing process (contact dispensing) Dupont KA802 - Needle gauge 27 gauge - Dot size controlled or varied by: 0 Dispense pressure 1 — 2 bars 0 Dispense time 200 — 500 ms Inner die attach is applied before outer die attach, this is because of drying behavior of the outer die attach material. Die Attachment pressure: - Placement pressure of die is approx. 10 to 20 grams of force per mm? Sintering profile: A sintering temperature is gradually increased to about 200 C in about 120 minutes, maintained at said temperature during about 60 minutes, and then decreased during about 60 minutes to room temperature. The next section is added to support the search, and the section thereafter is consid- ered to be a full translation thereof into Dutch.

1. Integrated circuit comprising a substrate (10), on the substrate an attachment layer (20), and on the attachment layer a die (30), characterized in that the die attachment layer comprises at least one first region (21) comprising a first at- tachment material and at least one second region (22) comprising a second attachment mate- rial different from the first attachment material, wherein the at least one first region is located centrally on the substrate,

wherein the at least one second region is located eccentric, such as at a side, at a part of a side, or at a corner,

2. Integrated circuit according to embodiment 1, wherein the substrate (10) has a first thermal coefficient (TCE), wherein the die (30) has a second thermal coefficient (TCE:), wherein the at least one first region (21) has a third thermal coefficient (TCEz3), wherein the at least one second region (22) has a fourth thermal coefficient (TCE), and wherein the values of the respective third thermal coefficient (TCE:3) and fourth thermal co- efficient (TCEy) are each individually in between the values of the first thermal coefficient (TCE) and the second thermal coefficient (TCE:2).

3. Integrated circuit according to embodiment 1 or 2, wherein the at least one first region (21) has a first elastic modulus (EM), and at least one second region (22) has a second elas- tic modulus (EM:), wherein the first elastic modulus (EM) of the at least one first region is higher than the second elastic modulus (EM:) of the at least one second region, and prefera- bly wherein the first elastic modulus (EM) of the at least one first region is lower than an elastic modulus of the die, and preferably wherein the second elastic modulus (EM) of the at least one second region is higher than an elastic modulus of the substrate, wherein the re- spective elastic moduli each individually are selected from a Young’s modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus.

4. Integrated circuit according to embodiment 2 or3, wherein the value of the fourth thermal coefficient (TCE,4) is in between the values of the third thermal coefficient (TCE:) and the first thermal coefficient (TCE:), or wherein the value of the fourth thermal coefficient (TCE:) is in between the values of the third thermal coefficient (TCE:3) and the second ther- mal coefficient (TCE).

5. Integrated circuit according to any of embodiments 1-4, wherein the at least one first re- gion comprises a material with a thermal conductivity of > 50 W/(m*K), preferably > 100 W/(m*K), and/or wherein the at least one second region comprises a material with a thermal conductivity of > 40 W/(m*K) , preferably > 50 W/(m*K).

6. Integrated circuit according to any of embodiments 1-5, wherein the area of the at least one first region is 66-99% with respect to the bottom area of the die, preferably 75-95% thereof, more preferably 80-92% thereof, such as 85-90% thereof, and/or wherein the bottom area of the die is from 1 mm?-400 mm}, preferably 2 mm?-100 mm}, such as 5 mm?-60 mm?.

7. Integrated circuit according to any of embodiments 1-6, wherein a shape of the at least one second region is selected from circular, rectangular, square, L-shape, and v-shape, series thereof, matrices thereof, and combinations thereof.

8. Integrated circuit according to any of embodiments 1-7, wherein the at least one first re- gion comprises a die-attach material selected from heat assisted attach materials, pressure-

based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably wherein the metal is selected from Ag, Au, and/or wherein the at least one second region comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably wherein the metal is selected from Ag, Au, and/or wherein the attach material is lead free, and/or wherein the attachment layer has a thickness of 5-250 um, preferably 10-100 um, more pref- erably 20-80 um, such as 30-50 um.

9. Integrated circuit according to any of embodiments 1-8, wherein the attachment layer ex- tends up to a side of the die, preferably forming a fillet (27) of up to 97%, such as of 75- 95%.

10. Integrated circuit according to any of embodiments 1-9, wherein the die is an IC with an output power of >50 W, such as > 100 W, such as a Low power die with 80-100W output, a Medium Power die with 110-200W power output, or a high power die with 200-270W out- put.

11. Integrated circuit according to any of embodiments 1-10, wherein the substrate compris- es a material selected from metals, such as copper, and alloys thereof, dielectric materials, such as metal oxides, laminates, such as epoxy-based laminates, epoxy-blends laminates, tape substrates, preferably comprising a polymer, such as poly-imide, ceramic materials, comprising fibres, such as fibre glass, multi-layers comprising two or more of the aforemen- tioned materials, and combinations thereof.

12. Integrated circuit according to any of embodiments 1-10, wherein the die attach layer comprises a cavity (28) for receiving the die, preferably a cavity adapted to outer dimensions of the die.

13. Method of die bonding comprising providing a substrate, such as with a first thermal coefficient (TCE), providing an attachment layer with at least one first region, such as with a third ther- mal coefficient (TCE:3), and at least one second region, such as with a fourth thermal coeffi- cient (TCEs) on the substrate, and attaching a die, such as with a second thermal coefficient (TCE:), to the attachment layer, preferably wherein the values of the respective third thermal coefficient (TCE:3) and fourth thermal coefficient (TCE4) are each individually in between the values of the first thermal coefficient (TCE) and the second thermal coefficient (TCE:), and wherein the value of the fourth thermal coefficient (TCE) is in between the values of the third thermal coefficient (TCEj3) and the first thermal coefficient (TCE).

14. Method of die bonding according to embodiment 13, wherein the at least one first region is provided and thereafter the at least one second region is provided, or vice versa.

15. Method of die bonding according to embodiment 13 or 14, wherein the at least one first region and the at least one second region each individually are provided by fluid dispensing, or by printing, or by stencilling, or by screen printing, or by depositing, or by preforming, or by a combination thereof.

16. Method of die bonding according to any of embodiments 13-15, wherein the at least one first region is provided in the form of at least one central bar-shaped volume, optionally with at least one first order side branch, preferably at least one first order side branch in every corner, optionally with at least one further first order side branch at each longitudinal side of the substrate, wherein first order side branches may be oriented in-plane perpendicular to the at least one central bar-shaped volume, or under an in-plane angle therewith, such as under an angle of 30-60 degrees, and optionally with at least one second order side branch of the first order side branch.

17. Method of die bonding according to any of embodiments 13-16, wherein the at least one first region is provided centrally on the substrate, such as over an area of 5-50% of the sub- strate, preferably 10-40% of the area, such as 20-35%, and/or wherein the at least one second region is provided eccentric, such as at a side, at a part of a side, or at a corner, such as over an area of 1-15% of the substrate, preferably 2-10% of the area, such as 4-8%.

18. Method of die bonding according to any of embodiments 13-17, wherein the die is at- tached by applying pressure, or by applying heat, or by applying curing, or sintering, or dif- fusion, or a combination thereof.

Claims

Conclusions:

An integrated circuit comprising a substrate (10), on the substrate a fixation layer (20), and on the fixation layer a chip (30), characterized in that the chip fixation layer comprises at least one first region (21) with a first fixation material and at least one second region (22) having a second fastener material different from the first fastener material, wherein the at least one first region is centrally located on the substrate, wherein the at least one second region is located eccentrically, such as on a side, on part of a side, or at a corner.

The integrated circuit of claim 1, wherein the substrate (10) has a first thermal coefficient (TCE1), the chip (30) has a second thermal coefficient (TCE2), the at least a first region (21) has a third thermal coefficient (TCE3), wherein the at least a second region (22) has a fourth thermal coefficient (TCE4), wherein the values of the respective third thermal coefficient (TCE3) and fourth thermal coefficient (TCE4) are each separately between the values of the first thermal coefficient (TCE1) and the second thermal coefficient (TCE2).

The integrated circuit of claim 1 or 2, wherein the at least a first region (21) has a first modulus of elasticity (EM1) and wherein the at least a second region (22) has a second modulus of elasticity (EM2), wherein the first modulus of elasticity (EMI) of the at least a first region is higher than the second modulus of elasticity (EM2) of the at least a second region, and preferably wherein the first modulus of elasticity (EMI) of the at least a first region is lower is then an elastic modulus of the chip, and preferably wherein the second elastic modulus (EM2) of the at least a second region is higher than an elastic modulus of the substrate, the respective elastic moduli being each individually selected from a Young's modulus, a bulk modulus, a viscoelastic modulus, and/or a volumetric modulus.

An integrated circuit according to claim 2 or 3, wherein the value of the fourth thermal coefficient (TCE4) is between the values of the third thermal coefficient (TCE3) and the first thermal coefficient (TCE 1), or wherein the value of the fourth thermal coefficient (TCE4) is between the values of the third thermal coefficient (TCE3) and the second thermal coefficient (TCE2).

Integrated circuit according to any one of claims 1-4, wherein the at least a first region comprises a material with a thermal conductivity of > 50 W/(m*K), preferably > 100 W/(m*K), and/ or, wherein in the at least a second region comprises a material with a thermal conductivity of > 40 W/(m*K), preferably > 50 W/(m*K).

An integrated circuit according to any one of claims 1-5, wherein the area of the first region is 66-99% with respect to the bottom area of the chip, preferably 75-95% thereof, more preferably 80-92% thereof, such as 85-90% thereof, and/or wherein the bottom surface of the chip is 1mm 2 -400mm 2 , preferably 2mm 2 - 100mm 2 , such as 5mm 2 - 60mm 2 .

An integrated circuit according to any one of claims 1-6, wherein a shape of the at least a second region is selected from circular, rectangular, square, L-shaped, and V-shaped, arrays thereof, matrices thereof, and combinations thereof .

An integrated circuit according to any one of claims 1 to 7 wherein the at least one first region comprises a chip fastener selected from heat resistant fasteners, pressure based fasteners, pressureless fasteners, thermosetting fasteners such as epoxy resins, curable fasteners polymer-based fasteners, resin-based fasteners, fibers, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably when the metal is selected from Ag, Au, and/or wherein at least one second region a chip fastener includes a fastener selected from heat-resistant fasteners, pressure-based fasteners, pressureless fasteners, thermosetting fasteners, such as epoxy resins, curable fasteners, polymer-based fasteners, resin-based fasteners materials, fibers, nanoparticles, and combinations thereof, such as comprising at least one metal, preferably when the metal is selected from Ag, Au, and/or wherein the attachment material is lead-free, and/or wherein the attachment layer has a thickness from 5-250 µm, preferably 10-100 µm, more preferably 20-80 µm, such as 30-50 µm.

An integrated circuit according to any one of claims 1-8, wherein the securing layer extends to one side of the chip, preferably to a fillet (27) of maximum 97%, such as 75-95%.

An integrated circuit according to any one of claims 1-9, wherein the chip is an IC with an output power of >50W, such as >100W, such as a Low power chip with 80-100W power, a Medium Power chip with 110- 200W power, or a high power chip with 200-270W power.

An integrated circuit according to any one of claims 1-10, wherein the substrate comprises a material selected from metals, such as copper, and alloys thereof, dielectric materials, such as metal oxides, laminates, such as epoxy-based laminates, epoxy laminates tape substrates, preferably comprising a polymer such as polyimide, ceramic materials comprising fibers such as glass fiber, multiple layers comprising two or more of the above materials, and combinations thereof.

An integrated circuit according to any one of claims 1-11, wherein the chip mounting layer comprises a cavity (28) for receiving the chip, preferably a cavity adapted to the outer dimensions of the chip.

A method of chip attachment, comprising providing a substrate, such as having a first thermal coefficient (TCEI), providing a mounting layer having at least one first region, such as having a third thermal coefficient (TCE3), and at least one second region, such as having a fourth thermal coefficient (TCE4) on the substrate, and attaching a chip, such as having a second thermal coefficient (TCE2), to the mounting layer, preferably wherein the values of the respective third thermal coefficient (TCE3 ) and fourth thermal coefficient (TCE4) each lie separately between the values of the first thermal coefficient (TCE1) and the second thermal coefficient (TCE2), and wherein the value of the fourth thermal coefficient (TCE4) lies between the values of the third thermal coefficient (TCE3) and the first thermal coefficient (TCE 1).

The method of template connection according to claim 13, wherein the at least one first region is provided and then the at least one second region, or vice versa.

An adhesive bonding method according to claim 13 or 14, wherein the at least one first region and the at least one second region are provided separately by liquid metering, or by printing, or by stencilling, or by screen printing, or by deposition, or by preforming, or by a combination thereof.

A chip bonding method according to any one of claims 13-15, wherein the at least one first region is provided in the form of at least one central rod-shaped volume, optionally with at least one first-order side branch, preferably with at least one first-order side branch in each corner, optionally with at least one further first-order side branch on each longitudinal side of the substrate, the first-order side branches in the plane perpendicular to at least one central rod-shaped volume may be oriented, or at an angle thereof, in the plane, such as at an angle of 30-60 degrees, and optionally with at least one second order branch of the first order branch.

A method of chip bonding according to any one of claims 13-16, wherein at least one first region is applied centrally on the substrate, such as over an area of 5-50% of the substrate, preferably 10-40% of the area, such as 20-35%, and/or wherein at least one second area is provided eccentrically, such as on a side, on a part of a side, or at an angle, such as over an area of 1-15% of the substrate, preferably 2-10% of the surface, such as 4-8%.

A chip bonding method according to any one of claims 13 to 17, wherein the chip is attached by applying pressure, or by applying heat, or by applying curing, or by sintering, or by diffusion, or by a combination thereof.