MXPA97003405A - Pixel data correction device for use with a mirror provision action - Google Patents

Abstract

The present invention relates to an apparatus for use with an array of powered mirrors of M x N driven mirrors, having the array of driven mirrors M x N of driven mirrors, for correcting the value of an input pixel using a predetermined corrected value of its corresponding driven mirror, comprising: a means for correcting in gamma the value of the input pixel, a means for storing a set of corrected values for the M x N driven mirrors, wherein the set of corrected values represent directions and inclined angles of the M x N driven mirrors, a means for generating address data representing the location of the input pixel, a means responsive to the address data generated for the input pixel, to retrieve a corresponding corrected value from the corrected values of the stored game, where the corresponding corrected value consists of S-bits and S is an integer greater than 1, being a more significant bit in the S bit value corrected one bit denoting whether a driven mirror corresponding to the input pixel is tilted in a positive direction or in a negative direction, and the remaining bits denote the angle of a tilted driven mirror; means for correcting the gamma corrected value of the input pixel using the corresponding corrected value, to thereby provide a corrected output pixel value, wherein the means for correcting the gamma corrected value includes: a means for performing an operation or exclusive for the most significant bit of the value of S-corrected bits and each of the remaining bits, respectively, to obtain a corresponding number of operated or exclusive data, and a means of operation, if the most significant bit is a first level logic that indicates that the driven mirror that corresponds to the input pixel is tilted in a positive direction, to subtract both the data operated or exclusive of (S-1) -bitios as the most significant bit of the value corrected in gamma, in order to obtain the output pixel value and, if the most significant bit is a second logical level that indicates that the driven mirror is tilted in a negative direction, to add both the operated or exclusive data of (s-1) -bitio and the most significant bit to the value corrected in gamma, in order to derive the pixel value of the

Description

PIXEL DATA CORRECTION DEVICE FOR USE WITH A DISP MIRRORED SITION OF MIRRORS TECHNICAL FIELD OF THE INVENTION The present invention relates to a pixel data correction apparatus for use with an activated mirror array (AMA) included in an optical projection system; and, more particularly, with an apparatus for correcting a value of each of the input pixels using a predetermined value-corrected from its corresponding powered mirror.

PREVIOUS TECHNIQUE Among the various video display systems available in the field, an optical projection system is known to be capable of providing high quality images on a large scale. In said orthodontic projection system, the light of a lamp is uniformly illuminated towards, eg, an arrangement of mirrors M x N. The arrangement of mirrors M x N is mounted in an array of actuators that includes a corresponding number. say, M x N, of actuators so that each of the mirrors is coupled with each of the actuators to thereby form an AMA wherein each of the driven mirrors corresponds to a pixel. The actuators can be made of an azable electrodesol material such as a Diezoelectric material or an electrorestrictive material that deforms in response to a supply voltage applied to it. The reflected light beam of each of the mirrors is incident on an opening of a baffle. Applying an electrical signal to each of the actuators, the relative position of each of the mirrors to the incident light beam is altered, thus causing a deviation in the optical path of the reflected beam from each of the mirrors. . As the optical path of each of the reflected beams is broken, the amount of light reflected from each of the mirrors passing through the aperture is changed, thereby modulating the beam intensity. Beams modulated through the aperture are transmitted to a projection screen through an appropriate optical device such as a projection lens, so as to display an image thereon. In the optical projection system that uses an AMA, the mirror to reflect the beam of light in each of the mirrors operated in the arrangement must be parallel to the surface of a panel on which the AMA is mounted when it is not applied to the - same electrical signal. However, some of the mirrors may not be parallel to the surface, preventing mirrors from accurately reflecting the beam of light, which, in turn, may lead to deterioration in image quality.

EXHIBITION OF THE INVENTION Therefore, a primary object of the present invention The purpose of this invention is to provide an apparatus, for use with a powered mirror arrangement included in an optical projection system, capable of correcting a value of a corresponding input pixel to a mirror that is not aligned in parallel with the surface of the mirror. a panel on which the layout is mounted. In accordance with the present invention, an apparatus is provided, for use with an acted mirror arrangement included in an optical projection system, for correcting the value of an input pixel using a predetermined corregid value of its corresponding actuated mirror. within M x N driven mirrors included in the arrangement, where M and N are integers, comprising: an element for correcting in gamma the value of the input pixel; an element for storing a predetermined set of corrected values for the driven mirrors M x N; an element for generating address data representing the location of the input pixel; an element, which responds to the address data generated for the input oixel, to remove a predetermined corrected value from the corrected values to the predetermined stored game; and an element to correct the gamma corrected value of the input pixel using the corrected value removed in order to provide a corrected value of the output pixel.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention, together with the foregoing objects and advantages and others will become apparent from the following description of the preferred embodiments provided in conjunction with the accompanying drawings, wherein: Figure 1 shows a block diagram illustrating a novel pixel data correction apparatus used with an AMA in accordance with the present invention; and Figure 2 provides a detailed circuit diagram of the third correction circuit shown in Figure 1.

MODES FOR CARRYING OUT THE INVENTION In Figure 1, a block diagram of the novel pixel data correction apparatus 100 in accordance with the present invention for use with an AMA 200 in an optical projection system is illustrated. The pixel data correction apparatus 100 comprises a analog-to-digital conversion (ADC) circuit 10, a first, a second and a third correction circuit 20, 40 and 50 and a steering generator 30. An analog video input signal of M x N, e.g., 640 x 480, pixels is applied to the ADC circuit 10 which is adapted to convert each analog video signal input to corresponding digital video pixel data. S, v.gr., 8, bits using a conventional ADC algorithm, where M, N and S are integers. For the sake of simplicity, the following description The apparatus of the invention will be provided with respect to the 8-bit digital video pixel data. The converted 8-bit digital pixel pixel data of the ADC circuit 10 is then fed to the first correction circuit 20. In the first correction circuit 20, in response to 8-bit digital video pixel data of the ADC circuit 10, a corresponding 8-bit corrected pixel data, e.g., (RS0-RS7), is read from a set of pixel data corrected orevi mind stored in a read only memory (ROM) (not shown) thereof. The set of corrected pixel data previously stored in the ROM can be derived using a somewhat conventional gamma correction rate well known in the art. The 8-bit gamma corrected pixel data (RS0-RS7) read from the ROM of the first correction circuit 20 is then coupled to the correction circuit 50 in a parallel fashion. Meanwhile, as shown in Figure 1, synchronization signals one horizontal and one vertical (SYNC), Hsync and Vsync, provided from a SYNC signal separator (not shown) are applied to the address generator 30, using the signals Horizontal and vertical SYNC, Hsync and Vsync, the address generator 30 serves to generate P, eg, 19, bit direction data, eg, (A0-A18), which represents the location of the pi input xel applied to ADC circuit 10, where P is a positive integer. Again, the following description will be provided with respect to the 19-bit address data for of simplicity. The 19-bit address data (A0-A18) for the input footer generated in the address generator 30 is then supplied to the second correction circuit 40. In response to the 19-bit address data (A0-A18) for the input pixel supplied from the address generator 30, the second correction circuit 40 serves to remove the corrected value of 8 bits, e.g., ( RC0-RC7), for a mirror that corresponds to the input pixel of a set of corrected values for M x N previously activated mirrors store two in a ROM thereof. The set of corrected values for M x N previously operated mirrors stored in the ROM can be obtained through the use of a known angle-angle calculation equipment. In each of the corrected values included in the game, a more significant bit (MSB), eg, RC7, of them represents whether their corresponding powered mirror is tilted in a positive direction or in a negative direction, while the rest, e.g., (RC0-RC6) denotes an angle of a substantially slanted driven mirror. The set of corrected values has a scale of 00000000 to 11111111, where the 8-bit corrected value of 00000000 represents that a driven mirror is in a normal state, i.e. it is aligned in parallel with the surface of a panel in the one that is mounted the AMA. Subsequently, the pixei data corrected in 8-bit gamma (RS0-RS7) output from the first correction circuit 20 and the corr value.

The corresponding 8-bit clock (RC0-RC7) removed from the second correction block 40 is simultaneously coupled to the third correction circuit 50 in a parallel fashion. In the third correction circuit 50, the correction operation of the pixel data corrected in 8-bit gamma (RS0-RS7) for the input pixel its inserted in the first correction circuit 2 is performed using the corrected value of 8 bits ( RC0-RC7) for the corresponding powered mirror provided by the second correction circuit 40. Turning now to Figure 2, a detailed circuit diagram of the third correction circuit 50 shown in Figure 1 is illustrated. The third correction circuit 50 comprises a signal determiner 52, a pixel data corrector 54 and a limiter 56 of carrier digit. As shown, the 8-bit corrected value (RC0-RC7 for the driven mirror corresponding to the input port provided from the second correction circuit 40 is coupled to the signal detector 52 in a parallel fashion. , which includes a plurality of exclusive 0R gates (EX), eg, 52a to 52g, performs exclusive 0R operation for an M &B, that is, rC7, of the corrected value of 8 bits coupled to it and the rest , that is, corrected value of 7 bits (RC0, RC6) respectively Specifically, the inputs to each of the gates 52a to 52g EX-OR are MSB and RC7 and one corresponding bit of the rest (RC0-RC6) except the MSB RC7 in the corrected value of bits As is well known in the industry, one output from each of the gates 52a to 52g EX-OR, Xi, can be represented as follows: Xi RCi $ RC7 Ec. (1) where i is an integer used as an index of each of the EX-OR gates. Next, an output from each of the registers 52a to 52g ER-OR, Xi, is provided to the pixel data corrector 54 including T number, eg. 2, full adders (FAs), 54a and 54b, which are adapted to provide S, is, the output pixel data corrected by 8 bits, eg, SO to S7, where T is a positive integer . As shown in FIG. 2, the inputs to the FA 54a are K, eg, 4, bit corrected bit data, eg, (RS0-RS3), provided from the first correction circuit 20. K, that is, 4, corrected values operated by bit exclusive OR, eg, Xo to X3, supplied from gates 52a to 52d EX-OR, and MSB RC7 of the corrected value of 8 bits, as a first input bearer bit, eg, Clin, directly applied to the second correction circuit 40, where K is a positive enter less than S. On the other hand, the inputs to the FA 54b are K, i.e. , pixel data corrected in bit, v.gr., (RS4-RS7), proportion two from the first correction circuit 20, L. v, gr., 3, corrected values operated by bit exclusive OR, eg, X4 through X6, supplied from gates 52e through 52g EX-OR, MSB RC7 directly applied to the second correction circuit 40, and one of the outputs of the FA 54a, eg, a first output bearer bit, eg, Clout, as a second input bearer bit, v.gr ., C2in, wherein the first output bearer bit Clout represents a bearer bit produced from an NSB, that is, S3, of outputs of the FA 54a and L is a positive integer smaller than K. In a preferred embodiment of the present invention, c gives one of the outputs of the FAs, 54a, 54b, which performs the addition operations for the inputs applied to them, as is well known in the field, eg, SO, can be defined as : SO (XO? RSO) • Cl in Ec. (2) The remainder, ie, SI to S7, of the outputs of the FAs 54a and 54b, can be derived in a similar manner as explained above since the agorhythms processed therein are substantially identical to Eq. (2) except that their respective entries are different from each other. As can be seen from the Ees (1) and (2), if the MSB RC7 to each of the gates EX-OR, 52a, 54g, and to the Fa 54a is a logical elevated node, that is, the actuating mirror Correspondingly, it is inclined in a positive direction, the FAS, 54a and 54b, carry out the addition operations for the incoming These are applied to them in order to provide 8-bit corrected output pixel data, SO to S7, which is derived using the 8-bit corrected value (RC0-RC7) corresponding to the inclined angle of the actuator mirror. In this case, the corrected 8-bit output pixel dat, SO to S7, can be obtained by subtly subtracting the corrected values operated from the 7-bit exclusive OR, Xo to X6, supplied from the EX-OR gates, 52a to 52g, and the MSB RC7 directly applied from the second correction circuit 40 from the corrected 8-bit pixel data (RS0-RS7) provided from the first correction circuit 20, respectively. On the other hand, if the MSB RC7 to each of the EX-OR comps, 52a to 52g, and the FA 54a are at a low logic level, ie the corresponding actuator mirror is tilted in a negative direction, the FAs 54a and 54b perform sum operations for the inputs applied thereto to thereby provide 8-bit corrected output pixel data, SO to S7, which is obtained using the 8-bit corrected value (CRO RC7) corresponding to the angle inclined of the actuator mirror. In this case, the corrected output pixel data of 8 bits, SO to S7, can be obtained by adding substantially the correct values operated by 7-bit exclusive 0R, X0 to X6, from each of the EX-OR gates, 52a at 52g, and from the MSB RC7 of the second correction circuit 40 to the 8-bit corrected pixel data (RS0-RS7) from the first correction circuit 20, respectively. mind . Next, the output pixel data corrected from 8 bits SO to S7 and the second output carrier bit C2out of the -FAs, 54a, 54b are coupled to the digital limiter 56 that is adapted to limit the output pixel data. extra corrections that are not included within a predefined pixel data scale, wherein the second C2out bit carrier of sa 1 da represents a generator bearer bit of an MSB, i.e., S7, of the outputs of the FA 54b. In other words, the limiter 56 d_i such a carrier serves to generate limited corrected output pixel data of 8 bits that are adapted to drive each of the actuator mirrors included in the provided panel - with the AMA 200 within a scale of supply voltage pr determined, e.g., OV at 30V, wherein the supply voltages of OV and 30V represent the 8-bit pixel data of 00000000 and 11111111, respectively. As shown in Figure 2, the digital carrier limiter 56 includes an EX-OR gate 56a, and NAND gate 56b, a plurality of gates 0R, e.g., 54c to 56j, and a plurality of AND components, v. gr., 56k to 56r. Specifically, those sent to the EX-OR gate 56a and the MSB RC7 of the 8-bit corrected value of the first correction circuit 20 and the second output carrier bit C2out of the FA 54b. The output of the gate -EX-OR 56a can be derived in a similar manner as described in the EX-OR gates 52a to 54g.

Subsequently, the output of the gate 56a EX-OR is provided to each of the gates OR, 56c to 56j, and to the gate NAND 56b. Specifically, the inputs to each - one of the gates OR, 56c to 56f, are the output operated by explusive OR from gate EX-OR 56a and one of the output pixel data corrected, SO to S3, of FA 54a; and, the inputs to each of the gates or, 56g to 56j, are the output-operated by exclusive OR from gate EX-OR 56a and one of the output pixel data corrected from 4 bits, S4 to S7, of the FA 54b. As is well known in the industry, each of the OR-doors, 56c to 56j, produces a high logic if all inputs to them are not at a low logical level; and, for the rest, it produces a low logic. On the other hand, the inputs to gate NAND 56b are the output operated by exclusive OR of gate EX-OR -56a and MSB RC7 of second correction circuit 20. The output of the NAND gate 56b, as is well known in the industry, is a high logic if all the inputs to it are not at a high logical level.; and, a low logic level if all the inputs to it are at a high logical level. The output of each of the gates OR, 56c to 56j is coupled to an input port of each of the AND gates, 56k to 56r, while the output of the NAN gate 56b is coupled to another input gate of the gates. each of the co doors AND, 56k to 56r. As is well known in the industry, each one of the AND gates, 56k to 56r, produces a high logic if all the inputs to them are at a high logical level; and for the rest, it generates a low logic. The pixel data corrected output of 8 bits thus corrected, eg, (R00-R07), is provided to a column impeller (not shown) included in the AMA 200 for driving the actuator mirror corresponding to the pixel. of entry. As it can be seen from the above, if the inputs are, both the MSB RC7 and the second output bearer bit C2out, the EX-OR gate 56a and the NAND gate 56b are of a low logic or high logic, the output pixel data corrected d 8 bits (R00-R07) of the AND gates, 56k to 56r, is identical to output pixel data converted from 8 bits, SO to S7, generated in the FAs, 54a and 54b. But, if the MSB RC7 and the second output bit C2out applied to the EX-OR gate 56a and the gate NAND 56b are a high logic and a low logic, respectively, the output pixel data corrected for 8 bits (R00-R07) of the AND gates, 56k to 56r, is 00000000; and, if the MSB RC7 and the second output bearer bit C2out to gate EX-OR 56a and gate NAND 56b are of low logic and high logic, respectively, the output pixel data corrected is 8 bits. (R00-R07) of the AND gates, 56k to 56r, is 11111111. As shown above, therefore, the pixel data correction apparatus of the invention is capable of correcting the value of each pixel of each pixel. entry using a value corrected default of your corresponding powered mirror - in an arrangement of M x N powered mirrors, thereby improving the quality of the image. Although the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (3)

CLAIMS:

1. - An apparatus, for use with an array of M x N powered mirrors (AMA) included in an optical projection system, for correcting the value of an input pixel using a predetermined corrected value of its corresponding acted mirror, in where M and N are integers, comprising: an element to correct in gamma the value of the input pixel; an element for storing a predetermined set of corrected values for the M x N powered mirrors; an element for generating address data representing the location of the input pixel; an element, responsive to the address data generated for the input pixel, to remove a predetermined corrected value from the corrected values of the predetermined set ali; and an element to correct the corrected value in gamma of the input oixel that uses the corrected value removed for in this way provides a corrected output pixel value

2. - The apparatus of claim 1, wherein each of the corrected values included in the predetermined set consists of 8 bits, and a most significant bit (MSB) in the corrected 8-bit value is a bit denoting whether a Acting mirror corresponding to the input pixel is inclined in a positive direction or in a negative direction.

3. - The apparatus of claim 2, further comprising an element for limiting the output pixel value if it is not within a predefined pixel value scale.