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MX2016003484A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents

Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Info

Publication number
MX2016003484A
MX2016003484A MX2016003484A MX2016003484A MX2016003484A MX 2016003484 A MX2016003484 A MX 2016003484A MX 2016003484 A MX2016003484 A MX 2016003484A MX 2016003484 A MX2016003484 A MX 2016003484A MX 2016003484 A MX2016003484 A MX 2016003484A
Authority
MX
Mexico
Prior art keywords
parity
data processing
ldpc
bits
matrix
Prior art date
Application number
MX2016003484A
Other languages
English (en)
Inventor
Yuji Shinohara
Makiko Yamamoto
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of MX2016003484A publication Critical patent/MX2016003484A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

Esta tecnología pertenece a un dispositivo de procesamiento de datos y a un método de procesamiento de datos que hacen posible proporcionar un código de LDPC que tiene una buena tasa de error. Un codificador de LDPC codifica utilizando un código de LDPC que tiene una longitud de código de 16,200 bits y una tasa de código de 12/15. El código de LDPC contiene bits de información y bits de paridad, y la matriz de paridad-comprobación (H) para el código de LDPC comprende una sección de matriz de información que corresponde a los bits de paridad. La sección de matriz de información de la matriz de comprobación de paridad (H) se representa por una tabla de valores iniciales de matriz de comprobación de paridad que representa la posición de un elemento de la sección de matriz de información cada 360 columnas. Esta tecnología puede aplicarse cuando se realice codificación del LDPC y descodificación de LDPC.
MX2016003484A 2013-09-24 2014-09-12 Dispositivo de procesamiento de datos y metodo de procesamiento de datos. MX2016003484A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013197536 2013-09-24
PCT/JP2014/074242 WO2015045912A1 (ja) 2013-09-24 2014-09-12 データ処理装置、及びデータ処理方法

Publications (1)

Publication Number Publication Date
MX2016003484A true MX2016003484A (es) 2016-07-06

Family

ID=52743054

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2016003484A MX2016003484A (es) 2013-09-24 2014-09-12 Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Country Status (8)

Country Link
US (1) US20160126978A1 (es)
EP (1) EP3051708A4 (es)
JP (1) JPWO2015045912A1 (es)
KR (1) KR20160060027A (es)
CN (1) CN105556858A (es)
CA (1) CA2924027A1 (es)
MX (1) MX2016003484A (es)
WO (1) WO2015045912A1 (es)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6553975B2 (ja) * 2015-08-03 2019-07-31 日本放送協会 符号化装置、復号装置、半導体チップ、及びプログラム

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2454195A (en) * 2007-10-30 2009-05-06 Sony Corp Address generation polynomial and permutation matrix for DVB-T2 16k OFDM sub-carrier mode interleaver
JP4224777B2 (ja) 2003-05-13 2009-02-18 ソニー株式会社 復号方法および復号装置、並びにプログラム
JP4688841B2 (ja) * 2007-03-20 2011-05-25 日本放送協会 符号化器及び復号器、並びに送信装置及び受信装置
TWI410055B (zh) * 2007-11-26 2013-09-21 Sony Corp Data processing device, data processing method and program product for performing data processing method on computer
TWI497920B (zh) * 2007-11-26 2015-08-21 Sony Corp Data processing device and data processing method
EP2093887B1 (en) * 2008-02-18 2013-08-28 Samsung Electronics Co., Ltd. Apparatus and method for channel encoding and decoding in a communication system using low-density parity-check codes
JP5500379B2 (ja) * 2010-09-03 2014-05-21 ソニー株式会社 データ処理装置、及びデータ処理方法
JP5664919B2 (ja) * 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
EP2560311A1 (en) * 2011-08-17 2013-02-20 Panasonic Corporation Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes
EP3051707A4 (en) * 2013-09-26 2017-06-21 Sony Corporation Data processing device and data processing method

Also Published As

Publication number Publication date
EP3051708A1 (en) 2016-08-03
WO2015045912A1 (ja) 2015-04-02
US20160126978A1 (en) 2016-05-05
EP3051708A4 (en) 2017-05-31
JPWO2015045912A1 (ja) 2017-03-09
KR20160060027A (ko) 2016-05-27
CA2924027A1 (en) 2015-04-02
CN105556858A (zh) 2016-05-04

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