Nothing Special   »   [go: up one dir, main page]

Yuan et al., 2016 - Google Patents

A 70 mW 25 Gb/s quarter-rate SerDes transmitter and receiver chipset with 40 dB of equalization in 65 nm CMOS technology

Yuan et al., 2016

Document ID
3895341622324173151
Author
Yuan S
Wu L
Wang Z
Zheng X
Zhang C
Wang Z
Publication year
Publication venue
IEEE Transactions on Circuits and Systems I: Regular Papers

External Links

Snippet

A 25 Gb/s transmitter (TX) and receiver (RX) chipset designed in a 65 nm CMOS technology is presented. The proposed quarter-rate TX architecture with divider-less clock generation can not only guarantee the timing constraint for the highest-speed serialization, but also …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0282—Provision for current-mode coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults; Receiver end arrangements for detecting or overcoming line faults
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/01—Equalisers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Similar Documents

Publication Publication Date Title
Roshan-Zamir et al. A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR-and IIR-tap adaptation in 65-nm CMOS
Yuan et al. A 70 mW 25 Gb/s quarter-rate SerDes transmitter and receiver chipset with 40 dB of equalization in 65 nm CMOS technology
Zhang et al. A 28 Gb/s multistandard serial link transceiver for backplane applications in 28 nm CMOS
Krupnik et al. 112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels
Wong et al. A 27-mW 3.6-gb/s I/O transceiver
Kim et al. A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET
Han et al. Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology
Chen et al. A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology
Beukema et al. A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
Bassi et al. A high-swing 45 Gb/s hybrid voltage and current-mode PAM-4 transmitter in 28 nm CMOS FDSOI
Musah et al. A 4–32 Gb/s bidirectional link with 3-tap FFE/6-tap DFE and collaborative CDR in 22 nm CMOS
Ibrahim et al. Low-power CMOS equalizer design for 20-Gb/s systems
Zheng et al. A 40-Gb/s quarter-rate SerDes transmitter and receiver chipset in 65-nm CMOS
US9178563B2 (en) Voltage regulator for a serializer/deserializer communication application
Kocaman et al. A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5 tap DFE and a 4 tap transmit FFE in 28 nm CMOS
Kim et al. A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method
Shahramian et al. Edge-Based Adaptation for a 1 IIR+ 1 Discrete-Time Tap DFE Converging in $5~\mu $ s
Liao et al. A 40 Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
Lin et al. ADC-DSP-based 10-to-112-Gb/s multi-standard receiver in 7-nm FinFET
Cui et al. A dual-channel 23-Gbps CMOS transmitter/receiver chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK optical transmission
Jeong et al. A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-${\rm G} _ {\rm m} $ Bias
Peng et al. A 112-Gb/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS
Wang et al. A 56-Gbps PAM-4 wireline receiver with 4-tap direct DFE employing dynamic CML comparators in 65 nm CMOS
Erett et al. A 0.5–16.3 Gbps multi-standard serial transceiver with 219 mW/channel in 16-nm FinFET
Huang et al. A 80 mW 40 Gb/s transmitter with automatic serializing time window search and 2-tap pre-emphasis in 65 nm CMOS technology