Dong et al., 2021 - Google Patents
Hao: Hardware-aware neural architecture optimization for efficient inferenceDong et al., 2021
View PDF- Document ID
- 3662679487013120128
- Author
- Dong Z
- Gao Y
- Huang Q
- Wawrzynek J
- So H
- Keutzer K
- Publication year
- Publication venue
- 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
External Links
Snippet
Automatic algorithm-hardware co-design for DNN has shown great success in improving the performance of DNNs on FPGAs. However, this process remains challenging due to the intractable search space of neural network architectures and hardware accelerator …
- 230000001537 neural 0 title abstract description 60
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06Q—DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/04—Forecasting or optimisation, e.g. linear programming, "travelling salesman problem" or "cutting stock problem"
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F19/00—Digital computing or data processing equipment or methods, specially adapted for specific applications
- G06F19/10—Bioinformatics, i.e. methods or systems for genetic or protein-related data processing in computational molecular biology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Dong et al. | Hao: Hardware-aware neural architecture optimization for efficient inference | |
Blott et al. | FINN-R: An end-to-end deep-learning framework for fast exploration of quantized neural networks | |
Su et al. | Redundancy-reduced mobilenet acceleration on reconfigurable logic for imagenet classification | |
Xu et al. | AutoDNNchip: An automated DNN chip predictor and builder for both FPGAs and ASICs | |
US10656962B2 (en) | Accelerate deep neural network in an FPGA | |
Yang et al. | A fully onchip binarized convolutional neural network fpga impelmentation with accurate inference | |
Li et al. | FLASH: F ast Neura l A rchitecture S earch with H ardware Optimization | |
Ke et al. | Nnest: Early-stage design space exploration tool for neural network inference accelerators | |
Tao et al. | Challenges in energy-efficient deep neural network training with FPGA | |
Reggiani et al. | Pareto optimal design space exploration for accelerated CNN on FPGA | |
Ayachi et al. | Optimizing neural networks for efficient FPGA implementation: A survey | |
Jahanshahi | Tinycnn: A tiny modular CNN accelerator for embedded FPGA | |
Gong et al. | N3h-core: Neuron-designed neural network accelerator via fpga-based heterogeneous computing cores | |
Vo et al. | A deep learning accelerator based on a streaming architecture for binary neural networks | |
Sateesan et al. | A survey of algorithmic and hardware optimization techniques for vision convolutional neural networks on FPGAs | |
Baharani et al. | Deepdive: An integrative algorithm/architecture co-design for deep separable convolutional neural networks | |
Reggiani et al. | Mix-gemm: An efficient hw-sw architecture for mixed-precision quantized deep neural networks inference on edge devices | |
Sivasankari et al. | High-throughput and power-efficient convolutional neural network using one-pass processing elements | |
Shawahna et al. | FxP-QNet: a post-training quantizer for the design of mixed low-precision DNNs with dynamic fixed-point representation | |
Mazouz et al. | Automated CNN back-propagation pipeline generation for FPGA online training | |
Garbay et al. | Cnn inference costs estimation on microcontrollers: the est primitive-based model | |
Liu et al. | An efficient fpga-based depthwise separable convolutional neural network accelerator with hardware pruning | |
Sait et al. | Optimization of FPGA-based CNN accelerators using metaheuristics | |
Kulkarni et al. | Hybrid optimization for DNN model compression and inference acceleration | |
León-Vega et al. | Automatic Generation of Resource and Accuracy Configurable Processing Elements |