Nothing Special   »   [go: up one dir, main page]

Dong et al., 2017 - Google Patents

Wafer yield prediction using derived spatial variables

Dong et al., 2017

View PDF
Document ID
3582050195405289997
Author
Dong H
Chen N
Wang K
Publication year
Publication venue
Quality and Reliability Engineering International

External Links

Snippet

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use …
Continue reading at www2.ie.tsinghua.edu.cn (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K9/00Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
    • G06K9/62Methods or arrangements for recognition using electronic means
    • G06K9/6267Classification techniques
    • G06K9/6268Classification techniques relating to the classification paradigm, e.g. parametric or non-parametric approaches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass
    • G06N99/005Learning machines, i.e. computer in which a programme is changed according to experience gained by the machine itself during a complete run
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K9/00Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
    • G06K9/62Methods or arrangements for recognition using electronic means
    • G06K9/6217Design or setup of recognition systems and techniques; Extraction of features in feature space; Clustering techniques; Blind source separation

Similar Documents

Publication Publication Date Title
US20240003968A1 (en) Integrated circuit profiling and anomaly detection
US10657638B2 (en) Wafer map pattern detection based on supervised machine learning
Dong et al. Wafer yield prediction using derived spatial variables
US10628935B2 (en) Method and system for identifying defects of integrated circuits
TWI663667B (en) Method for adaptive sampling in examining an object and system thereof
Madkour et al. Hotspot detection using machine learning
Fan et al. Fault diagnosis of wafer acceptance test and chip probing between front-end-of-line and back-end-of-line processes
Kim et al. A generalised uncertain decision tree for defect classification of multiple wafer maps
Liu et al. Fine-grained adaptive testing based on quality prediction
Hwang et al. Shifting artificial data to detect system failures
Zhang et al. WDP-BNN: Efficient wafer defect pattern classification via binarized neural network
Li et al. An Orthogonal Wavelet Transform‐Based K‐Nearest Neighbor Algorithm to Detect Faults in Bearings
Huang et al. LAIDAR: Learning for accuracy and ideal diagnostic resolution
Alqudah et al. A systemic comparison between using augmented data and synthetic data as means of enhancing wafermap defect classification
CN108073674B (en) Early development of fault identification database for system defects in integrated circuit chips
Zhang et al. A workflow of hotspot prediction based on semi-supervised machine learning methodology
Fang et al. Diagnosis outcome preview through learning
Yeh et al. Prediction of the test yield of future integrated circuits through the deductive estimation method
US8190391B2 (en) Determining die performance by incorporating neighboring die performance metrics
Aye et al. Data driven framework for degraded pogo pin detection in semiconductor manufacturing
Yu et al. Center Loss Guided Prototypical Networks for Unbalance Few‐Shot Industrial Fault Diagnosis
US10095826B2 (en) Feed-forward for silicon inspections (DFM2CFM : design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM : silicon to design) guided by marker classification, sampling, and higher dimensional analysis
Oviya et al. Advanced Semiconductor Classifiers Using Machine Learning Techniques
Jourdan et al. A Nearest Neighbor-Based Concept Drift Detection Strategy for Reliable Tool Condition Monitoring
Cheng et al. Improving test quality of memory chips by a decision tree-based screening method