Lu et al., 2016 - Google Patents
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applicationsLu et al., 2016
- Document ID
- 3511658693225318952
- Author
- Lu G
- Wang Y
- Cao J
- Jia S
- Zhang X
- Publication year
- Publication venue
- 2016 IEEE International Symposium on Circuits and Systems (ISCAS)
External Links
Snippet
This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of …
- 230000036039 immunity 0 title abstract description 11
Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/335—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with more than two electrodes and exhibiting avalanche effect
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Semenov et al. | ESD protection device and circuit design for advanced CMOS technologies | |
Meng et al. | Novel decoupling capacitor designs for sub-90nm CMOS technology | |
Gossner et al. | Simulation methods for ESD protection development | |
Altolaguirre et al. | Power-rail ESD clamp circuit with diode-string ESD detection to overcome the gate leakage current in a 40-nm CMOS process | |
CN104867910A (en) | Electrostatic discharge protection circuit and semiconductor device | |
Li et al. | Compact modeling of on-chip ESD protection devices using Verilog-A | |
Di Sarro et al. | A scalable SCR compact model for ESD circuit simulation | |
Beebe | Characterization, modeling, and design of ESD protection circuits | |
Do et al. | A novel low dynamic resistance dual-directional SCR with high holding voltage for 12 V applications | |
Lu et al. | Transient and static hybrid-triggered active clamp design for power-rail ESD protection | |
Wang et al. | Design of power-rail ESD clamp circuit with ultra-low standby leakage current in nanoscale CMOS technology | |
EP2849228A2 (en) | Bigfet ESD protection that is robust against the first peak of a system-level pulse | |
Song et al. | Robust silicon-controlled rectifier with high-holding voltage for on-chip electrostatic protection | |
Zhou et al. | Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models | |
Yeh et al. | Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection | |
Lu et al. | A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications | |
Shen et al. | Area-efficient power-rail ESD clamp circuit with false-trigger immunity in 28nm CMOS process | |
Yeh et al. | Resistor-less design of power-rail ESD clamp circuit in nanoscale CMOS technology | |
Ker et al. | Design of high-voltage-tolerant ESD protection circuit in low-voltage CMOS processes | |
Yeh et al. | Power-rail ESD clamp circuit with ultralow standby leakage current and high area efficiency in nanometer CMOS technology | |
Wang et al. | Design of 2$\times $ VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology | |
Shen et al. | A novel low-leakage ESD power clamp circuit with adjustable transient response time | |
Altolaguirre et al. | Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology | |
Yang et al. | Low leakage 3× VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process | |
Lu et al. | Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process |