Kamali et al., 2016 - Google Patents
AdapNoC: A fast and flexible FPGA-based NoC simulatorKamali et al., 2016
View PDF- Document ID
- 3168842148083500580
- Author
- Kamali H
- Hessabi S
- Publication year
- Publication venue
- 2016 26th international conference on field programmable logic and applications (FPL)
External Links
Snippet
Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC …
- 230000003044 adaptive 0 abstract description 28
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5027—Logic emulation using reprogrammable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding through a switch fabric
- H04L49/253—Connections establishment or release between ports
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Kamali et al. | AdapNoC: A fast and flexible FPGA-based NoC simulator | |
Wang et al. | DART: A programmable architecture for NoC simulation on FPGAs | |
Genko et al. | A complete network-on-chip emulation framework | |
Wolkotte et al. | Fast, accurate and detailed NoC simulations | |
Monemi et al. | ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform | |
Kapre et al. | Hoplite: A deflection-routed directional torus noc for fpgas | |
Kamali et al. | DuCNoC: A high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architecture | |
Van Chu et al. | Ultra-fast NoC emulation on a single FPGA | |
Abdelfattah et al. | Design and applications for embedded networks-on-chip on FPGAs | |
Boutros et al. | RAD-Sim: Rapid architecture exploration for novel reconfigurable acceleration devices | |
Prasad et al. | YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs | |
Abdelfattah et al. | LYNX: CAD for FPGA-based networks-on-chip | |
Prasad et al. | FPGA friendly NoC simulation acceleration framework employing the hard blocks | |
Parane et al. | LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA | |
Prabhu Prasad et al. | An efficient FPGA-based network-on-chip simulation framework utilizing the hard blocks | |
Parane et al. | FPGA based NoC simulation acceleration framework supporting adaptive routing | |
Parane et al. | YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs | |
Sangeetha et al. | Trace-driven simulation and design space exploration of network-on-chip topologies on FPGA | |
Parane et al. | P-noc: performance evaluation and design space exploration of nocs for chip multiprocessor architecture using fpga | |
Zhu et al. | BiLink: A high performance NoC router architecture using bi-directional link with double data rate | |
Liu et al. | A NoC emulation/verification framework | |
Marvasti et al. | An analysis of hypermesh nocs in fpgas | |
Ijaz et al. | Implementation of NoC on FPGA with area and power optimization | |
Zhang et al. | Software/hardware hybrid network-on-chip simulation on FPGA | |
Ahmed et al. | FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems |