Persky et al., 1976 - Google Patents
LTX-A system for the directed automatic design of LSI circuitsPersky et al., 1976
View PDF- Document ID
- 3061309413398042589
- Author
- Persky G
- Deutsch D
- Schweikert D
- Publication year
- Publication venue
- Proceedings of the 13th Design Automation Conference
External Links
Snippet
LTX is a minicomputer-based design system for large-scale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms …
- 230000002452 interceptive 0 abstract description 17
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/20—Handling natural language data
- G06F17/21—Text processing
- G06F17/24—Editing, e.g. insert/delete
- G06F17/245—Tables; Ruled lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/74—Symbolic schematics
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Persky et al. | LTX-A system for the directed automatic design of LSI circuits | |
Doll et al. | Iterative placement improvement by network flow methods | |
Sechen et al. | The TimberWolf placement and routing package | |
Kleinhans et al. | GORDIAN: VLSI placement by quadratic programming and slicing optimization | |
Soukup | Circuit layout | |
Ousterhout et al. | The magic VLSI layout system | |
JP4679029B2 (en) | System for partitioning, placing and routing integrated circuits | |
Preas et al. | Methods for hierarchical automatic layout of custom LSI circuit masks | |
US20020087940A1 (en) | Method for designing large standard-cell based integrated circuits | |
Dai | Hierarchical placement and floorplanning in BEAR | |
US20020087939A1 (en) | Method for designing large standard-cell based integrated circuits | |
Niessen | Hierarchical design methodologies and tools for VLSI chips | |
Cho et al. | FLOSS: An approach to automated layout for high-volume designs | |
Schweikert | A 2-dimensional placement algorithm for the layout of electrical circuits | |
Kurdahi et al. | PLEST: A program for area estimation of VLSI integrated circuits | |
Sudo et al. | CAD systems for VLSI in Japan | |
Dutt et al. | Design synthesis and silicon compilation | |
Trick et al. | Lassie: Structure to layout for behavioral synthesis tools | |
Beke et al. | CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI | |
Persky et al. | The Hughes automated layout system-automated LSI/VLSI layout based on channel routing | |
Sato et al. | MIRAGE-A simple-model routing program for the hierarchical layout design of IC masks | |
Todd et al. | CGAL-A Multi Technology Gate Array Layout System | |
Hsueh | Symbolic layout compaction | |
Avenier | Digitizing, layout, rule checking—The everyday tasks of chip designers | |
Karatsu et al. | An integrated design automation system for VLSI circuits |